Pub Date : 2010-02-01DOI: 10.1109/TADVP.2008.2010525
A. Chinea, Student Member Ieee Piero Triverio, Senior Member Ieee Stefano Grivet-Talocia
We present a robust and efficient scheme for the generation of delay-based macromodels from frequency-domain tabulated responses. These responses can come from both simulation or direct measurement. The main algorithm is based on an iterative weighted least-squares process for the identification of delayed rational approximations. In case that pole relocation is performed during the iterations, the scheme can be interpreted as a generalization of the well-known vector fitting algorithm to delayed systems. Therefore, we denote this algorithm as delayed vector fitting (DVF). In case no pole relocation is performed, the scheme generalizes the so-called Sanathanan-Koerner iteration, calling for the denomination of delayed Sanathanan-Koerner algorithm. These techniques produce compact macromodels that are readily synthesized in SPICE-compatible equivalent circuits including delayed sources or ideal transmission line elements. These macromodels outperform classical rational macromodels in terms of simulation time. Several examples illustrate the advantages of proposed methodology.
{"title":"Delay-Based Macromodeling of Long Interconnects From Frequency-Domain Terminal Responses","authors":"A. Chinea, Student Member Ieee Piero Triverio, Senior Member Ieee Stefano Grivet-Talocia","doi":"10.1109/TADVP.2008.2010525","DOIUrl":"https://doi.org/10.1109/TADVP.2008.2010525","url":null,"abstract":"We present a robust and efficient scheme for the generation of delay-based macromodels from frequency-domain tabulated responses. These responses can come from both simulation or direct measurement. The main algorithm is based on an iterative weighted least-squares process for the identification of delayed rational approximations. In case that pole relocation is performed during the iterations, the scheme can be interpreted as a generalization of the well-known vector fitting algorithm to delayed systems. Therefore, we denote this algorithm as delayed vector fitting (DVF). In case no pole relocation is performed, the scheme generalizes the so-called Sanathanan-Koerner iteration, calling for the denomination of delayed Sanathanan-Koerner algorithm. These techniques produce compact macromodels that are readily synthesized in SPICE-compatible equivalent circuits including delayed sources or ideal transmission line elements. These macromodels outperform classical rational macromodels in terms of simulation time. Several examples illustrate the advantages of proposed methodology.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"220 1","pages":"246-256"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2008.2010525","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62384152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2034634
Jin Yang, I. C. Ume, Lizheng Zhang
Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages, and ball grid arrays, chips/packages are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. Solder bumps hidden between the chips/packages and the substrate/board are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometer techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chip packages, chip scale packages and land grid arrays. The system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response in nanometer scale on the package surface is measured using the interferometer technique. In this paper, wavelet analysis of laser ultrasound signals is presented and compared to previous signal processing methods, such as error ratio and correlation coefficient. The results show that wavelet analysis increases measurement sensitivity for inspecting solder bumps in electronic packages. Laser ultrasound inspection results are also compared to X-ray results. In particular, this paper discusses defect detection for a 6.35 mm × 6.35 mm × 0.6 mm PB18 flip chip package and flip chip package (¿SiMAF¿) with 24 lead-free solder bumps. These two types of flip chip specimens are both nonunderfilled.
微电子封装技术已经从通孔封装和批量封装发展到表面贴装封装和小轮廓封装。在表面贴装封装中，如倒装芯片、芯片级封装和球栅阵列，芯片/封装使用凸点连接连接到基板/印刷配线板(PWB)上。隐藏在芯片/封装和基板/电路板之间的焊料凸起在检查时不再可见。利用激光超声和干涉仪技术，研制了一种新型的凸点检测系统。该系统已成功应用于倒装芯片封装、芯片规模封装和地面网格阵列中焊点凸起缺陷的检测，包括缺失、不对准、打开和裂纹焊点缺陷。该系统采用脉冲Nd:YAG激光诱导热弹性超声，采用干涉仪技术测量了封装表面纳米尺度的瞬态面外位移响应。本文对激光超声信号进行了小波分析，并与以往的误差率、相关系数等信号处理方法进行了比较。结果表明，小波分析提高了电子封装中焊点检测的灵敏度。激光超声检查结果也与x射线结果进行比较。本文特别讨论了6.35 mm × 6.35 mm × 0.6 mm PB18倒装芯片封装和具有24个无铅焊点的倒装芯片封装(¿SiMAF¿)的缺陷检测。这两种类型的倒装芯片标本都是非欠填充的。
{"title":"Defect Detection of Flip Chip Solder Bumps With Wavelet Analysis of Laser Ultrasound Signals","authors":"Jin Yang, I. C. Ume, Lizheng Zhang","doi":"10.1109/TADVP.2009.2034634","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034634","url":null,"abstract":"Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages, and ball grid arrays, chips/packages are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. Solder bumps hidden between the chips/packages and the substrate/board are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometer techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chip packages, chip scale packages and land grid arrays. The system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response in nanometer scale on the package surface is measured using the interferometer technique. In this paper, wavelet analysis of laser ultrasound signals is presented and compared to previous signal processing methods, such as error ratio and correlation coefficient. The results show that wavelet analysis increases measurement sensitivity for inspecting solder bumps in electronic packages. Laser ultrasound inspection results are also compared to X-ray results. In particular, this paper discusses defect detection for a 6.35 mm × 6.35 mm × 0.6 mm PB18 flip chip package and flip chip package (¿SiMAF¿) with 24 lead-free solder bumps. These two types of flip chip specimens are both nonunderfilled.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"19-29"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034634","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2019965
B. Nouri, R. Achar, M. Nakhla
In this paper, novel z-domain orthonormal basis functions are presented for physical systems identification. The new basis functions yield guaranteed real-valued time-domain responses for physical systems containing both real and complex-conjugate poles. Also, application of the new basis functions is demonstrated by adopting them for z-domain orthogonal vector fitting algorithm. Necessary theoretical foundations and validating examples are presented.
{"title":"$z$ -Domain Orthonormal Basis Functions for Physical System Identifications","authors":"B. Nouri, R. Achar, M. Nakhla","doi":"10.1109/TADVP.2009.2019965","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2019965","url":null,"abstract":"In this paper, novel z-domain orthonormal basis functions are presented for physical systems identification. The new basis functions yield guaranteed real-valued time-domain responses for physical systems containing both real and complex-conjugate poles. Also, application of the new basis functions is demonstrated by adopting them for z-domain orthogonal vector fitting algorithm. Necessary theoretical foundations and validating examples are presented.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"293-307"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2019965","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62390048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2019844
H. Gan, D. Jiao
This paper proposes a hierarchical finite-element reduction-recovery method for large-scale transient analysis of high-speed integrated circuits. This method rigorously reduces the matrix of a multilayer system of O(N) to that of a single-cell system of O(1) regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. In addition, the reduction preserves the sparsity of the original system matrix. As a result, the matrix factorization cost is reduced to O(1) by the proposed method. The CPU cost at each time step scales linearly with the number of unknowns. The method is applicable to any Manhattan-type integrated circuit embedded in layered dielectric media. Numerical and experimental results demonstrate the performance of the proposed method.
{"title":"Hierarchical Finite-Element Reduction-Recovery Method for Large-Scale Transient Analysis of High-Speed Integrated Circuits","authors":"H. Gan, D. Jiao","doi":"10.1109/TADVP.2009.2019844","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2019844","url":null,"abstract":"This paper proposes a hierarchical finite-element reduction-recovery method for large-scale transient analysis of high-speed integrated circuits. This method rigorously reduces the matrix of a multilayer system of O(N) to that of a single-cell system of O(1) regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. In addition, the reduction preserves the sparsity of the original system matrix. As a result, the matrix factorization cost is reduced to O(1) by the proposed method. The CPU cost at each time step scales linearly with the number of unknowns. The method is applicable to any Manhattan-type integrated circuit embedded in layered dielectric media. Numerical and experimental results demonstrate the performance of the proposed method.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"276-284"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2019844","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62390257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2021156
B. Mohajer-Iravani, O. Ramahi
In this paper, we present a comprehensive equivalent circuit model to accurately characterize an important class of electromagnetic bandgap (EBG) structures over a wide range of frequencies. The model is developed based on a combination of lumped elements and transmission lines. The model presented here predicts with high degree of accuracy the dispersion diagram over a wide band of frequencies. Since the circuit model can be simulated using SPICE-like simulation tools, optimization of EBG structures to meet specific engineering criteria can be performed with high efficiency, thus saving significant computation time and memory resources. The model was validated by comparison to full-wave simulation results.
{"title":"Wideband Circuit Model for Planar EBG Structures","authors":"B. Mohajer-Iravani, O. Ramahi","doi":"10.1109/TADVP.2009.2021156","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2021156","url":null,"abstract":"In this paper, we present a comprehensive equivalent circuit model to accurately characterize an important class of electromagnetic bandgap (EBG) structures over a wide range of frequencies. The model is developed based on a combination of lumped elements and transmission lines. The model presented here predicts with high degree of accuracy the dispersion diagram over a wide band of frequencies. Since the circuit model can be simulated using SPICE-like simulation tools, optimization of EBG structures to meet specific engineering criteria can be performed with high efficiency, thus saving significant computation time and memory resources. The model was validated by comparison to full-wave simulation results.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"169-179"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2021156","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62390640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2025365
Qian Li, K. Melde
This paper compares four commonly used on-wafer calibration methods including multiline thru-reflect-line (TRL), line-reflect-reflect-match, line-reflect-match, and short-open-load- thru, for three diverse coplanar waveguide (CPW) circuits. The magnitudes and phases of S 11 and S 21 of the CPW circuits are compared to quantify how the specific calibration method influences measured scattering parameters. Special care is taken to ensure that the measured scattering parameters are normalized to the same reference impedance and reference plane for accurate comparison. The measured results are compared with full-wave simulations to provide additional assessment of accuracy. A method to de-embed the discontinuity of the CPW at the probe tip and the CPW of the test structures is presented. The effect of probe-to-device-under-test discontinuity is effectively modeled by one- or two- section of shunt capacitor and series inductor. The results show that the multiline TRL calibration method provides the highest transmission coefficient repeatability on not well-matched circuits and highest accuracy on the three circuits in this paper up to 40 GHz.
{"title":"The Impact of On-Wafer Calibration Method on the Measured Results of Coplanar Waveguide Circuits","authors":"Qian Li, K. Melde","doi":"10.1109/TADVP.2009.2025365","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2025365","url":null,"abstract":"This paper compares four commonly used on-wafer calibration methods including multiline thru-reflect-line (TRL), line-reflect-reflect-match, line-reflect-match, and short-open-load- thru, for three diverse coplanar waveguide (CPW) circuits. The magnitudes and phases of S 11 and S 21 of the CPW circuits are compared to quantify how the specific calibration method influences measured scattering parameters. Special care is taken to ensure that the measured scattering parameters are normalized to the same reference impedance and reference plane for accurate comparison. The measured results are compared with full-wave simulations to provide additional assessment of accuracy. A method to de-embed the discontinuity of the CPW at the probe tip and the CPW of the test structures is presented. The effect of probe-to-device-under-test discontinuity is effectively modeled by one- or two- section of shunt capacitor and series inductor. The results show that the multiline TRL calibration method provides the highest transmission coefficient repeatability on not well-matched circuits and highest accuracy on the three circuits in this paper up to 40 GHz.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"285-292"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2025365","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2033705
Jinwoo Choi, V. Govind, M. Swaminathan, K. Bharath
This paper presents efficient noise isolation and suppression method in mixed-signal systems using alternating impedance electromagnetic bandgap (AI-EBG) structure-based power distribution network (PDN). Currently, split planes are used for isolation in mixed-signal systems for isolating sensitive RF/analog circuits from noisy digital circuits. However, split planes show good isolation only at low frequencies due to electromagnetic coupling through the gap. The AI-EBG structure-based PDN presented in this paper provides excellent isolation (-80 dB ~ -100 dB) in the frequency range of interest by suppressing almost all possible electromagnetic modes. The AI-EBG structure has been integrated into a mixed-signal test vehicle to demonstrate the isolation level achievable. The ability of the AI-EBG structure to suppress switching noise has been quantified in this paper. The AI-EBG structure provided greater than 100 dB of isolation in passive S-parameter measurement and suppressed in-band noise down to -88 dBm of isolation in a functional test.
提出了基于交流阻抗电磁带隙(AI-EBG)结构的配电网络(PDN)在混合信号系统中有效的噪声隔离和抑制方法。目前，在混合信号系统中，分离平面用于隔离敏感的射频/模拟电路和噪声的数字电路。然而，由于通过间隙的电磁耦合，分裂平面仅在低频时表现出良好的隔离。本文提出的基于AI-EBG结构的PDN通过抑制几乎所有可能的电磁模式，在感兴趣的频率范围内提供了良好的隔离(-80 dB ~ -100 dB)。AI-EBG结构已集成到混合信号测试车辆中，以验证可实现的隔离级别。本文对AI-EBG结构抑制开关噪声的能力进行了量化。AI-EBG结构在被动s参数测量中提供了大于100 dB的隔离，在功能测试中将带内噪声抑制到-88 dBm的隔离。
{"title":"Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN)","authors":"Jinwoo Choi, V. Govind, M. Swaminathan, K. Bharath","doi":"10.1109/TADVP.2009.2033705","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033705","url":null,"abstract":"This paper presents efficient noise isolation and suppression method in mixed-signal systems using alternating impedance electromagnetic bandgap (AI-EBG) structure-based power distribution network (PDN). Currently, split planes are used for isolation in mixed-signal systems for isolating sensitive RF/analog circuits from noisy digital circuits. However, split planes show good isolation only at low frequencies due to electromagnetic coupling through the gap. The AI-EBG structure-based PDN presented in this paper provides excellent isolation (-80 dB ~ -100 dB) in the frequency range of interest by suppressing almost all possible electromagnetic modes. The AI-EBG structure has been integrated into a mixed-signal test vehicle to demonstrate the isolation level achievable. The ability of the AI-EBG structure to suppress switching noise has been quantified in this paper. The AI-EBG structure provided greater than 100 dB of isolation in passive S-parameter measurement and suppressed in-band noise down to -88 dBm of isolation in a functional test.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"2-12"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033705","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2033942
B. Lameres, C. McIntosh, M. Abusultan
This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.
{"title":"Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications","authors":"B. Lameres, C. McIntosh, M. Abusultan","doi":"10.1109/TADVP.2009.2033942","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033942","url":null,"abstract":"This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"37-47"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033942","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2015958
Shih-Hao Lee, Jianming Jin
The spatial discretization of a thin wire often leads to a highly dense mesh in the peripheral region and thus increases the computational burden. In this paper, lossy conducting wires are modeled with infinitely thin lumped impedance elements, which significantly reduce the modeling complexity while still offers an accurate broadband modeling. This paper also describes the incorporation of lumped elements into our model order reduction formulation and the tree-cotree splitting technique.
{"title":"Fast Reduced-Order Finite-Element Modeling of Lossy Thin Wires Using Lumped Impedance Elements","authors":"Shih-Hao Lee, Jianming Jin","doi":"10.1109/TADVP.2009.2015958","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2015958","url":null,"abstract":"The spatial discretization of a thin wire often leads to a highly dense mesh in the peripheral region and thus increases the computational burden. In this paper, lossy conducting wires are modeled with infinitely thin lumped impedance elements, which significantly reduce the modeling complexity while still offers an accurate broadband modeling. This paper also describes the incorporation of lumped elements into our model order reduction formulation and the tree-cotree splitting technique.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"212-218"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2015958","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62388744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2019843
Byung-gil Jeong, S. Ham, Chang-youl Moon, Byung-Sung Kim
With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-¿P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.
{"title":"Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device","authors":"Byung-gil Jeong, S. Ham, Chang-youl Moon, Byung-Sung Kim","doi":"10.1109/TADVP.2009.2019843","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2019843","url":null,"abstract":"With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-¿P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"64-71"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2019843","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62390142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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