Pub Date : 2020-01-28DOI: 10.1109/CJECE.2019.2938844
Sahib Khan, M. Irfan, Arslan Arif, Arslan Ali, Z. A. Memon, Aleem Khaliq
The secure exchange of secret information is one of the most important challenges in the era of modern communication. To address the issue and establish secure communication, various techniques have been developed. Transmitting secret information in a hidden manner is one of the numerous possible solutions. It can be used to transmit secret information, hidden in other media called cover medium. However, this increases the amount of transmittable data and bandwidth requirements. The work proposed technique is an effort to hide secret information in a cover medium to achieve secure communication, reduce the bandwidth requirement, and ensure the retrieval of secret information in full-strength. The proposed data hiding technique has a high data hiding capacity (HC), provides a high level of security, and results in high-quality stego images. The proposed technique, reversible-enhanced stego block chaining (RESBC), has demonstrated very good results as compared to the state-of-the-art steganography techniques. The RESBC successfully solves the data rate requirement of SBC. It has an improved security level of secret information as compared to the 4-least significant bits (4LSB) steganography. The RESBC has solved the problem of information recovery, associated with ESBC and ensures full health recovery.
{"title":"Reversible-Enhanced Stego Block Chaining Image Steganography: A Highly Efficient Data Hiding Technique","authors":"Sahib Khan, M. Irfan, Arslan Arif, Arslan Ali, Z. A. Memon, Aleem Khaliq","doi":"10.1109/CJECE.2019.2938844","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2938844","url":null,"abstract":"The secure exchange of secret information is one of the most important challenges in the era of modern communication. To address the issue and establish secure communication, various techniques have been developed. Transmitting secret information in a hidden manner is one of the numerous possible solutions. It can be used to transmit secret information, hidden in other media called cover medium. However, this increases the amount of transmittable data and bandwidth requirements. The work proposed technique is an effort to hide secret information in a cover medium to achieve secure communication, reduce the bandwidth requirement, and ensure the retrieval of secret information in full-strength. The proposed data hiding technique has a high data hiding capacity (HC), provides a high level of security, and results in high-quality stego images. The proposed technique, reversible-enhanced stego block chaining (RESBC), has demonstrated very good results as compared to the state-of-the-art steganography techniques. The RESBC successfully solves the data rate requirement of SBC. It has an improved security level of secret information as compared to the 4-least significant bits (4LSB) steganography. The RESBC has solved the problem of information recovery, associated with ESBC and ensures full health recovery.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2938844","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44950005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-28DOI: 10.1109/CJECE.2019.2949934
R. Muresan
This article presents an effective on-chip power analysis attack countermeasure based on a new CMOS self-decoupling battery cell system that uses a self-decoupling circuit. The self-decoupling circuit dynamically controls an on-chip virtual power supply point, $V_{mathrm {ddv}}$ , that can be used to power security-sensitive modules. The circuit automatically decouples an on-chip CMOS battery cell from powering a sensitive module when its voltage level reaches a designed minimum threshold level $V_{mathrm {dd-min}}$ and connects it for a very short charging cycle to the chip’s main voltage supply, $V_{mathrm {dd}}$ . The charging cycles for the experiments presented in this article are less than 10 ns and are designed to support the CMOS battery cell size and the minimum designed threshold voltage level $V_{mathrm {dd-min}}$ . Simulation results of test designs implemented in the 45-nm CMOS technology process show that the proposed countermeasure is efficient when used with battery cell sizes that can power the protected cryptographic module for more than ten data operation cycles before recharging. In addition, using the on-chip self-decoupling battery cell system allows for power consumption savings within the protected module of up to 43 % due to the dynamic voltage scaling generated at the virtual power supply point.
{"title":"On-Chip CMOS Self-Decoupling Battery Cell System for Security Protection","authors":"R. Muresan","doi":"10.1109/CJECE.2019.2949934","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2949934","url":null,"abstract":"This article presents an effective on-chip power analysis attack countermeasure based on a new CMOS self-decoupling battery cell system that uses a self-decoupling circuit. The self-decoupling circuit dynamically controls an on-chip virtual power supply point, <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {ddv}}$ </tex-math></inline-formula>, that can be used to power security-sensitive modules. The circuit automatically decouples an on-chip CMOS battery cell from powering a sensitive module when its voltage level reaches a designed minimum threshold level <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {dd-min}}$ </tex-math></inline-formula> and connects it for a very short charging cycle to the chip’s main voltage supply, <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {dd}}$ </tex-math></inline-formula>. The charging cycles for the experiments presented in this article are less than 10 ns and are designed to support the CMOS battery cell size and the minimum designed threshold voltage level <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {dd-min}}$ </tex-math></inline-formula>. Simulation results of test designs implemented in the 45-nm CMOS technology process show that the proposed countermeasure is efficient when used with battery cell sizes that can power the protected cryptographic module for more than ten data operation cycles before recharging. In addition, using the on-chip self-decoupling battery cell system allows for power consumption savings within the protected module of up to 43 % due to the dynamic voltage scaling generated at the virtual power supply point.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2949934","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45588966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2019.2950280
Ahmad Ehteram, Hossein Sabaghian-Bidgoli, H. Ghasvari, S. Hessabi
Due to the growing complexity of today’s digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and accuracy of the proposed algorithm are examined and evaluated using ISCAS85, ISCAS89, and ITC99 benchmark circuits. In order to assess the accuracy, the false-positive and false-negative detection of faults are counted for each benchmark circuit. The experimental results reveal considerable speedup as well as acceptable accuracy of the proposed approach in comparison with the traditional methods and commercial fault simulators.
{"title":"A Simple and Fast Solution for Fault Simulation Using Approximate Parallel Critical Path Tracing","authors":"Ahmad Ehteram, Hossein Sabaghian-Bidgoli, H. Ghasvari, S. Hessabi","doi":"10.1109/CJECE.2019.2950280","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2950280","url":null,"abstract":"Due to the growing complexity of today’s digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and accuracy of the proposed algorithm are examined and evaluated using ISCAS85, ISCAS89, and ITC99 benchmark circuits. In order to assess the accuracy, the false-positive and false-negative detection of faults are counted for each benchmark circuit. The experimental results reveal considerable speedup as well as acceptable accuracy of the proposed approach in comparison with the traditional methods and commercial fault simulators.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2950280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62192949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/cjece.2020.2970737
Ahmad Sghaier Omar, O. Basir
The smartphone industry is lucrative for device counterfeiting with over 1.5 billion devices sold annually in the last three years. In 2017, it is estimated that there were around 184 million counterfeit devices, valued at 45.3 billion EUR, 12.9% of total sales. Beyond its economic impact, smartphone counterfeiting affects various aspects of user security and privacy, harms manufacturer reputation, and degrades service quality. Furthermore, since smartphone devices are attached to different mobile networks globally, challenges arise on how devices’ identities are maintained and verified and how the supply chain actors can access the device identity throughout its life cycle with less control from third parties. Decentralized identifiers (DIDs) and verifiable claims implemented on a distributed ledger technology present a powerful candidate to address this challenge. Thanks to Blockchain’s use of cryptographic identifiers, record immutability, and provenance, and the features provided by the DIDs and verifiable claims that enable identity management decentralization, portability, and discoverability. This article proposes a smartphone anticounterfeiting system based on an integrated approach of the technologies mentioned above. The proposed system eliminates the need for a central authority and provides the features of identity creation, transfer of ownership, and the capability of fast and secure reporting of stolen devices.
{"title":"Decentralized Identifiers and Verifiable Credentials for Smartphone Anticounterfeiting and Decentralized IMEI Database","authors":"Ahmad Sghaier Omar, O. Basir","doi":"10.1109/cjece.2020.2970737","DOIUrl":"https://doi.org/10.1109/cjece.2020.2970737","url":null,"abstract":"The smartphone industry is lucrative for device counterfeiting with over 1.5 billion devices sold annually in the last three years. In 2017, it is estimated that there were around 184 million counterfeit devices, valued at 45.3 billion EUR, 12.9% of total sales. Beyond its economic impact, smartphone counterfeiting affects various aspects of user security and privacy, harms manufacturer reputation, and degrades service quality. Furthermore, since smartphone devices are attached to different mobile networks globally, challenges arise on how devices’ identities are maintained and verified and how the supply chain actors can access the device identity throughout its life cycle with less control from third parties. Decentralized identifiers (DIDs) and verifiable claims implemented on a distributed ledger technology present a powerful candidate to address this challenge. Thanks to Blockchain’s use of cryptographic identifiers, record immutability, and provenance, and the features provided by the DIDs and verifiable claims that enable identity management decentralization, portability, and discoverability. This article proposes a smartphone anticounterfeiting system based on an integrated approach of the technologies mentioned above. The proposed system eliminates the need for a central authority and provides the features of identity creation, transfer of ownership, and the capability of fast and secure reporting of stolen devices.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/cjece.2020.2970737","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62193405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2020.3005360
I. Zagan, V. Gaitan
The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.
{"title":"Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation","authors":"I. Zagan, V. Gaitan","doi":"10.1109/CJECE.2020.3005360","DOIUrl":"https://doi.org/10.1109/CJECE.2020.3005360","url":null,"abstract":"The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.3005360","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62193596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2019.2925780
Cristiane B. R. Ferreira, Fabrízzio Soares, H. Pedrini, Neil Bruce, William D. Ferreira, Gelson da Cruz
Digital images are found in several sizes and are easily displayed on a computer screen using techniques that can reduce their dimensions. Moreover, algorithms are used to process images to perform several tasks, for instance, detection of people. Recently, gigapixel images emerged, providing a huge amount of data; however, algorithms for people detection have been usually tested only on regular size images. This paper presents an impact analysis of the resolution reduction in the detection of people in gigapixel images. People detectors were trained with the INRIA and CALTECH data sets and results show that, although gigapixel images provide a huge false positive rate, the resolution reduction significantly decreases the number of bounding boxes and false positives, however, increasing the rate of missing people.
{"title":"A Study of Dimensionality Reduction Impact on an Approach to People Detection in Gigapixel Images","authors":"Cristiane B. R. Ferreira, Fabrízzio Soares, H. Pedrini, Neil Bruce, William D. Ferreira, Gelson da Cruz","doi":"10.1109/CJECE.2019.2925780","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2925780","url":null,"abstract":"Digital images are found in several sizes and are easily displayed on a computer screen using techniques that can reduce their dimensions. Moreover, algorithms are used to process images to perform several tasks, for instance, detection of people. Recently, gigapixel images emerged, providing a huge amount of data; however, algorithms for people detection have been usually tested only on regular size images. This paper presents an impact analysis of the resolution reduction in the detection of people in gigapixel images. People detectors were trained with the INRIA and CALTECH data sets and results show that, although gigapixel images provide a huge false positive rate, the resolution reduction significantly decreases the number of bounding boxes and false positives, however, increasing the rate of missing people.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2925780","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62192827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2019.2950133
Aditya Singh, C. Saavedra
A four-element frequency reconfigurable and pattern diverse multiple-input–multiple-output (MIMO) antenna array for fifth-generation relay node applications is presented to operate in LTE bands 42 (3400–3600 MHz), 43 (3600–3800 MHz), and 46 (5150–5925 MHz). A planar microstrip line-fed monopole antenna is utilized as the MIMO element. The antenna relies on fluidic reconfiguration mechanism to either serve LTE bands 42/43 or 46. It incorporates a substrate milled channel beneath each monopole arm to hold distilled water. The water in the channel perturbs the $E$ -field distribution in the vicinity of the antenna arm and modifies the effective permittivity of the dielectric medium. To realize pattern diversity, adjacent elements are placed orthogonal to each other. Measured prototype exhibits a total active reflection coefficient $|{text{TARC}}|$ and $|S_{11} |leq -10$ dB for the high band when the channel is vacant (case 1) and the low band when filled with water (case 2), while minimum isolation is above 19.6 dB. The peak measured gain is ~4.6 and ~2.8 dBi, while the worst case envelope correlation coefficient (ECC) is ~0.004 and ~0.016 for cases 1 and 2, respectively. It measures 82.4 $times$ 82.4 mm2 and was fabricated on a 1.52-mm-thick substrate of $epsilon_{r}$ = 3.55.
{"title":"Fluidically Reconfigurable MIMO Antenna With Pattern Diversity for Sub-6-GHz 5G Relay Node Applications","authors":"Aditya Singh, C. Saavedra","doi":"10.1109/CJECE.2019.2950133","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2950133","url":null,"abstract":"A four-element frequency reconfigurable and pattern diverse multiple-input–multiple-output (MIMO) antenna array for fifth-generation relay node applications is presented to operate in LTE bands 42 (3400–3600 MHz), 43 (3600–3800 MHz), and 46 (5150–5925 MHz). A planar microstrip line-fed monopole antenna is utilized as the MIMO element. The antenna relies on fluidic reconfiguration mechanism to either serve LTE bands 42/43 or 46. It incorporates a substrate milled channel beneath each monopole arm to hold distilled water. The water in the channel perturbs the <inline-formula> <tex-math notation=\"LaTeX\">$E$ </tex-math></inline-formula>-field distribution in the vicinity of the antenna arm and modifies the effective permittivity of the dielectric medium. To realize pattern diversity, adjacent elements are placed orthogonal to each other. Measured prototype exhibits a total active reflection coefficient <inline-formula> <tex-math notation=\"LaTeX\">$|{text{TARC}}|$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$|S_{11} |leq -10$ </tex-math></inline-formula> dB for the high band when the channel is vacant (case 1) and the low band when filled with water (case 2), while minimum isolation is above 19.6 dB. The peak measured gain is ~4.6 and ~2.8 dBi, while the worst case envelope correlation coefficient (ECC) is ~0.004 and ~0.016 for cases 1 and 2, respectively. It measures 82.4 <inline-formula> <tex-math notation=\"LaTeX\">$times$ </tex-math></inline-formula> 82.4 mm2 and was fabricated on a 1.52-mm-thick substrate of <inline-formula> <tex-math notation=\"LaTeX\">$epsilon_{r}$ </tex-math></inline-formula> = 3.55.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2950133","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62192914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2020.2966148
Muhammad Sifatul Alam Chowdhury, Xiaodong Liang
The introduction of wireless charging systems for electric vehicles (EVs) is a revolutionary step in the field of electrified transportation. Misalignments between transmitting and receiving power pads significantly affect the overall power transfer efficiency of an EV wireless charging system. In this article, a new power pad named “double D circular” (DDC) is designed. To evaluate the proposed DDC power pad design, its performance is compared with that of the existing circular and double D (DD) power pads by analyzing the power transfer efficiency in the wireless charging system considering different vertical and horizontal misalignments between the transmitting and receiving power pads. We use physical dimensions published in the Society of Automotive Engineers (SAE) J2954 recommended practice for existing circular and DD power pads in the simulation software, ANSYS Maxwell 3D. The influence of ferrite plates on the performance of power pads is also evaluated in the article.
{"title":"Design and Performance Evaluation for a New Power Pad in Electric Vehicles Wireless Charging Systems","authors":"Muhammad Sifatul Alam Chowdhury, Xiaodong Liang","doi":"10.1109/CJECE.2020.2966148","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2966148","url":null,"abstract":"The introduction of wireless charging systems for electric vehicles (EVs) is a revolutionary step in the field of electrified transportation. Misalignments between transmitting and receiving power pads significantly affect the overall power transfer efficiency of an EV wireless charging system. In this article, a new power pad named “double D circular” (DDC) is designed. To evaluate the proposed DDC power pad design, its performance is compared with that of the existing circular and double D (DD) power pads by analyzing the power transfer efficiency in the wireless charging system considering different vertical and horizontal misalignments between the transmitting and receiving power pads. We use physical dimensions published in the Society of Automotive Engineers (SAE) J2954 recommended practice for existing circular and DD power pads in the simulation software, ANSYS Maxwell 3D. The influence of ferrite plates on the performance of power pads is also evaluated in the article.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2966148","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62193079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2019.2914959
A. Yetgin
In induction motors, the leakage reactance values are obtained from the motor short circuit operation experiment. However, these values do not give clear results for different geometries. For this reason, taking into the parameters of the slot geometry accounts for determining the stator and rotor leakage reactance values that are important in terms of obtaining more accurate results. This paper has investigated the stator slot permeance values of nine different stator slot structures commonly used in industrial type of three-phase squirrel cage induction motors for obtaining the best starting torque. The stator inductance and leakage reactance values were calculated for each stator slot structure. The change of starting torque of the induction motor has been analyzed by using the MATLAB code. As a result of the analysis, the stator slot structure, which gives the best starting torque, has been obtained. It has been also shown that a 16% improvement can be achieved by changing the stator slot structure at the starting torque. This increase in the starting torque will provide a great advantage for the motor’s acceleration versus a heavy load.
{"title":"Investigation of the Effects of Stator Slot Permeance on Induction Motor and Obtaining the Best Starting Torque Using Permeance Calculation","authors":"A. Yetgin","doi":"10.1109/CJECE.2019.2914959","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2914959","url":null,"abstract":"In induction motors, the leakage reactance values are obtained from the motor short circuit operation experiment. However, these values do not give clear results for different geometries. For this reason, taking into the parameters of the slot geometry accounts for determining the stator and rotor leakage reactance values that are important in terms of obtaining more accurate results. This paper has investigated the stator slot permeance values of nine different stator slot structures commonly used in industrial type of three-phase squirrel cage induction motors for obtaining the best starting torque. The stator inductance and leakage reactance values were calculated for each stator slot structure. The change of starting torque of the induction motor has been analyzed by using the MATLAB code. As a result of the analysis, the stator slot structure, which gives the best starting torque, has been obtained. It has been also shown that a 16% improvement can be achieved by changing the stator slot structure at the starting torque. This increase in the starting torque will provide a great advantage for the motor’s acceleration versus a heavy load.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2914959","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62193215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.1109/CJECE.2020.3002243
Jiayi Fan, Yongkeun Lee
The demagnetization of switched reluctance motor (SRM) is usually a nonnegligible problem as the speed increases due to large back electromotive force (EMF). A slow demagnetization causes long tail current and negative torque, which reduces the efficiency and the output capability of SRM. In the conventional SRM design method, the inductance slope is normally designed to be high. However, it causes the problems of slow demagnetization in the negative torque region and low utilization efficiency of the torque-generative region. This article proposed a totally contrary way of SRM design, a small value of the inductance slope is chosen. Therefore, the effect of the back EMF can be diminished and the demagnetization is improved. The utilization of the torque-generative region is also improved due to the delayed turn-off angle. Simulation results are provided to verify the advantages of the proposed idea compared with the conventional one.
{"title":"A Concept of Accelerating the Demagnetization of Switched Reluctance Motor","authors":"Jiayi Fan, Yongkeun Lee","doi":"10.1109/CJECE.2020.3002243","DOIUrl":"https://doi.org/10.1109/CJECE.2020.3002243","url":null,"abstract":"The demagnetization of switched reluctance motor (SRM) is usually a nonnegligible problem as the speed increases due to large back electromotive force (EMF). A slow demagnetization causes long tail current and negative torque, which reduces the efficiency and the output capability of SRM. In the conventional SRM design method, the inductance slope is normally designed to be high. However, it causes the problems of slow demagnetization in the negative torque region and low utilization efficiency of the torque-generative region. This article proposed a totally contrary way of SRM design, a small value of the inductance slope is chosen. Therefore, the effect of the back EMF can be diminished and the demagnetization is improved. The utilization of the torque-generative region is also improved due to the delayed turn-off angle. Simulation results are provided to verify the advantages of the proposed idea compared with the conventional one.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.3002243","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62193509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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