A. Perelli, Carlo Caione, L. Marchi, D. Brunelli, A. Marzani, L. Benini
One of the popular structural health monitoring (SHM) applications of both automotive and aeronautic fields is devoted to the non-destructive localization of impacts in plate-like structures. The aim of this paper is to develop a miniaturized, self-contained and low power device for automated impact detection that can be used in a distributed fashion without central coordination. The proposed device uses an array of four piezoelectric transducers, bonded to the plate, capable to detect the guided waves generated by an impact, to a STM32F4 board equipped with an ARM Cortex-M4 microcontroller and a IEEE802.15.4 wireless transceiver. The waves processing and the localization algorithm are implemented on-board and optimized for speed and power consumption. In particular, the localization of the impact point is obtained by cross-correlating the signals related to the same event acquired by the different sensors in the warped frequency domain. Finally the performance of the whole system is analysed in terms of localization accuracy and power consumption, showing the effectiveness of the proposed implementation.
{"title":"Design of an ultra-low power device for aircraft structural health monitoring","authors":"A. Perelli, Carlo Caione, L. Marchi, D. Brunelli, A. Marzani, L. Benini","doi":"10.7873/DATE.2013.236","DOIUrl":"https://doi.org/10.7873/DATE.2013.236","url":null,"abstract":"One of the popular structural health monitoring (SHM) applications of both automotive and aeronautic fields is devoted to the non-destructive localization of impacts in plate-like structures. The aim of this paper is to develop a miniaturized, self-contained and low power device for automated impact detection that can be used in a distributed fashion without central coordination. The proposed device uses an array of four piezoelectric transducers, bonded to the plate, capable to detect the guided waves generated by an impact, to a STM32F4 board equipped with an ARM Cortex-M4 microcontroller and a IEEE802.15.4 wireless transceiver. The waves processing and the localization algorithm are implemented on-board and optimized for speed and power consumption. In particular, the localization of the impact point is obtained by cross-correlating the signals related to the same event acquired by the different sensors in the warped frequency domain. Finally the performance of the whole system is analysed in terms of localization accuracy and power consumption, showing the effectiveness of the proposed implementation.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"1127-1130"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75435008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Dogan, R. Braojos, J. Constantin, G. Ansaloni, A. Burg, David Atienza Alonso
Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instruction multiple data (SIMD) processing paradigm enables considerable power savings and application speedup, in turn allowing for a lower voltage supply for a given workload. The state-of-the-art multi-core architectures for biosignal analysis however lack a bare, yet smart, synchronization technique among the cores, allowing lockstep execution of algorithm parts that can be performed using the SIMD, even in the presence of data-dependent execution flows. In this paper, we propose a lightweight synchronization technique to enhance an ULP multi-core processor, resulting in improved energy efficiency through lockstep SIMD execution. Our results show that the proposed improvements accomplish tangible power savings, up to 64% for an 8-core system operating at a workload of 89 MOps/s while exploiting voltage scaling.
{"title":"Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms","authors":"A. Dogan, R. Braojos, J. Constantin, G. Ansaloni, A. Burg, David Atienza Alonso","doi":"10.7873/DATE.2013.090","DOIUrl":"https://doi.org/10.7873/DATE.2013.090","url":null,"abstract":"Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instruction multiple data (SIMD) processing paradigm enables considerable power savings and application speedup, in turn allowing for a lower voltage supply for a given workload. The state-of-the-art multi-core architectures for biosignal analysis however lack a bare, yet smart, synchronization technique among the cores, allowing lockstep execution of algorithm parts that can be performed using the SIMD, even in the presence of data-dependent execution flows. In this paper, we propose a lightweight synchronization technique to enhance an ULP multi-core processor, resulting in improved energy efficiency through lockstep SIMD execution. Our results show that the proposed improvements accomplish tangible power savings, up to 64% for an 8-core system operating at a workload of 89 MOps/s while exploiting voltage scaling.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"17 1","pages":"396-399"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73338611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gasser Ayad, A. Acquaviva, E. Macii, Brahim Sahbi, R. Lemaire
Recent trends in embedded system architectures brought a rapid shift towards multicore, heterogeneous and reconfigurable platforms. This imposes a large effort for programmers to develop their applications to efficiently exploit the underlying architecture. In addition, process variability issues lead to performance and power uncertainties, impacting expected quality of service and energy efficiency of the running software. In particular, variability may lead to sub-optimal runtime task allocation.
{"title":"HW-SW integration for energy-efficient/variability-aware computing","authors":"Gasser Ayad, A. Acquaviva, E. Macii, Brahim Sahbi, R. Lemaire","doi":"10.7873/DATE.2013.133","DOIUrl":"https://doi.org/10.7873/DATE.2013.133","url":null,"abstract":"Recent trends in embedded system architectures brought a rapid shift towards multicore, heterogeneous and reconfigurable platforms. This imposes a large effort for programmers to develop their applications to efficiently exploit the underlying architecture. In addition, process variability issues lead to performance and power uncertainties, impacting expected quality of service and energy efficiency of the running software. In particular, variability may lead to sub-optimal runtime task allocation.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"85 1","pages":"607-611"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74191863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between the through-silicon vias (TSVs) and silicon substrate, and the presence of elevated thermal gradients. To address the stress issue, we propose a thorough solution that combines design-time and run-time techniques for the relief of thermomechanical stress and the associated reliability issues. A sophisticated TSV stress-aware floorplan policy is proposed to minimize the possibility of wafer cracking and interfacial delamination. In addition, the run-time thermal management scheme effectively eliminates large thermal gradients between layers. The experimental results show that the reliability of 3D design can be significantly improved due to the reduced TSV thermal load and the elimination of mechanical damaging thermal cycling pattern.
{"title":"Thermomechanical stress-aware management for 3D IC designs","authors":"Qiaosha Zou, Zhang Tao, E. Kursun, Yuan Xie","doi":"10.7873/DATE.2013.260","DOIUrl":"https://doi.org/10.7873/DATE.2013.260","url":null,"abstract":"The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between the through-silicon vias (TSVs) and silicon substrate, and the presence of elevated thermal gradients. To address the stress issue, we propose a thorough solution that combines design-time and run-time techniques for the relief of thermomechanical stress and the associated reliability issues. A sophisticated TSV stress-aware floorplan policy is proposed to minimize the possibility of wafer cracking and interfacial delamination. In addition, the run-time thermal management scheme effectively eliminates large thermal gradients between layers. The experimental results show that the reliability of 3D design can be significantly improved due to the reduced TSV thermal load and the elimination of mechanical damaging thermal cycling pattern.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"12 1","pages":"1255-1258"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75088166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.
{"title":"An enhanced double-TSV scheme for defect tolerance in 3D-IC","authors":"Hsiu-Chuan Shih, Cheng-Wen Wu","doi":"10.7873/DATE.2013.302","DOIUrl":"https://doi.org/10.7873/DATE.2013.302","url":null,"abstract":"Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"94 12","pages":"1486-1489"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72616154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Joshi, A. Lombardot, M. Belleville, E. Beigné, S. Girard
A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.
{"title":"A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits","authors":"S. Joshi, A. Lombardot, M. Belleville, E. Beigné, S. Girard","doi":"10.7873/DATE.2013.221","DOIUrl":"https://doi.org/10.7873/DATE.2013.221","url":null,"abstract":"A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"280 1","pages":"1056-1057"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74955449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, R. David
The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, the STMicroelectronics/CEA Platform 2012 (P2012) project designed an area- and power-efficient many-core accelerator as an answer to the needs of computing power of next-generation data-intensive embedded applications. Synchronization handling on this architecture was critical since speed-ups of parallel implementations of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This paper presents the HardWare Synchronizer (HWS), a flexible hardware accelerator for synchronization operations in the P2012 architecture. Experiments on a multi-core test chip showed that the HWS has less than 1% area overhead while reducing synchronization latencies (up to 2.8 times) and contentions.
{"title":"An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture","authors":"F. Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, R. David","doi":"10.7873/DATE.2013.119","DOIUrl":"https://doi.org/10.7873/DATE.2013.119","url":null,"abstract":"The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, the STMicroelectronics/CEA Platform 2012 (P2012) project designed an area- and power-efficient many-core accelerator as an answer to the needs of computing power of next-generation data-intensive embedded applications. Synchronization handling on this architecture was critical since speed-ups of parallel implementations of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This paper presents the HardWare Synchronizer (HWS), a flexible hardware accelerator for synchronization operations in the P2012 architecture. Experiments on a multi-core test chip showed that the HWS has less than 1% area overhead while reducing synchronization latencies (up to 2.8 times) and contentions.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"83 1","pages":"531-534"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77648768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.
{"title":"Dynamic configuration prefetching based on piecewise linear prediction","authors":"A. Lifa, P. Eles, Zebo Peng","doi":"10.7873/DATE.2013.173","DOIUrl":"https://doi.org/10.7873/DATE.2013.173","url":null,"abstract":"Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"30 1","pages":"815-820"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78142709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many applications are inherently resilient to inexactness or approximations in their underlying computations. Approximate circuit design is an emerging paradigm that exploits this inherent resilience to realize hardware implementations that are highly efficient in energy or performance. In this work, we propose Substitute-And-SIMplIfy (SASIMI), a new systematic approach to the design and synthesis of approximate circuits. The key insight behind SASIMI is to identify signal pairs in the circuit that assume the same value with high probability, and substitute one for the other. While these substitutions introduce functional approximations, if performed judiciously, they result in some logic to be eliminated from the circuit while also enabling downsizing of gates on critical paths (simplification), resulting in significant power savings. We propose an automatic synthesis framework that performs substitution and simplification iteratively, while ensuring that a user-specified quality constraint is satisfied. We extend the proposed framework to perform automatic synthesis of quality configurable circuits that can dynamically operate at different accuracy levels depending on application requirements. We used SASIMI to automatically synthesize approximate and quality configurable implementations of a wide range of arithmetic units (Adders, Multipliers, MAC), complex data paths (SAD, FFT butterfly, Euclidean distance) and ISCAS85 benchmarks, using various error metrics such as error rate and average error magnitude. The synthesized approximate circuits demonstrate power improvements of 10%–28% for tight error constraints, and 30%–60% for relaxed error constraints. The quality configurable circuits obtain between 14%–40% improvement in energy in the approximate mode, while incurring no energy overheads in the accurate mode.
{"title":"Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits","authors":"Swagath Venkataramani, K. Roy, A. Raghunathan","doi":"10.7873/DATE.2013.280","DOIUrl":"https://doi.org/10.7873/DATE.2013.280","url":null,"abstract":"Many applications are inherently resilient to inexactness or approximations in their underlying computations. Approximate circuit design is an emerging paradigm that exploits this inherent resilience to realize hardware implementations that are highly efficient in energy or performance. In this work, we propose Substitute-And-SIMplIfy (SASIMI), a new systematic approach to the design and synthesis of approximate circuits. The key insight behind SASIMI is to identify signal pairs in the circuit that assume the same value with high probability, and substitute one for the other. While these substitutions introduce functional approximations, if performed judiciously, they result in some logic to be eliminated from the circuit while also enabling downsizing of gates on critical paths (simplification), resulting in significant power savings. We propose an automatic synthesis framework that performs substitution and simplification iteratively, while ensuring that a user-specified quality constraint is satisfied. We extend the proposed framework to perform automatic synthesis of quality configurable circuits that can dynamically operate at different accuracy levels depending on application requirements. We used SASIMI to automatically synthesize approximate and quality configurable implementations of a wide range of arithmetic units (Adders, Multipliers, MAC), complex data paths (SAD, FFT butterfly, Euclidean distance) and ISCAS85 benchmarks, using various error metrics such as error rate and average error magnitude. The synthesized approximate circuits demonstrate power improvements of 10%–28% for tight error constraints, and 30%–60% for relaxed error constraints. The quality configurable circuits obtain between 14%–40% improvement in energy in the approximate mode, while incurring no energy overheads in the accurate mode.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"60 1","pages":"1367-1372"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79805112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang, S. Jinglin
This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.
{"title":"A 100 GOPS ASP based baseband processor for wireless communication","authors":"Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang, S. Jinglin","doi":"10.7873/DATE.2013.038","DOIUrl":"https://doi.org/10.7873/DATE.2013.038","url":null,"abstract":"This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"6 1","pages":"121-124"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80529055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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