Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782655
Juan Quiros, J. Viejo, A. Millán, A. Muñoz, José Villar, D. Guerrero
This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that allow to administer the system. This environment requires a compact (specific dimensions) and low power and low cost device. Thus, a general purpose device (e.g. a PC) is discarded and an embedded one with these features has been developed. However, in addition to these requirements it offers a flexibility similar to the PC. Thereby it is able to update and carry out tasks beyond synchronization platform easily.
{"title":"Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA","authors":"Juan Quiros, J. Viejo, A. Millán, A. Muñoz, José Villar, D. Guerrero","doi":"10.1109/SPL.2011.5782655","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782655","url":null,"abstract":"This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that allow to administer the system. This environment requires a compact (specific dimensions) and low power and low cost device. Thus, a general purpose device (e.g. a PC) is discarded and an embedded one with these features has been developed. However, in addition to these requirements it offers a flexibility similar to the PC. Thereby it is able to update and carry out tasks beyond synchronization platform easily.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"24 1","pages":"239-244"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88508659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782628
Luis F. Castaño, G. Osorio
In this paper we present the design, implementation and experimental validation of a FPGA based position servo controller for a DC motor with dry friction. VHDL and block diagram modules for trajectory generation, encoder signal decoding, PI controller and PWM control signal generation are described. The control system is implemented in the DE3 board of Terasic Technologies Inc using Quartus II environment of Altera Corporation. Servo system simulation was made using Simulink. The analytical non linear model for the anti-windup saturation on the integral control action, saturation on the actuator and dry friction is validated through experiments and simulations.
{"title":"Design of a FPGA based position PI servo controller for a DC motor with dry friction","authors":"Luis F. Castaño, G. Osorio","doi":"10.1109/SPL.2011.5782628","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782628","url":null,"abstract":"In this paper we present the design, implementation and experimental validation of a FPGA based position servo controller for a DC motor with dry friction. VHDL and block diagram modules for trajectory generation, encoder signal decoding, PI controller and PWM control signal generation are described. The control system is implemented in the DE3 board of Terasic Technologies Inc using Quartus II environment of Altera Corporation. Servo system simulation was made using Simulink. The analytical non linear model for the anti-windup saturation on the integral control action, saturation on the actuator and dry friction is validated through experiments and simulations.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"41 1","pages":"75-80"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77103345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782643
W. Bast, D. Dellavale, F. Bonetto
The dynamic-clamp electrophysiological technique allows the mimicking of the electrical effects of ion channels embedded into the membrane of an intracellularly recorded cell. Dynamic-clamp relies on the establishing of a loop between the injected current and the recorded membrane potential. In this work, a real-time dynamic-clamp system was implemented on a Field Programmable Gate Array (FPGA). The system proposed allows the concurrent controlling of the activation of several ion channels. The architecture of the instrument developed is based on two main modules: a state machine (as the logic arbiter) with the ADC and DAC interface, and a signal processing module. The state machine controls the converters along with the serial data-transfer interface (SPI). The signal processing module implements the algorithms needed to mimic several HH-type ion channel conductances. Extensive simulations of the device operation were made, showing that the instrument developed implements effectively the dynamic-clamp control loop, with a maximum operation frequency of 532 kHZ. The main application of this instrument is the manipulation of ion channels.
{"title":"FPGA implementation of a “dynamic-clamp” system","authors":"W. Bast, D. Dellavale, F. Bonetto","doi":"10.1109/SPL.2011.5782643","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782643","url":null,"abstract":"The dynamic-clamp electrophysiological technique allows the mimicking of the electrical effects of ion channels embedded into the membrane of an intracellularly recorded cell. Dynamic-clamp relies on the establishing of a loop between the injected current and the recorded membrane potential. In this work, a real-time dynamic-clamp system was implemented on a Field Programmable Gate Array (FPGA). The system proposed allows the concurrent controlling of the activation of several ion channels. The architecture of the instrument developed is based on two main modules: a state machine (as the logic arbiter) with the ADC and DAC interface, and a signal processing module. The state machine controls the converters along with the serial data-transfer interface (SPI). The signal processing module implements the algorithms needed to mimic several HH-type ion channel conductances. Extensive simulations of the device operation were made, showing that the instrument developed implements effectively the dynamic-clamp control loop, with a maximum operation frequency of 532 kHZ. The main application of this instrument is the manipulation of ion channels.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"26 1","pages":"167-172"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84669871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782624
J. Alves, P. Diniz
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources.
{"title":"Custom FPGA-based micro-architecture for streaming computing","authors":"J. Alves, P. Diniz","doi":"10.1109/SPL.2011.5782624","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782624","url":null,"abstract":"This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"62 1","pages":"51-56"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84747329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782636
D. L. Oliveira, E. Lussari
Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used to implement circuits in FPGAs (Field Programmable Gate Array). Although these devices have the benefits of low-cost and short development time, there's a major drawback which is implementing Asynchronous Interfaces (AI) in FPGA devices. There's a typical AI design style which is based on asynchronous controllers that provides communication between modules (called ports), but Port controllers are subject to essential-hazard when implemented FPGAs. This paper proposes a method based on direct mapping to implement these ports. It begins with an MBG (multi-burst graph) specification and makes use of the essential signal concept to check if the resulting circuit is hazard-free, or to point potential essential-hazard problems in the circuit. By satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.
{"title":"Synthesis of robust controllers for GALS_FPGA from multi-burst graph specification","authors":"D. L. Oliveira, E. Lussari","doi":"10.1109/SPL.2011.5782636","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782636","url":null,"abstract":"Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used to implement circuits in FPGAs (Field Programmable Gate Array). Although these devices have the benefits of low-cost and short development time, there's a major drawback which is implementing Asynchronous Interfaces (AI) in FPGA devices. There's a typical AI design style which is based on asynchronous controllers that provides communication between modules (called ports), but Port controllers are subject to essential-hazard when implemented FPGAs. This paper proposes a method based on direct mapping to implement these ports. It begins with an MBG (multi-burst graph) specification and makes use of the essential signal concept to check if the resulting circuit is hazard-free, or to point potential essential-hazard problems in the circuit. By satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"79 1","pages":"123-129"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90666676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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