Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782635
J. I. Villar, J. Juan, M. Bellido, J. Viejo, D. Guerrero, J. Decaluwe
Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study. This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral. The use of MyHDL has revealed to be a powerful and promising tool, not only because of the surprising results, but also because it opens new horizons towards the development of new techniques for modeling and verification, using the full power of one of the most versatile programming languages nowadays.
{"title":"Python as a hardware description language: A case study","authors":"J. I. Villar, J. Juan, M. Bellido, J. Viejo, D. Guerrero, J. Decaluwe","doi":"10.1109/SPL.2011.5782635","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782635","url":null,"abstract":"Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study. This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral. The use of MyHDL has revealed to be a powerful and promising tool, not only because of the surprising results, but also because it opens new horizons towards the development of new techniques for modeling and verification, using the full power of one of the most versatile programming languages nowadays.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87749743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782649
Sunil Malipatlolla, S. Huss
The configuration data sequence of a Field Programmable Gate Array (FPGA) is an Intellectual Property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the Dynamic Partial Reconfiguration (Dynamic PR) feature of an SRAM-based FPGA with the Public Key Cryptography (PKC) to protect the FPGA configuration files without the need of fixed key storage on FPGA or external to FPGA. The proposed method, is secure against the known attacks such as the Man-In-The-Middle (MITM) attack and replay attack. Therefore, the method can be used for secure deploying of IPs from local and remote vendors. Also, using this novel method not only high-end FPGAs but also low-end FPGAs with PR capabilities are secured.
{"title":"A novel method for secure intellectual property deployment in embedded systems","authors":"Sunil Malipatlolla, S. Huss","doi":"10.1109/SPL.2011.5782649","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782649","url":null,"abstract":"The configuration data sequence of a Field Programmable Gate Array (FPGA) is an Intellectual Property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the Dynamic Partial Reconfiguration (Dynamic PR) feature of an SRAM-based FPGA with the Public Key Cryptography (PKC) to protect the FPGA configuration files without the need of fixed key storage on FPGA or external to FPGA. The proposed method, is secure against the known attacks such as the Man-In-The-Middle (MITM) attack and replay attack. Therefore, the method can be used for secure deploying of IPs from local and remote vendors. Also, using this novel method not only high-end FPGAs but also low-end FPGAs with PR capabilities are secured.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75557020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782651
A. Ehliar, J. Siverskog
This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.
{"title":"Using partial reconfigurability to aid debugging of FPGA designs","authors":"A. Ehliar, J. Siverskog","doi":"10.1109/SPL.2011.5782651","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782651","url":null,"abstract":"This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72548600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782645
T. Silva, Marcilyanne Moreira Gois, Paulo Matias, A. Delbem, E. Marques, Vanderlei Bonato
Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary algorithms have been investigated. Recently, researches have shown that the performance of evolutionary algorithms for network design problems can be significantly increased by means of more appropriate dynamic data structures (encodings). To achieve high performance, we parallelized the application via a dynamic data structure, called node-depth encoding for representation of a set (population) of spanning forests. This paper proposes an FPGA-based hardware architecture, denominated Hardware-Parallelized NDE (HPNDE), which is able to generate spanning trees (forests) in a constant average running time O(1), enabling its application in real large-scale problems, given an FPGA with enough resources to implement such structure. The parallelized approach is 1.5k times faster than its sequential counterpart.
{"title":"Spanning forests in constant time using FPGAS applied to network design problems","authors":"T. Silva, Marcilyanne Moreira Gois, Paulo Matias, A. Delbem, E. Marques, Vanderlei Bonato","doi":"10.1109/SPL.2011.5782645","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782645","url":null,"abstract":"Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary algorithms have been investigated. Recently, researches have shown that the performance of evolutionary algorithms for network design problems can be significantly increased by means of more appropriate dynamic data structures (encodings). To achieve high performance, we parallelized the application via a dynamic data structure, called node-depth encoding for representation of a set (population) of spanning forests. This paper proposes an FPGA-based hardware architecture, denominated Hardware-Parallelized NDE (HPNDE), which is able to generate spanning trees (forests) in a constant average running time O(1), enabling its application in real large-scale problems, given an FPGA with enough resources to implement such structure. The parallelized approach is 1.5k times faster than its sequential counterpart.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87960648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782621
P. Gianni, H. Carrer, G. Corral-Briones, M. Hueda
This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.
{"title":"A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems","authors":"P. Gianni, H. Carrer, G. Corral-Briones, M. Hueda","doi":"10.1109/SPL.2011.5782621","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782621","url":null,"abstract":"This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91313252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782652
W. Kuang, Yu Bai
In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that it is much easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.
{"title":"Soft error in FPGA-implemented asynchronous circuits","authors":"W. Kuang, Yu Bai","doi":"10.1109/SPL.2011.5782652","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782652","url":null,"abstract":"In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that it is much easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73472787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782634
O. Goni, M. Vazquez, E. Todorovich, G. Sutter
This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independent of the ALU operand representation and IEEE754-2008 specific modules were also implemented. Verification results, the experience itself, and a comparative study of the alternatives was made and summarized for designers and verification engineers.
{"title":"Experiences applying framework-based functional verification to a design for programmable logic","authors":"O. Goni, M. Vazquez, E. Todorovich, G. Sutter","doi":"10.1109/SPL.2011.5782634","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782634","url":null,"abstract":"This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independent of the ALU operand representation and IEEE754-2008 specific modules were also implemented. Verification results, the experience itself, and a comparative study of the alternatives was made and summarized for designers and verification engineers.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73871780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782654
Juan Augusto Maya, Nicolas A. Casco, P. A. Roncagliolo, Javier G. García
In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.
{"title":"A high data rate BPSK receiver implementation in FPGA for high dynamics applications","authors":"Juan Augusto Maya, Nicolas A. Casco, P. A. Roncagliolo, Javier G. García","doi":"10.1109/SPL.2011.5782654","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782654","url":null,"abstract":"In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76175267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782658
M. Véstias, H. Neto
The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the importance of decimal arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations. A few hardware approaches have been proposed for decimal arithmetic, including addition, subtraction, multiplication and division. Parallel implementations for these operations are very expensive in terms of occupied resources and therefore implementations based on iterative algorithms are good alternatives. In this paper, we propose an iterative decimal multiplier for FPGA that uses binary arithmetic. The circuits were implemented in a Xilinx Virtex 4 FPGA. The results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.
{"title":"Iterative decimal multiplication using binary arithmetic","authors":"M. Véstias, H. Neto","doi":"10.1109/SPL.2011.5782658","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782658","url":null,"abstract":"The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the importance of decimal arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations. A few hardware approaches have been proposed for decimal arithmetic, including addition, subtraction, multiplication and division. Parallel implementations for these operations are very expensive in terms of occupied resources and therefore implementations based on iterative algorithms are good alternatives. In this paper, we propose an iterative decimal multiplier for FPGA that uses binary arithmetic. The circuits were implemented in a Xilinx Virtex 4 FPGA. The results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90519994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782631
Sagnik Mukhopadhyay, Pritha Banerjee, S. Sur-Kolay
In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.
{"title":"Balanced bipartitioning of a multi-weighted hypergraph for heterogeneous FPGAS","authors":"Sagnik Mukhopadhyay, Pritha Banerjee, S. Sur-Kolay","doi":"10.1109/SPL.2011.5782631","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782631","url":null,"abstract":"In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88925550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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