Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782644
D. Muñoz, C. Llanos, L. Coelho, M. Ayala-Rincón
Achieving high performance optimization algorithms for embedded applications can be very challenging, particularly when several requirements such as high accuracy computations, short elapsed time, area cost, low power consumption and portability must be accomplished. This paper proposes a hardware implementation of the Particle Swarm Optimization algorithm with passive congregation (HPPSOpc), which was developed using several floating-point arithmetic libraries. The passive congregation is a biological behavior which allows the swarm to preserve its integrity, balancing between global and local search. The HPPSOpc architecture was implemented on a Virtex5 FPGA device and validated using two multimodal benchmark problems. Synthesis, simulation and execution time results demonstrates that the passive congregation approach is a low cost solution for solving embedded optimization problems with a high performance.
{"title":"Hardware Particle Swarm Optimization with passive congregation for embedded applications","authors":"D. Muñoz, C. Llanos, L. Coelho, M. Ayala-Rincón","doi":"10.1109/SPL.2011.5782644","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782644","url":null,"abstract":"Achieving high performance optimization algorithms for embedded applications can be very challenging, particularly when several requirements such as high accuracy computations, short elapsed time, area cost, low power consumption and portability must be accomplished. This paper proposes a hardware implementation of the Particle Swarm Optimization algorithm with passive congregation (HPPSOpc), which was developed using several floating-point arithmetic libraries. The passive congregation is a biological behavior which allows the swarm to preserve its integrity, balancing between global and local search. The HPPSOpc architecture was implemented on a Virtex5 FPGA device and validated using two multimodal benchmark problems. Synthesis, simulation and execution time results demonstrates that the passive congregation approach is a low cost solution for solving embedded optimization problems with a high performance.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"26 1","pages":"173-178"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87902370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782630
J. Oliver, E. Boemo
This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.
本文介绍了65nm Cyclone III FPGA核心逻辑功耗的实验测量，并与功耗估计工具预测值进行了比较。描述了实验室工作，包括测量设置，基准电路和用于获得功率估计的CAD流程。所选电路用作基准是在lut和嵌入式块中实现的不同类型的乘法器，有或没有流水线阶段。给出了三类结果:一是功率测量值与功率估计值之间的误差;第二，采用流水线分段的节能，第三，采用嵌入式模块的节能量化。
{"title":"Power estimations vs. power measurements in Cyclone III devices","authors":"J. Oliver, E. Boemo","doi":"10.1109/SPL.2011.5782630","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782630","url":null,"abstract":"This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"23 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85104703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782640
Diego Sanchez-Roman, G. Sutter, S. López-Buedo, Iván González, Francisco J. Gómez-Arribas, J. Aracil
This paper addresses the problem of accelerating Computational Fluid Dynamics (CFD) applications, utilized by aeronautical engineers to create more efficient and aerodynamic designs. CFD applications require intensive floating point calculations, so they are usually executed on High-Performance Computing (HPC) systems. Here, we study the HW implementation of a cell-vertex finite volume algorithm to solve Euler equations, using the XtremeData XD2000i in-socket FPGA accelerator. Taking advantage of high-level language synthesis tools together with optimized low level components, a HW-accelerated implementation that achieved speedups up to 13.25x could be created in a short time.
{"title":"An Euler solver accelerator in FPGA for computational fluid dynamics applications","authors":"Diego Sanchez-Roman, G. Sutter, S. López-Buedo, Iván González, Francisco J. Gómez-Arribas, J. Aracil","doi":"10.1109/SPL.2011.5782640","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782640","url":null,"abstract":"This paper addresses the problem of accelerating Computational Fluid Dynamics (CFD) applications, utilized by aeronautical engineers to create more efficient and aerodynamic designs. CFD applications require intensive floating point calculations, so they are usually executed on High-Performance Computing (HPC) systems. Here, we study the HW implementation of a cell-vertex finite volume algorithm to solve Euler equations, using the XtremeData XD2000i in-socket FPGA accelerator. Taking advantage of high-level language synthesis tools together with optimized low level components, a HW-accelerated implementation that achieved speedups up to 13.25x could be created in a short time.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"35 1","pages":"149-154"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77792541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782617
J. Castiñeira Moreira, M. Rabini, C. Gonzalez, C. A. Gayoso, L. Arnone
Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.
{"title":"FPGA implementation of two very low complexity LDPC decoders","authors":"J. Castiñeira Moreira, M. Rabini, C. Gonzalez, C. A. Gayoso, L. Arnone","doi":"10.1109/SPL.2011.5782617","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782617","url":null,"abstract":"Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"76 1","pages":"7-12"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76342517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782641
G. Marcus, Wenxue Gao, A. Kugel, R. Manner
We present an open source stack for the development of custom FPGA boards, primarily but not limited to PCI Express interconnects. Supporting current Linux distributions, the stack consists of a PCI driver, an IP core for a DMA engine, a hardware abstraction library for IO operations, and a buffer management library for efficient handling of data transfers between an application and a FPGA design. The stack has been validated in diverse hardware and software platforms and provides several building blocks that facilitate the use of accelerators in applications. The DMA Engine IP provides high performance data transfers in PCIe 4-lane boards with Xilinx PCIe cores, with 380 MB/s read and 700 MB/s write maximum measured performance. The buffer management library allows the utilization of 80–95% of this bandwidth with reduced resource consumption and minimal effort.
{"title":"The MPRACE framework: An open source stack for communication with custom FPGA-based accelerators","authors":"G. Marcus, Wenxue Gao, A. Kugel, R. Manner","doi":"10.1109/SPL.2011.5782641","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782641","url":null,"abstract":"We present an open source stack for the development of custom FPGA boards, primarily but not limited to PCI Express interconnects. Supporting current Linux distributions, the stack consists of a PCI driver, an IP core for a DMA engine, a hardware abstraction library for IO operations, and a buffer management library for efficient handling of data transfers between an application and a FPGA design. The stack has been validated in diverse hardware and software platforms and provides several building blocks that facilitate the use of accelerators in applications. The DMA Engine IP provides high performance data transfers in PCIe 4-lane boards with Xilinx PCIe cores, with 380 MB/s read and 700 MB/s write maximum measured performance. The buffer management library allows the utilization of 80–95% of this bandwidth with reduced resource consumption and minimal effort.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"99 1","pages":"155-160"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90265459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782627
Juan Pablo Tettamanti, A. Latini, M. Aguirre
This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a reference frame for grid synchronization. The performance of proposed PLL structure and logic control is simulated via Matlab/Simulink. The proposed PLL structure shows fast synchronization and adequate tolerance to grid voltage unbalance. Both the PLL and the control logic can be downloaded and tested on a Field-Programmable-Gate-Array (FPGA) using the same software tool.
{"title":"An example of rapid design of power electronics control with FPGA in Matlab/Simulink","authors":"Juan Pablo Tettamanti, A. Latini, M. Aguirre","doi":"10.1109/SPL.2011.5782627","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782627","url":null,"abstract":"This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a reference frame for grid synchronization. The performance of proposed PLL structure and logic control is simulated via Matlab/Simulink. The proposed PLL structure shows fast synchronization and adequate tolerance to grid voltage unbalance. Both the PLL and the control logic can be downloaded and tested on a Field-Programmable-Gate-Array (FPGA) using the same software tool.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"23 1","pages":"69-74"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83205653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782648
E. C. Pedrino, O. Morandin, E. Kato, V. O. Roda
Mathematical morphology supplies powerful tools for low level image analysis, with applications in many areas. In this paper, the development of a novel reconfigurable hardware using a genetic algorithm and a pipeline architecture is proposed for the task of shape recognition in binary images. For the recognition process, a large sized convex structuring element representing the object shape to be recognized is decomposed into the architecture stages. Each stage can handle structuring elements of a limited size. In this approach, a genetic algorithm was used to decompose this structuring element. Thus, a simple erosion performed in each stage is used to detect the goal object. The hardware is capable of processing binary images at high speed. The developed system is based on FPGAs. Our approach represents an intelligent mechanism to reconfigure the pipeline architecture, it is different from other systems found in the literature, and the obtained results are promising.
{"title":"Intelligent FPGA based system for shape recognition","authors":"E. C. Pedrino, O. Morandin, E. Kato, V. O. Roda","doi":"10.1109/SPL.2011.5782648","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782648","url":null,"abstract":"Mathematical morphology supplies powerful tools for low level image analysis, with applications in many areas. In this paper, the development of a novel reconfigurable hardware using a genetic algorithm and a pipeline architecture is proposed for the task of shape recognition in binary images. For the recognition process, a large sized convex structuring element representing the object shape to be recognized is decomposed into the architecture stages. Each stage can handle structuring elements of a limited size. In this approach, a genetic algorithm was used to decompose this structuring element. Thus, a simple erosion performed in each stage is used to detect the goal object. The hardware is capable of processing binary images at high speed. The developed system is based on FPGAs. Our approach represents an intelligent mechanism to reconfigure the pipeline architecture, it is different from other systems found in the literature, and the obtained results are promising.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"8 1","pages":"197-202"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88380504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782642
C. Sisterna, Marcelo J. Segura, Martin Guzzo, Gustavo Ensinck, Carlos Gil
Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.
{"title":"FPGA implementation of an ultra-high speed ADC interface","authors":"C. Sisterna, Marcelo J. Segura, Martin Guzzo, Gustavo Ensinck, Carlos Gil","doi":"10.1109/SPL.2011.5782642","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782642","url":null,"abstract":"Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"33 1","pages":"161-166"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86477182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782653
M. Véstias, H. Neto
Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. In this paper, we analyze the buffer resize approaches applied to FPGA and propose a buffer resize technique. The results show that the technique improves the area and the performance of the architecture on FPGA but is less efficient than ASIC implementations.
{"title":"A dynamic buffer resize technique for networks-on-chip on FPGA","authors":"M. Véstias, H. Neto","doi":"10.1109/SPL.2011.5782653","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782653","url":null,"abstract":"Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. In this paper, we analyze the buffer resize approaches applied to FPGA and propose a buffer resize technique. The results show that the technique improves the area and the performance of the architecture on FPGA but is less efficient than ASIC implementations.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"270 1","pages":"227-232"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82798278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/SPL.2011.5782647
Emna Amouri, Z. Marrakchi, H. Mehrez
The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.
{"title":"Security-centric FPGA CAD tools to balance dual-rail routing INWDDL designs","authors":"Emna Amouri, Z. Marrakchi, H. Mehrez","doi":"10.1109/SPL.2011.5782647","DOIUrl":"https://doi.org/10.1109/SPL.2011.5782647","url":null,"abstract":"The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"51 1","pages":"191-196"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88047735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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