Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615587
S. Isono, T. Satake, T. Hyakushima, K. Taki, R. Sakaida, S. Kishimura, S. Hirao, K. Nomura, N. Torazawa, M. Tsutsue, T. Ueda
A stacked image sensor with a 0.9 μm pixel size fabricated by using organic photoconductive film (OPF) was realized. It is the first trial to introduce an active material, that is, an organic semiconductor into the BEOL process. This pixel structure is fabricated by using a standard 45 nm BEOL process. However, after OPF deposition, it is essential to restrict the thermal budget and to avoid oxygen, moisture, and plasma irradiation. By controlling the above conditions, a demonstration of a stacked image sensor with OPF, which has high sensitivity, high saturation charge, and a wide incident light angle, was successfully performed.
{"title":"A 0.9 µm pixel size image sensor realized by introducing organic photoconductive film into the BEOL process","authors":"S. Isono, T. Satake, T. Hyakushima, K. Taki, R. Sakaida, S. Kishimura, S. Hirao, K. Nomura, N. Torazawa, M. Tsutsue, T. Ueda","doi":"10.1109/IITC.2013.6615587","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615587","url":null,"abstract":"A stacked image sensor with a 0.9 μm pixel size fabricated by using organic photoconductive film (OPF) was realized. It is the first trial to introduce an active material, that is, an organic semiconductor into the BEOL process. This pixel structure is fabricated by using a standard 45 nm BEOL process. However, after OPF deposition, it is essential to restrict the thermal budget and to avoid oxygen, moisture, and plasma irradiation. By controlling the above conditions, a demonstration of a stacked image sensor with OPF, which has high sensitivity, high saturation charge, and a wide incident light angle, was successfully performed.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"51 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78546880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615558
Chirag Shah, A. Karmarkar, Xiaopeng Xu
A novel simulation approach is developed to examine the stress evolution in the chip-to-package interconnect structures during the sequential IC Backend processes followed by packaging / assembly operation. Packaging induced stress in near-bump and BEOL level models is examined using the multi-level FEA methodology. Likewise, the Backend process induced stresses in the interconnect structures is analyzed using a sequential process simulation that looks into stress evolution of the BEOL structure as each metal-dielectric layer is being patterned. Finally, the cumulative impact of packaging induced stress and the BEOL process induced stress on the interconnect structures is examined to demonstrate the significance of this approach in performing a “design dependent” CPI risk analysis for BEOL interconnects.
{"title":"Modeling of interconnect stress evolution during BEOL process and packaging","authors":"Chirag Shah, A. Karmarkar, Xiaopeng Xu","doi":"10.1109/IITC.2013.6615558","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615558","url":null,"abstract":"A novel simulation approach is developed to examine the stress evolution in the chip-to-package interconnect structures during the sequential IC Backend processes followed by packaging / assembly operation. Packaging induced stress in near-bump and BEOL level models is examined using the multi-level FEA methodology. Likewise, the Backend process induced stresses in the interconnect structures is analyzed using a sequential process simulation that looks into stress evolution of the BEOL structure as each metal-dielectric layer is being patterned. Finally, the cumulative impact of packaging induced stress and the BEOL process induced stress on the interconnect structures is examined to demonstrate the significance of this approach in performing a “design dependent” CPI risk analysis for BEOL interconnects.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"374 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80540375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615598
T. Mourier, C. Ribiére, G. Romero, M. Gottardi, N. Allouti, R. Eleouet, A. Roman, T. Magis, S. Minoret, C. Ratin, D. Scevola, E. Dupuy, B. Martin, L. Gabette, D. Marseilhan, T. Enot, M. Pellat, V. Loup, R. Segaud, H. Feldis, A. Charpentier, J. Bally, M. Assous, I. Charbonnier, C. Laviron, P. Coudrain, N. Sillon
3D integration, also referred as “More than Moore” approach is considered as the most attractive alternative to “More Moore” concept in order to increase circuit functionalities and performances while keeping reasonable cost of integrated devices. This technology has been widely presented and discussed during last years and is now available on several world wide integration platforms. Major part of the work done in recent years was focused on the three challenges to be overcome to allow manufacturing of 3D technology: design, process integration and tests. This was presented [1] as the availability of a complete toolbox including the design kit definition, the development and maturity increasing of the required process modules such as TSV, Wafer bonding and debonding, back side contact, both side interconnects and the definition of functional and reliability tests. This toolbox is dedicated to the construction of specific process flows and designs depending on the targeted applications. These applications, in the 3D integration world, are very flexible going from the passive and active interposers to memory on logic or logic on logic partitioning as well as stackable processors. Today, the different process modules are at a sufficient maturity state to allow the realization of demonstrators for all types of integration schemes. Depending on the type of integration flow and requested device, challenges to perform this demonstrator can come from the process integration itself but also from the need of specific equipment toolset. Base wafers already containing devices for 3D demonstrator can come from various site and be of different size. The demonstrator can be fully realized from bulk silicon as it is the case for an interposer or the 3D part of the device, only, will have to be developed which will be the case for heterogeneous integration. For this, a new 300 mm pilot line was built in Leti in addition to the 200 mm one and was designed to be compatible with manufacturing lines. These facilities are today allowing the realization of 300 mm 3D demonstrators. Results of these prototypes and the challenges overcome for integration are discussed in this paper.
3D集成，也被称为“More than Moore”方法，被认为是“More Moore”概念的最有吸引力的替代方案，以增加电路功能和性能，同时保持集成器件的合理成本。该技术在过去几年中得到了广泛的介绍和讨论，目前已在几个全球集成平台上可用。近年来所做的主要工作集中在实现3D技术制造需要克服的三个挑战:设计、工艺集成和测试。这被提出[1]作为一个完整工具箱的可用性，包括设计工具包的定义，所需工艺模块的开发和成熟度的提高，如TSV，晶圆键合和去键合，背面接触，两侧互连以及功能和可靠性测试的定义。此工具箱专门用于根据目标应用程序构建特定的流程流和设计。在3D集成领域中，这些应用程序非常灵活，从被动和主动中介器到逻辑上的内存或逻辑上的逻辑分区以及可堆叠处理器。如今，不同的流程模块处于足够成熟的状态，可以为所有类型的集成方案实现演示。根据集成流程的类型和所要求的设备，执行该演示的挑战可能来自流程集成本身，也可能来自特定设备工具集的需求。已经包含3D演示设备的基础晶圆可以来自不同的地点，尺寸也不同。演示器可以完全由大块硅实现，因为它是中间层或设备的3D部分的情况，只有，必须开发，这将是异质集成的情况。为此，除了200毫米的试验生产线外，Leti还新建了一条300毫米的试验生产线，旨在与生产线兼容。这些设施今天允许实现300毫米的3D演示。本文讨论了这些原型的结果以及为集成所克服的挑战。
{"title":"3D Integration challenges today from technological toolbox to industrial prototypes","authors":"T. Mourier, C. Ribiére, G. Romero, M. Gottardi, N. Allouti, R. Eleouet, A. Roman, T. Magis, S. Minoret, C. Ratin, D. Scevola, E. Dupuy, B. Martin, L. Gabette, D. Marseilhan, T. Enot, M. Pellat, V. Loup, R. Segaud, H. Feldis, A. Charpentier, J. Bally, M. Assous, I. Charbonnier, C. Laviron, P. Coudrain, N. Sillon","doi":"10.1109/IITC.2013.6615598","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615598","url":null,"abstract":"3D integration, also referred as “More than Moore” approach is considered as the most attractive alternative to “More Moore” concept in order to increase circuit functionalities and performances while keeping reasonable cost of integrated devices. This technology has been widely presented and discussed during last years and is now available on several world wide integration platforms. Major part of the work done in recent years was focused on the three challenges to be overcome to allow manufacturing of 3D technology: design, process integration and tests. This was presented [1] as the availability of a complete toolbox including the design kit definition, the development and maturity increasing of the required process modules such as TSV, Wafer bonding and debonding, back side contact, both side interconnects and the definition of functional and reliability tests. This toolbox is dedicated to the construction of specific process flows and designs depending on the targeted applications. These applications, in the 3D integration world, are very flexible going from the passive and active interposers to memory on logic or logic on logic partitioning as well as stackable processors. Today, the different process modules are at a sufficient maturity state to allow the realization of demonstrators for all types of integration schemes. Depending on the type of integration flow and requested device, challenges to perform this demonstrator can come from the process integration itself but also from the need of specific equipment toolset. Base wafers already containing devices for 3D demonstrator can come from various site and be of different size. The demonstrator can be fully realized from bulk silicon as it is the case for an interposer or the 3D part of the device, only, will have to be developed which will be the case for heterogeneous integration. For this, a new 300 mm pilot line was built in Leti in addition to the 200 mm one and was designed to be compatible with manufacturing lines. These facilities are today allowing the realization of 300 mm 3D demonstrators. Results of these prototypes and the challenges overcome for integration are discussed in this paper.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82528498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615596
A. Rahman, J. Schulz, R. Grenier, K. Chanda, M. Lee, D. Ratakonda, H. Shi, Z. Li, K. Chandrasekar, J. Xie, D. Ibbotson
Die stacking technology with high-density interconnect is enabling new product architectures and capabilities. Silicon interposer based stacking with through silicon via (TSV) has gained traction for high-performance applications. Some of the challenges in manufacturing technology, supply-chain strategy, design tools and infrastructure are being addressed to enable broader technology adoption. This paper provides an overview of Field Programmable Gate Array (FPGA) application trends which are driving the need for advanced die-stacking technologies. We present design and manufacturing considerations for stacking technologies and highlight lessons learned from a recent technology demonstration vehicle.
{"title":"Interconnection requirements and multi-die integration for FPGAs","authors":"A. Rahman, J. Schulz, R. Grenier, K. Chanda, M. Lee, D. Ratakonda, H. Shi, Z. Li, K. Chandrasekar, J. Xie, D. Ibbotson","doi":"10.1109/IITC.2013.6615596","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615596","url":null,"abstract":"Die stacking technology with high-density interconnect is enabling new product architectures and capabilities. Silicon interposer based stacking with through silicon via (TSV) has gained traction for high-performance applications. Some of the challenges in manufacturing technology, supply-chain strategy, design tools and infrastructure are being addressed to enable broader technology adoption. This paper provides an overview of Field Programmable Gate Array (FPGA) application trends which are driving the need for advanced die-stacking technologies. We present design and manufacturing considerations for stacking technologies and highlight lessons learned from a recent technology demonstration vehicle.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"47 2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84808781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-02-13DOI: 10.1109/IITC.2013.6615582
Natsuki Fukuda, Kazunori Fukuju, Y. Nishioka, K. Suu
This paper deals with development of sputtering technology of Ta2O5/TaOx stacked film for ReRAM mass-production. Thickness of TaOx film deposited by sputtering process is possible to obtain with good uniformity. However, if a high deposition rate is required for mass production, it is very difficult to obtain good controllability and uniformity of TaOx film. These problems affect the switching characteristics of the ReRAM. In order to solve these problems, sputtering tool and process for ReRAM mass-production are developed. We report the result of TaOx film with good resistance uniformity and controllability and deposition stability without low deposition rate. Moreover, switching characteristics of Pt/Ta2O5/TaOx/Pt-ReRAM-cells are evaluated.
{"title":"Development of sputtering technology of Ta2O5/TaOx stacked film for ReRAM mass-production","authors":"Natsuki Fukuda, Kazunori Fukuju, Y. Nishioka, K. Suu","doi":"10.1109/IITC.2013.6615582","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615582","url":null,"abstract":"This paper deals with development of sputtering technology of Ta<sub>2</sub>O<sub>5</sub>/TaO<sub>x</sub> stacked film for ReRAM mass-production. Thickness of TaO<sub>x</sub> film deposited by sputtering process is possible to obtain with good uniformity. However, if a high deposition rate is required for mass production, it is very difficult to obtain good controllability and uniformity of TaO<sub>x</sub> film. These problems affect the switching characteristics of the ReRAM. In order to solve these problems, sputtering tool and process for ReRAM mass-production are developed. We report the result of TaO<sub>x</sub> film with good resistance uniformity and controllability and deposition stability without low deposition rate. Moreover, switching characteristics of Pt/Ta<sub>2</sub>O<sub>5</sub>/TaO<sub>x</sub>/Pt-ReRAM-cells are evaluated.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79234120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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