Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615575
J. M. Gu, Paragkumar Thadesar, A. Dembla, S. Hong, M. Bakir, G. May
A hybrid partial least squares-support vector machine (PLS-SVM) model of optical emission spectroscopy data is proposed and successfully demonstrated to predict the endpoint detection of through silicon vias (TSVs) etched using the Bosch process. Accurate results are shown for TSVs with diameters of 80 μm and 25 μm.
{"title":"Endpoint detection using optical emission spectroscopy in TSV fabrication","authors":"J. M. Gu, Paragkumar Thadesar, A. Dembla, S. Hong, M. Bakir, G. May","doi":"10.1109/IITC.2013.6615575","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615575","url":null,"abstract":"A hybrid partial least squares-support vector machine (PLS-SVM) model of optical emission spectroscopy data is proposed and successfully demonstrated to predict the endpoint detection of through silicon vias (TSVs) etched using the Bosch process. Accurate results are shown for TSVs with diameters of 80 μm and 25 μm.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88449659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615563
Y. Kikuchi, A. Wada, S. Samukawa
We developed a practical large-radius neutral beam enhanced CVD with a dimethoxy tetramethy ldisiloxane (DMOTMDS) to form low-k SiOCH film on 8-inch Si wafers. We fabricated extremely non-porous film with an ultra-low k-value of 2.3 and a sufficient modulus (>10 GPa). This particular film did not show any damage from the oxygen plasma and acid or alkali solutions used in the fabrication process. Furthermore, the dense film almost completely resisted Cu diffusion into the film during thermal annealing.
{"title":"Extremely non-porous ultra-low-k SiOCH (k=2.3) with sufficient modulus (>10 GPa), high Cu diffusion barrier and high tolerance for integration process formed by large-radius neutral-beam enhanced CVD","authors":"Y. Kikuchi, A. Wada, S. Samukawa","doi":"10.1109/IITC.2013.6615563","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615563","url":null,"abstract":"We developed a practical large-radius neutral beam enhanced CVD with a dimethoxy tetramethy ldisiloxane (DMOTMDS) to form low-k SiOCH film on 8-inch Si wafers. We fabricated extremely non-porous film with an ultra-low k-value of 2.3 and a sufficient modulus (>10 GPa). This particular film did not show any damage from the oxygen plasma and acid or alkali solutions used in the fabrication process. Furthermore, the dense film almost completely resisted Cu diffusion into the film during thermal annealing.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73539274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615572
R. Tzeng, Yan-Pin Huang, Y. Chien, C. Chuang, W. Hwang, J. Chiou, M. Shy, Teu-Hua Lin, Kou-Hua Chen, C. Chiu, H. Tong, Kuan-Neng Chen
A low temperature bonding technology of Sn/In composite solder bonded to Cu interconnect is proposed and investigated. The intermetallic compounds formed in the bonded interconnects can survive well in the following process. The Sn/In-Cu interconnects bonded at low temperature all exhibit excellent electrical performance and high resistance to multiple current stressing, showing a great potential in 3D applications.
提出并研究了一种Sn/In复合焊料与Cu互连的低温键合工艺。在键合互连中形成的金属间化合物可以在以下过程中很好地存活。在低温下结合的Sn/ in - cu互连都具有优异的电性能和高的耐多重电流应力，在3D应用中显示出巨大的潜力。
{"title":"Low temperature bonding of Sn/In-Cu interconnects for three-dimensional integration applications","authors":"R. Tzeng, Yan-Pin Huang, Y. Chien, C. Chuang, W. Hwang, J. Chiou, M. Shy, Teu-Hua Lin, Kou-Hua Chen, C. Chiu, H. Tong, Kuan-Neng Chen","doi":"10.1109/IITC.2013.6615572","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615572","url":null,"abstract":"A low temperature bonding technology of Sn/In composite solder bonded to Cu interconnect is proposed and investigated. The intermetallic compounds formed in the bonded interconnects can survive well in the following process. The Sn/In-Cu interconnects bonded at low temperature all exhibit excellent electrical performance and high resistance to multiple current stressing, showing a great potential in 3D applications.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89068553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615567
A. Kobayashi, D. Ishikawa, K. Matsushita, N. Kobayashi
A pore sealing process by Plasma-enhanced ALD (PEALD) with an amino-silane precursor has been developed, which enabled simultaneous restoration and pore-sealing film formation on damaged low-k film with k = 2.0. The precursor adsorbed preferentially at OR termination on the low-k surface to form self-assembled (SA) SiOC layer, which simultaneously recovered low-k damage. It is suggested that the SA-SiOC layer narrowed the pore opening at the low-k surface, and was followed by hermetic SiCN layer formation by PEALD. Sealing of pores against wet chemical was confirmed by forming 1.3 nm SiCN. Leakage current after pore-sealing formation was reduced by more than one magnitude compared to the pristine low-k. The current process will pave the way for enabling extremely thin diffusion barrier <;2nm at IX nm node Cu interconnect.
{"title":"Pore-sealing process initiated by self-assembled layer for extreme low-k SiOCH (k=2.0)","authors":"A. Kobayashi, D. Ishikawa, K. Matsushita, N. Kobayashi","doi":"10.1109/IITC.2013.6615567","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615567","url":null,"abstract":"A pore sealing process by Plasma-enhanced ALD (PEALD) with an amino-silane precursor has been developed, which enabled simultaneous restoration and pore-sealing film formation on damaged low-k film with k = 2.0. The precursor adsorbed preferentially at OR termination on the low-k surface to form self-assembled (SA) SiOC layer, which simultaneously recovered low-k damage. It is suggested that the SA-SiOC layer narrowed the pore opening at the low-k surface, and was followed by hermetic SiCN layer formation by PEALD. Sealing of pores against wet chemical was confirmed by forming 1.3 nm SiCN. Leakage current after pore-sealing formation was reduced by more than one magnitude compared to the pristine low-k. The current process will pave the way for enabling extremely thin diffusion barrier <;2nm at IX nm node Cu interconnect.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82427422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615557
D. Vogel, E. Auerswald, B. Michel, S. Rzepka
The paper presents a new stress measurement method on base of stress relief caused by local material removal with ion milling in FIB equipment. Stress relief deformations extracted from SEM micrographs by means of digital image correlation allow the determination of stresses, as well as to estimate Young's modulus on the position of ion milling. The paper gives an introduction into the method. The feasibility to extract local stresses in multilayer stacks, both in lateral direction and in depth, is discussed in more detail.
{"title":"Experimental analysis of mechanical stresses and material properties in multi-layer interconnect systems by fibDAC","authors":"D. Vogel, E. Auerswald, B. Michel, S. Rzepka","doi":"10.1109/IITC.2013.6615557","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615557","url":null,"abstract":"The paper presents a new stress measurement method on base of stress relief caused by local material removal with ion milling in FIB equipment. Stress relief deformations extracted from SEM micrographs by means of digital image correlation allow the determination of stresses, as well as to estimate Young's modulus on the position of ion milling. The paper gives an introduction into the method. The feasibility to extract local stresses in multilayer stacks, both in lateral direction and in depth, is discussed in more detail.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83580083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615578
A. Singulani, H. Ceric, E. Langer
Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. We identified that the presence of scallops on the TSV wall modifies the stress distribution. The achieved results support experiments and give a better insight into the influence of scallops in an open TSV.
{"title":"Stress reduction induced by Bosch scallops on an open TSV technology","authors":"A. Singulani, H. Ceric, E. Langer","doi":"10.1109/IITC.2013.6615578","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615578","url":null,"abstract":"Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. We identified that the presence of scallops on the TSV wall modifies the stress distribution. The achieved results support experiments and give a better insight into the influence of scallops in an open TSV.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77102664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615600
D. Kondo, H. Nakano, Bo Zhou, I. Kubota, Kenjiro Hayashi, K. Yagi, M. Takahashi, Motonobu Sato, Shintaro Sato, N. Yokoyama
We have fabricated multi-layer graphene (MLG) wiring and demonstrated a resistivity of the same order as Cu and reliability better than Cu. The MLG was synthesized epitaxially by chemical vapor deposition (CVD) on an epitaxial Co film, resulting in quality and electrical properties as good as those of a graphite crystal. The MLG was further intercalated with FeCl3 to achieve a resistivity as low as 9.1 μΩ cm. Our results show that intercalated MLG is really promising for future LSI interconnects.
{"title":"Intercalated multi-layer graphene grown by CVD for LSI interconnects","authors":"D. Kondo, H. Nakano, Bo Zhou, I. Kubota, Kenjiro Hayashi, K. Yagi, M. Takahashi, Motonobu Sato, Shintaro Sato, N. Yokoyama","doi":"10.1109/IITC.2013.6615600","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615600","url":null,"abstract":"We have fabricated multi-layer graphene (MLG) wiring and demonstrated a resistivity of the same order as Cu and reliability better than Cu. The MLG was synthesized epitaxially by chemical vapor deposition (CVD) on an epitaxial Co film, resulting in quality and electrical properties as good as those of a graphite crystal. The MLG was further intercalated with FeCl3 to achieve a resistivity as low as 9.1 μΩ cm. Our results show that intercalated MLG is really promising for future LSI interconnects.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"08 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74952633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615590
N. Inoue, F. Ito, H. Shobha, S. Gates, E. T. Ryan, K. Virwani, N. Klvmko, A. Madan, L. Tai, E. Adams, S. Cohen, E. Liniger, C. Hu, Y. Mignot, A. Grill, T. Spooner
UV cure on robust low-k with sub-nm pore and high carbon content (R-ELK=Robust ELK) was studied to enhance the modulus of the film. UV cure helps to create Si-CH2-Si bridging bond, which plays a role to enhance the modulus. UV cure does not affect the advantage of low PID (plasma-induced damage) and it was confirmed by Cint (interconnect capacitance) measurement for 80 nm pitch interconnect. Besides, UV cured R-ELK demonstrated high TDDB and EM reliability, with lifetime similar to the mature ULK baseline. High TDDB reliability with further dimensional scaling was also confirmed for the test structure with 20 nm spacing.
{"title":"UV cure impact on robust low-k with sub-nm pores and high carbon content for high performance Cu/low-k BEOL modules","authors":"N. Inoue, F. Ito, H. Shobha, S. Gates, E. T. Ryan, K. Virwani, N. Klvmko, A. Madan, L. Tai, E. Adams, S. Cohen, E. Liniger, C. Hu, Y. Mignot, A. Grill, T. Spooner","doi":"10.1109/IITC.2013.6615590","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615590","url":null,"abstract":"UV cure on robust low-k with sub-nm pore and high carbon content (R-ELK=Robust ELK) was studied to enhance the modulus of the film. UV cure helps to create Si-CH2-Si bridging bond, which plays a role to enhance the modulus. UV cure does not affect the advantage of low PID (plasma-induced damage) and it was confirmed by Cint (interconnect capacitance) measurement for 80 nm pitch interconnect. Besides, UV cured R-ELK demonstrated high TDDB and EM reliability, with lifetime similar to the mature ULK baseline. High TDDB reliability with further dimensional scaling was also confirmed for the test structure with 20 nm spacing.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74606458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615592
T. Nogami, M. He, X. Zhang, K. Tanwar, R. Patlolla, J. Kelly, D. Rath, M. Krishnan, X. Lin, O. Straten, H. Shobha, J. Li, A. Madan, P. Flaitz, C. Parks, C. Hu, C. Penny, A. Simon, T. Bolom, J. Maniscalco, D. Canaperi, T. Spooner, D. Edelstein
In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.
{"title":"CVD-Co/Cu(Mn) integration and reliability for 10 nm node","authors":"T. Nogami, M. He, X. Zhang, K. Tanwar, R. Patlolla, J. Kelly, D. Rath, M. Krishnan, X. Lin, O. Straten, H. Shobha, J. Li, A. Madan, P. Flaitz, C. Parks, C. Hu, C. Penny, A. Simon, T. Bolom, J. Maniscalco, D. Canaperi, T. Spooner, D. Edelstein","doi":"10.1109/IITC.2013.6615592","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615592","url":null,"abstract":"In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74448621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615601
M. H. van der Veen, Y. Barbarin, B. Vereecke, Masahito Sugiura, Y. Kashiwagi, D. Cott, C. Huyghebaert, Z. Tokei
We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·103 μΩ·cm down to 5.1·103 μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.
{"title":"Electrical improvement of CNT contacts with Cu damascene top metallization","authors":"M. H. van der Veen, Y. Barbarin, B. Vereecke, Masahito Sugiura, Y. Kashiwagi, D. Cott, C. Huyghebaert, Z. Tokei","doi":"10.1109/IITC.2013.6615601","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615601","url":null,"abstract":"We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·10<sup>3</sup> μΩ·cm down to 5.1·10<sup>3</sup> μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91193550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：