Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615556
M. Lin, A. Oates
The effects of AC and pulsed-DC (PDC) waveforms on electromigration failure distributions in Cu / low-k interconnects are examined. No failures are observed with a 1MHz pure AC stress, consistent with average current density controlled kinetics and complete recovery of damage during current reversal. Failure distributions with PDC stress are consistent with a degradation process that is determined by average current density and void growth kinetics.
{"title":"AC and pulsed-DC stress electromigration failure mechanisms in Cu interconnects","authors":"M. Lin, A. Oates","doi":"10.1109/IITC.2013.6615556","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615556","url":null,"abstract":"The effects of AC and pulsed-DC (PDC) waveforms on electromigration failure distributions in Cu / low-k interconnects are examined. No failures are observed with a 1MHz pure AC stress, consistent with average current density controlled kinetics and complete recovery of damage during current reversal. Failure distributions with PDC stress are consistent with a degradation process that is determined by average current density and void growth kinetics.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81980448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615569
T. Jeong, S. Windu, Dong-Cheon Baek, Jinseok Kim, Kyuho Tak, Miji Lee, Hyuniun Choi, S. Pae, Jongwoo Park
Early failure of the short-lead metal line EM (Electromigration) is investigated. Applying Wheatstone bridge (WSB) test structure and 3-parameter lognormal distribution enables to reduce sample size and time-to-fail (TTF) variation governed by early fails causing a poor standard deviation, EM lifetime is accurately predicted and improved by ~280×. In particular, EM TTF at lower percentiles can be well represented by 3-parameter lognormal. With respect to physical aspects of void, EM behaviors of the short-lead and long-lead metal line are addressed based on experimental results compared with Monte-Carlo simulations to support the Blech's back-stress effects.
{"title":"Early failure of short-lead metal line and its EM characterization with Wheatstone bridge test structure in advanced Cu/ULK BEOL process","authors":"T. Jeong, S. Windu, Dong-Cheon Baek, Jinseok Kim, Kyuho Tak, Miji Lee, Hyuniun Choi, S. Pae, Jongwoo Park","doi":"10.1109/IITC.2013.6615569","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615569","url":null,"abstract":"Early failure of the short-lead metal line EM (Electromigration) is investigated. Applying Wheatstone bridge (WSB) test structure and 3-parameter lognormal distribution enables to reduce sample size and time-to-fail (TTF) variation governed by early fails causing a poor standard deviation, EM lifetime is accurately predicted and improved by ~280×. In particular, EM TTF at lower percentiles can be well represented by 3-parameter lognormal. With respect to physical aspects of void, EM behaviors of the short-lead and long-lead metal line are addressed based on experimental results compared with Monte-Carlo simulations to support the Blech's back-stress effects.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77740942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615599
M. Wada, T. Ishikura, D. Nishide, B. Ito, Y. Yamazaki, Tatsuro Saito, A. Isobayashi, M. Kagaya, Takashi Matsumoto, M. Kitamura, A. Sakata, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai
The present work investigated the possibility of the formation of graphene interconnects and studied the behavior of graphene growth in wiring structure. Graphene nucleated on the facet of catalytic metal, and multi layer graphene grew along the terrace surface of catalytic metal. Selective graphene growth served the stacked interconnects structure of graphene / Ni catalytic metal.
{"title":"Graphene interconenets selectively grown on catalytic metal damascene structure and its growth mechanism on Ni catalyst","authors":"M. Wada, T. Ishikura, D. Nishide, B. Ito, Y. Yamazaki, Tatsuro Saito, A. Isobayashi, M. Kagaya, Takashi Matsumoto, M. Kitamura, A. Sakata, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai","doi":"10.1109/IITC.2013.6615599","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615599","url":null,"abstract":"The present work investigated the possibility of the formation of graphene interconnects and studied the behavior of graphene growth in wiring structure. Graphene nucleated on the facet of catalytic metal, and multi layer graphene grew along the terrace surface of catalytic metal. Selective graphene growth served the stacked interconnects structure of graphene / Ni catalytic metal.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"46 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79912686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615595
Paragkumar Thadesar, A. Dembla, Devin K. Brown, M. Bakir
To circumvent the performance and energy bottlenecks due to interconnects, novel interconnect solutions are needed both at the package and die levels. This paper reports (1) novel photodefined polymer-embedded vias within silicon interposers for improved through-silicon via insertion loss, and (2) ultrahigh density low-capacitance nanoscale TSVs with 100 nm diameter and 20:1 aspect ratio for fine-grain 3D IC implementation.
{"title":"Novel through-silicon via technologies for 3D system integration","authors":"Paragkumar Thadesar, A. Dembla, Devin K. Brown, M. Bakir","doi":"10.1109/IITC.2013.6615595","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615595","url":null,"abstract":"To circumvent the performance and energy bottlenecks due to interconnects, novel interconnect solutions are needed both at the package and die levels. This paper reports (1) novel photodefined polymer-embedded vias within silicon interposers for improved through-silicon via insertion loss, and (2) ultrahigh density low-capacitance nanoscale TSVs with 100 nm diameter and 20:1 aspect ratio for fine-grain 3D IC implementation.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75374455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615555
T. Kirimura, K. Croes, Y. Siew, K. Vanstreels, P. Czarnecki, Z. Ei-Mekki, M. H. van der Veen, D. Dictus, A. Yoon, A. Kolics, J. Bommcls, Z. Tokei
We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.
{"title":"Void nucleation and growth during electromigration in 30 nm wide Cu lines: Impact of different interfaces on failure mode","authors":"T. Kirimura, K. Croes, Y. Siew, K. Vanstreels, P. Czarnecki, Z. Ei-Mekki, M. H. van der Veen, D. Dictus, A. Yoon, A. Kolics, J. Bommcls, Z. Tokei","doi":"10.1109/IITC.2013.6615555","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615555","url":null,"abstract":"We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"BC-28 4","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72571292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615586
Y. Okawa, S. Mandal, M. Makarova, M. Aono
We found before that a stimulation with the probe tip of a scanning tunneling microscope (STM) could initiate a chain polymerization of diacetylene compound. Based on these previous studies, here we report a novel method for single molecular wiring, which we call “chemical soldering.” This method enables us to connect single conjugated polymer chains to single functional molecules, which would be an important step in advancing the development of single-molecule electronic circuitry.
{"title":"Interconnects with single conjugated polymers","authors":"Y. Okawa, S. Mandal, M. Makarova, M. Aono","doi":"10.1109/IITC.2013.6615586","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615586","url":null,"abstract":"We found before that a stimulation with the probe tip of a scanning tunneling microscope (STM) could initiate a chain polymerization of diacetylene compound. Based on these previous studies, here we report a novel method for single molecular wiring, which we call “chemical soldering.” This method enables us to connect single conjugated polymer chains to single functional molecules, which would be an important step in advancing the development of single-molecule electronic circuitry.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"38 11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82822425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615566
Kenji Matsumoto, Kaoru Maekawa, H. Nagai, Junichi Koike
We investigated the possibility of applying an ALD method to form a Cu diffusion barrier layer of MnOx in an attempt to develop a deposition process which would not be influenced by absorbed water in a substrate. The MnOx formed by ALD using (EtCp)2Mn and H2O had the following features. (1) Capability of thickness control of the MnOx layer by changing the ALD cycle number. (2) Capability of the ALD-MnOx formation on low-k dielectrics by surface modification. (3) Good adhesion of the Cu/ALD-MnOx/SiOCH structure showing a fracture toughness of 0.3 MPa·m1/2. (4) Good diffusion barrier property for the thickness of over 1 nm. (5) Minimizing via resistance increase accompanied by the formation of MnOx on Cu.
{"title":"Deposition behavior and substrate dependency of ALD MnOx diffusion barrier layer","authors":"Kenji Matsumoto, Kaoru Maekawa, H. Nagai, Junichi Koike","doi":"10.1109/IITC.2013.6615566","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615566","url":null,"abstract":"We investigated the possibility of applying an ALD method to form a Cu diffusion barrier layer of MnOx in an attempt to develop a deposition process which would not be influenced by absorbed water in a substrate. The MnOx formed by ALD using (EtCp)2Mn and H2O had the following features. (1) Capability of thickness control of the MnOx layer by changing the ALD cycle number. (2) Capability of the ALD-MnOx formation on low-k dielectrics by surface modification. (3) Good adhesion of the Cu/ALD-MnOx/SiOCH structure showing a fracture toughness of 0.3 MPa·m1/2. (4) Good diffusion barrier property for the thickness of over 1 nm. (5) Minimizing via resistance increase accompanied by the formation of MnOx on Cu.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"14 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82001004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615602
S. Vollebregt, H. Schellevis, K. Beenakker, R. Ishihara
Vertically aligned carbon nanotubes (CNT) were fabricated using a novel CoAlcatalyst at substrate temperatures as low as 350°C and analysed using Raman spectroscopy. Electrical measurement structures were fabricated and characterized using CNT bundles grown at 400°C. The resulting I-V characteristics display a slight non-linearity, likely due to a nonoptimal top contact. The first measurement results indicate CoAl can be an attractive candidate for back-end integration of CNT.
{"title":"Carbon nanotube vias fabricated at back-end of line compatible temperature using a novel CoAl catalyst","authors":"S. Vollebregt, H. Schellevis, K. Beenakker, R. Ishihara","doi":"10.1109/IITC.2013.6615602","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615602","url":null,"abstract":"Vertically aligned carbon nanotubes (CNT) were fabricated using a novel CoAlcatalyst at substrate temperatures as low as 350°C and analysed using Raman spectroscopy. Electrical measurement structures were fabricated and characterized using CNT bundles grown at 400°C. The resulting I-V characteristics display a slight non-linearity, likely due to a nonoptimal top contact. The first measurement results indicate CoAl can be an attractive candidate for back-end integration of CNT.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"77 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83307611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615594
T. Tanaka, H. Kino, K. Kiyoyama, H. Ohno, M. Koyanagi
A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.
{"title":"Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology","authors":"T. Tanaka, H. Kino, K. Kiyoyama, H. Ohno, M. Koyanagi","doi":"10.1109/IITC.2013.6615594","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615594","url":null,"abstract":"A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73534902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615570
B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan-Sabet, F. Bana
The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.
{"title":"Redundancy method to assess electromigration lifetime in power Grid design","authors":"B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan-Sabet, F. Bana","doi":"10.1109/IITC.2013.6615570","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615570","url":null,"abstract":"The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"239 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79707518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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