Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615591
N. Possémé, L. Vallier, C. Kao, C. Licitra, C. Petit-Etienne, C. Mannequin, P. Gonon, S. Belostotskiy, J. Pender, S. Banola, O. Joubert, S. Nemani
Today porous SiOCH combined with metallic hard masking strategy is an integration of choice for advanced BEOL interconnect technology node. However in this context the main integration issue is the dielectric film sensitivity to fluorocarbon (FC) etch chemistry. In this study, new FC free etching chemistry has been proposed as breakthrough solution. Based on pattern and blanket film analyses, the benefits of this new chemistry is presented and discussed with respect to conventional FC etching. Its compatibility with metallic hard mask integration and wet cleaning is also evaluated.
{"title":"New fluorocarbon free chemistry proposed as solution to limit porous SiOCH film modification during etching","authors":"N. Possémé, L. Vallier, C. Kao, C. Licitra, C. Petit-Etienne, C. Mannequin, P. Gonon, S. Belostotskiy, J. Pender, S. Banola, O. Joubert, S. Nemani","doi":"10.1109/IITC.2013.6615591","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615591","url":null,"abstract":"Today porous SiOCH combined with metallic hard masking strategy is an integration of choice for advanced BEOL interconnect technology node. However in this context the main integration issue is the dielectric film sensitivity to fluorocarbon (FC) etch chemistry. In this study, new FC free etching chemistry has been proposed as breakthrough solution. Based on pattern and blanket film analyses, the benefits of this new chemistry is presented and discussed with respect to conventional FC etching. Its compatibility with metallic hard mask integration and wet cleaning is also evaluated.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"136 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85769735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615564
N. Shishido, S. Kamiya, C. Chen, H. Sato, K. Koiwa, M. Omiya, M. Nishida, T. Suzuki, T. Nakamura, T. Nokuo
Macroscopic and microscopic adhesion strength of damascene interconnects was investigated by evaluating local strength through delaminating different scales of adhesion area under SEM observation. Macroscopic strength obtained by the areas larger than the copper grain was almost constant after considering the macroscopic plastic deformation. However, microscopic strength obtained by the areas smaller than the copper grain spread around the macroscopic strength and was highly sensitive to the copper grain structure, especially the grain boundary.
{"title":"Macroscopic and microscopic interface adhesion strength of copper damascene interconnects","authors":"N. Shishido, S. Kamiya, C. Chen, H. Sato, K. Koiwa, M. Omiya, M. Nishida, T. Suzuki, T. Nakamura, T. Nokuo","doi":"10.1109/IITC.2013.6615564","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615564","url":null,"abstract":"Macroscopic and microscopic adhesion strength of damascene interconnects was investigated by evaluating local strength through delaminating different scales of adhesion area under SEM observation. Macroscopic strength obtained by the areas larger than the copper grain was almost constant after considering the macroscopic plastic deformation. However, microscopic strength obtained by the areas smaller than the copper grain spread around the macroscopic strength and was highly sensitive to the copper grain structure, especially the grain boundary.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84220569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615581
Teppei Kawanabe, A. Kawabata, T. Murakami, M. Nihei, Y. Awano
We report numerical simulations of heat dissipation properties of nano-carbon through silicon via (TSV), thermal interface material (TIM), and chip package towards a high heat dissipation LSI 3-D packaging. By using vertically aligned multi-walled CNTs (MWNTs) as both TSV and TIM materials and graphite as chip package, a boundary temperature just under a heat source decreased 40.8K in total, comparing to that using conventional materials. This result suggests superior heat dissipation properties of nano-carbon 3-D packaging.
{"title":"Numerical simulations of high heat dissipation technology in LSI 3-D packaging using carbon nanotube through silicon via (CNT-TSV) and thermal interface material (CNT-TIM)","authors":"Teppei Kawanabe, A. Kawabata, T. Murakami, M. Nihei, Y. Awano","doi":"10.1109/IITC.2013.6615581","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615581","url":null,"abstract":"We report numerical simulations of heat dissipation properties of nano-carbon through silicon via (TSV), thermal interface material (TIM), and chip package towards a high heat dissipation LSI 3-D packaging. By using vertically aligned multi-walled CNTs (MWNTs) as both TSV and TIM materials and graphite as chip package, a boundary temperature just under a heat source decreased 40.8K in total, comparing to that using conventional materials. This result suggests superior heat dissipation properties of nano-carbon 3-D packaging.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86840480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615553
A. Oates
The short-length effect, whereby electromigration is eliminated due a mechanical stress-gradient induced backflow has a profound impact on the characteristics of electromigration failure. Here we review our recent studies of electromigration failure at short lengths in Cu/low-k interconnects. We show that voiding failures can occur at current densities below the critical value. We develop a model that accurately predicts failure distributions as a function of stress variables, conductor geometry, and presence of passive reservoirs. We also discuss the scaling of electromigration at short - lengths, and show that failure times decrease even more rapidly than long-lengths with technology scaling.
{"title":"The electromigration short — Length effect and its impact on circuit reliability","authors":"A. Oates","doi":"10.1109/IITC.2013.6615553","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615553","url":null,"abstract":"The short-length effect, whereby electromigration is eliminated due a mechanical stress-gradient induced backflow has a profound impact on the characteristics of electromigration failure. Here we review our recent studies of electromigration failure at short lengths in Cu/low-k interconnects. We show that voiding failures can occur at current densities below the critical value. We develop a model that accurately predicts failure distributions as a function of stress variables, conductor geometry, and presence of passive reservoirs. We also discuss the scaling of electromigration at short - lengths, and show that failure times decrease even more rapidly than long-lengths with technology scaling.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80656997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615584
Tengfei Jiang, Suk-kyu Ryu, J. Im, H.-Y Son, Nam-Seog Kim, Rui Huang, P. Ho
Thermal stresses and microstructures of two TSV structures with different fabrication conditions have been investigated using the precision wafer curvature and synchrotron x-ray microdiffraction methods, providing the first direct observation of local plasticity in the TSVs. Results from this study show that the electroplating chemistry directly affects the Cu microstructure, which in turn controls stress relaxation and build-up of the residual stress during thermal cycling. The implications on via extrusion and device keep-out zone (KOZ) are discussed.
{"title":"Impact of material and microstructure on thermal stresses and reliability of through-silicon via (TSV) structures","authors":"Tengfei Jiang, Suk-kyu Ryu, J. Im, H.-Y Son, Nam-Seog Kim, Rui Huang, P. Ho","doi":"10.1109/IITC.2013.6615584","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615584","url":null,"abstract":"Thermal stresses and microstructures of two TSV structures with different fabrication conditions have been investigated using the precision wafer curvature and synchrotron x-ray microdiffraction methods, providing the first direct observation of local plasticity in the TSVs. Results from this study show that the electroplating chemistry directly affects the Cu microstructure, which in turn controls stress relaxation and build-up of the residual stress during thermal cycling. The implications on via extrusion and device keep-out zone (KOZ) are discussed.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89762679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615576
K. Kohama, T. Iijima, M. Hayashida, S. Ogawa
We deposited tungsten-based pillars on ~300 nm-thick amorphous carbon and single-crystalline silicon substrates by a helium ion microscope (HIM) using tungsten hexacarbonyl (W(CO)6) as a gaseous precursor. We then investigated beam-induced damage to the substrates correlated with both pillar growth rate and material type of substrates. Faster pillar growth reduced the substrate damage because the pillars shielded the substrates from the incident beam, resulting in a low-damage process. On the other hand, the Si substrate was significantly damaged by the incident beam compared with the carbon substrates. This is because stopping cross-section of 30-ke V helium ion in silicon is ~1.5 times higher than that in carbon. The incident helium ions were considered to induce the substrate damage in the process of losing energy in the substrates.
{"title":"Beam-substrate interaction during tungsten deposition by helium ion microscope","authors":"K. Kohama, T. Iijima, M. Hayashida, S. Ogawa","doi":"10.1109/IITC.2013.6615576","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615576","url":null,"abstract":"We deposited tungsten-based pillars on ~300 nm-thick amorphous carbon and single-crystalline silicon substrates by a helium ion microscope (HIM) using tungsten hexacarbonyl (W(CO)6) as a gaseous precursor. We then investigated beam-induced damage to the substrates correlated with both pillar growth rate and material type of substrates. Faster pillar growth reduced the substrate damage because the pillars shielded the substrates from the incident beam, resulting in a low-damage process. On the other hand, the Si substrate was significantly damaged by the incident beam compared with the carbon substrates. This is because stopping cross-section of 30-ke V helium ion in silicon is ~1.5 times higher than that in carbon. The incident helium ions were considered to induce the substrate damage in the process of losing energy in the substrates.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"41 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86460094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615562
M. Baklanov, Liping Zhang, R. Dussart, J. de Marneffe
Cryogenic etching was applied to porous organosilicate (OSG) films. Plasma-induced damage was reduced due to the protective effect of etch by-products condensed in pores of low-k materials. Almost no carbon depletion was observed when the wafer temperature is below a certain critical level. Most of experiments were carried out with SF6 plasma. The addition of SiF4/O2 into the gas discharge allows a further reduction of plasma-induced damage by formation of a SiOxFy passivation layer.
{"title":"Damage free cryogenic etching of ultra low-k materials","authors":"M. Baklanov, Liping Zhang, R. Dussart, J. de Marneffe","doi":"10.1109/IITC.2013.6615562","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615562","url":null,"abstract":"Cryogenic etching was applied to porous organosilicate (OSG) films. Plasma-induced damage was reduced due to the protective effect of etch by-products condensed in pores of low-k materials. Almost no carbon depletion was observed when the wafer temperature is below a certain critical level. Most of experiments were carried out with SF<sub>6</sub> plasma. The addition of SiF<sub>4</sub>/O<sub>2</sub> into the gas discharge allows a further reduction of plasma-induced damage by formation of a SiO<sub>x</sub>F<sub>y</sub> passivation layer.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79066043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615573
Jiro Yokota, Clement Lansalot, Changhee Ko
Plasma enhanced atomic layer deposition (PEALD) using the novel η3-2-methylallyl N,N'-diisopropylacetamidinate nickel(II) precursor has been investigated. NH3 has been selected as the most appropriate co-reactant for the depositions. (PE)ALD saturations were observed at 200°C and 300 °C, with a deposition rate of 1.0 Å/cycle and 1.2Å/cycle respectively. No incubation time was observed with linear film growth at 300°C. Deposition on SiO2 patterned wafer was performed and SEM image analysis showed good step coverage of close to 100%. H2 anneal post treatment allowed to obtain very pure nickel film and resistivities value down to 9μΩ·cm, close to the resistivity value of bulk nickel (5-10μΩ·cm) [1].
{"title":"Thin nickel films growth using plasma enhanced atomic layer deposition from η3-2-methylallyl N, N'-diisopropylacetamidinate nickel(II)","authors":"Jiro Yokota, Clement Lansalot, Changhee Ko","doi":"10.1109/IITC.2013.6615573","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615573","url":null,"abstract":"Plasma enhanced atomic layer deposition (PEALD) using the novel η<sup>3</sup>-2-methylallyl N,N'-diisopropylacetamidinate nickel(II) precursor has been investigated. NH<sub>3</sub> has been selected as the most appropriate co-reactant for the depositions. (PE)ALD saturations were observed at 200°C and 300 °C, with a deposition rate of 1.0 Å/cycle and 1.2Å/cycle respectively. No incubation time was observed with linear film growth at 300°C. Deposition on SiO<sub>2</sub> patterned wafer was performed and SEM image analysis showed good step coverage of close to 100%. H<sub>2</sub> anneal post treatment allowed to obtain very pure nickel film and resistivities value down to 9μΩ·cm, close to the resistivity value of bulk nickel (5-10μΩ·cm) [1].","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79367257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615574
T. Konkova, S. Mironov, Y. Ke, J. Onuki
High-resolution electron backscatter diffraction (EBSD) technique was applied for systematic and detailed study of grain structure and texture changes in various microstructural regions of nano-scale damascene copper lines after annealing in a wide temperature range of 200-500°C. To ensure reliability of the obtained results, large EBSD maps including several thousand grains were obtained in each case. Above 200°C, the grain structure was established to be surprisingly stable in both the overburden layer as well as within the lines. The grain growth in the lines was supposed to be suppressed by pinning effect of second-phase particles entrapped during electrodeposition process.
{"title":"Annealing effect on the structure characteristics of nano-scale damascene copper lines","authors":"T. Konkova, S. Mironov, Y. Ke, J. Onuki","doi":"10.1109/IITC.2013.6615574","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615574","url":null,"abstract":"High-resolution electron backscatter diffraction (EBSD) technique was applied for systematic and detailed study of grain structure and texture changes in various microstructural regions of nano-scale damascene copper lines after annealing in a wide temperature range of 200-500°C. To ensure reliability of the obtained results, large EBSD maps including several thousand grains were obtained in each case. Above 200°C, the grain structure was established to be surprisingly stable in both the overburden layer as well as within the lines. The grain growth in the lines was supposed to be suppressed by pinning effect of second-phase particles entrapped during electrodeposition process.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80989144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-13DOI: 10.1109/IITC.2013.6615571
Vachan Kumar, Li Zheng, M. Bakir, A. Naeemi
This paper presents the first optimization methodology for silicon interposer interconnect technology. The dimensions of these fine-pitch interconnects are roughly a few microns, because of which they can neither be treated as on-chip RC interconnects, nor as conventional off-chip interconnects. 3D extraction tools can provide an accurate estimate of the circuit parameters, but they prove to be very slow and tedious for design space exploration and optimization. Thus, the novel analytical models developed here for the frequency dependent resistance of fine-pitch interconnects are essential to efficiently optimize these interconnects. The error in the model is shown to be less than 15% for interconnect dimensions and frequency range of interest. The analytical models developed are then used to optimize the data-rate and cross-sectional dimensions to maximize the bandwidth-density and minimize the energy-per-bit, simultaneously.
{"title":"Compact modeling and optimization of fine-pitch interconnects for silicon interposers","authors":"Vachan Kumar, Li Zheng, M. Bakir, A. Naeemi","doi":"10.1109/IITC.2013.6615571","DOIUrl":"https://doi.org/10.1109/IITC.2013.6615571","url":null,"abstract":"This paper presents the first optimization methodology for silicon interposer interconnect technology. The dimensions of these fine-pitch interconnects are roughly a few microns, because of which they can neither be treated as on-chip RC interconnects, nor as conventional off-chip interconnects. 3D extraction tools can provide an accurate estimate of the circuit parameters, but they prove to be very slow and tedious for design space exploration and optimization. Thus, the novel analytical models developed here for the frequency dependent resistance of fine-pitch interconnects are essential to efficiently optimize these interconnects. The error in the model is shown to be less than 15% for interconnect dimensions and frequency range of interest. The analytical models developed are then used to optimize the data-rate and cross-sectional dimensions to maximize the bandwidth-density and minimize the energy-per-bit, simultaneously.","PeriodicalId":6377,"journal":{"name":"2013 IEEE International Interconnect Technology Conference - IITC","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81713464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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