Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437620
Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal
We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of maximum entropy), which improves testability. We propose using partial-scan for testing, to maximize fault coverage (FC), reduce test volume (TV), reduce test application time (TAT), and reduce test power (TP) but we allow for full-scan during silicon debug. Full-scan is commonly used for testing, to reduce sequential automatic test-pattern generation (ATPG) to the complexity of combinational ATPG, but comes with serious TV, TAT, and TP overheads. Partial-scan significantly reduces circuit delay, when compared to full-scan, because critical flip-flops in the circuit data path do not have the extra hardware for full-scan, and therefore are roughly 5% faster, and use 10% less area. This is particularly critical for microprocessors. The HITEC ATPG program generated results for this new partial-scan algorithm.
{"title":"SPARTAN: a spectral and information theoretic approach to partial-scan","authors":"Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal","doi":"10.1109/TEST.2007.4437620","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437620","url":null,"abstract":"We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of maximum entropy), which improves testability. We propose using partial-scan for testing, to maximize fault coverage (FC), reduce test volume (TV), reduce test application time (TAT), and reduce test power (TP) but we allow for full-scan during silicon debug. Full-scan is commonly used for testing, to reduce sequential automatic test-pattern generation (ATPG) to the complexity of combinational ATPG, but comes with serious TV, TAT, and TP overheads. Partial-scan significantly reduces circuit delay, when compared to full-scan, because critical flip-flops in the circuit data path do not have the extra hardware for full-scan, and therefore are roughly 5% faster, and use 10% less area. This is particularly critical for microprocessors. The HITEC ATPG program generated results for this new partial-scan algorithm.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"164 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75103860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437658
G. Carlsson, J. Holmqvist, E. Larsson
Integrated circuits, printed circuits boards, and multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/ IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.
{"title":"Protocol requirements in an SJTAG/IJTAG environment","authors":"G. Carlsson, J. Holmqvist, E. Larsson","doi":"10.1109/TEST.2007.4437658","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437658","url":null,"abstract":"Integrated circuits, printed circuits boards, and multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/ IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"241 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77533530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437697
Bernd Gessner
Today, reliability of electronic products is considered as the minimum requirement to ensure the functionality in a safe and reliable way over years. From the semiconductor sector, as the provider from high-integrated circuits, this trend, is one of the main challenges to ensure the reliability of the product, but much more to precisely predict the reliability of those products. austriamicrosystems very early recognized this trend and implemented the zero-defect program over all process steps from design to the end-of-the-life their product. In this paper an overview of the zero-defect program the achievements and the methods are described is shown.
{"title":"How to ensure zero defects from the beginning with semiconductor test methods","authors":"Bernd Gessner","doi":"10.1109/TEST.2007.4437697","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437697","url":null,"abstract":"Today, reliability of electronic products is considered as the minimum requirement to ensure the functionality in a safe and reliable way over years. From the semiconductor sector, as the provider from high-integrated circuits, this trend, is one of the main challenges to ensure the reliability of the product, but much more to precisely predict the reliability of those products. austriamicrosystems very early recognized this trend and implemented the zero-defect program over all process steps from design to the end-of-the-life their product. In this paper an overview of the zero-defect program the achievements and the methods are described is shown.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"62 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77903442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437610
A. Uzzaman, Bibo Li, T. Snethen, B. Keller, Gary Grise
Although on-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.
{"title":"Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation","authors":"A. Uzzaman, Bibo Li, T. Snethen, B. Keller, Gary Grise","doi":"10.1109/TEST.2007.4437610","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437610","url":null,"abstract":"Although on-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"1 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77974258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437702
P. Maxwell
This paper describes several different approaches to obtain test cost reduction, with emphasis on experimental results obtained for a class of ASICs, although the techniques are general. A review is given of some architectural approaches before giving details of techniques which address reduction in test time. The importance of the gathering and analysis of production data is highlighted with a view to better balance wafer and package tests, eliminate ineffective tests, truncate existing tests and carefully examine at which voltage a test should be run. Stress testing is also discussed with the goal of optimizing tests which are run before and after stress.
{"title":"Principles and results of some test cost reduction methods for ASICs","authors":"P. Maxwell","doi":"10.1109/TEST.2007.4437702","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437702","url":null,"abstract":"This paper describes several different approaches to obtain test cost reduction, with emphasis on experimental results obtained for a class of ASICs, although the techniques are general. A review is given of some architectural approaches before giving details of techniques which address reduction in test time. The importance of the gathering and analysis of production data is highlighted with a view to better balance wafer and package tests, eliminate ineffective tests, truncate existing tests and carefully examine at which voltage a test should be run. Stress testing is also discussed with the goal of optimizing tests which are run before and after stress.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"56 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72826799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437598
V. Devanathan, C. Ravikumar, R. Mehrotra, V. Kamakoti
In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a power-managed scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.
{"title":"PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test","authors":"V. Devanathan, C. Ravikumar, R. Mehrotra, V. Kamakoti","doi":"10.1109/TEST.2007.4437598","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437598","url":null,"abstract":"In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a power-managed scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"170 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76943336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437612
Seongmoon Wang, Zhanglei Wang, Wenlong Wei, S. Chakradhar
This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed decompressor can achieve high n-detection fault coverage. The proposed technique computes weight sets from a set of test cubes that are generated by a traditional 1-detection ATPG tool. The computed weight sets are modified to achieve high n-detection fault coverage. The proposed decompressor can be implemented with low area overhead. Since the proposed technique requires no special ATPG that is customized for the proposed scheme, it can compress test patterns generated by any ATPG tool and generate test patterns from the compressed test data that achieve high n-detection fault coverage. Experimental results show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.
{"title":"A low cost test data compression technique for high n-detection fault coverage","authors":"Seongmoon Wang, Zhanglei Wang, Wenlong Wei, S. Chakradhar","doi":"10.1109/TEST.2007.4437612","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437612","url":null,"abstract":"This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed decompressor can achieve high n-detection fault coverage. The proposed technique computes weight sets from a set of test cubes that are generated by a traditional 1-detection ATPG tool. The computed weight sets are modified to achieve high n-detection fault coverage. The proposed decompressor can be implemented with low area overhead. Since the proposed technique requires no special ATPG that is customized for the proposed scheme, it can compress test patterns generated by any ATPG tool and generate test patterns from the compressed test data that achieve high n-detection fault coverage. Experimental results show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"30 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82316969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437660
S. Ravi
Power-aware test is increasingly becoming a major manufacturing test consideration due to the problems of increased power dissipation in various test modes as well as test implications that arise due to the usage of various low-power design technologies in devices today. Several challenges emerge for test engineers and test tool developers, including (and not restricted to) understanding of various concerns associated with power-aware test, development of power-aware design-for-test (DFT), automatic test pattern generation (ATPG) techniques, and test power analysis flows, evaluation of their efficacy and ensuring easy/rapid deployment. This paper highlights concerns and challenges in power-aware test, surveys various practices drawn from both academia and industry, and points out critical gaps that need to be addressed in the future.
{"title":"Power-aware test: Challenges and solutions","authors":"S. Ravi","doi":"10.1109/TEST.2007.4437660","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437660","url":null,"abstract":"Power-aware test is increasingly becoming a major manufacturing test consideration due to the problems of increased power dissipation in various test modes as well as test implications that arise due to the usage of various low-power design technologies in devices today. Several challenges emerge for test engineers and test tool developers, including (and not restricted to) understanding of various concerns associated with power-aware test, development of power-aware design-for-test (DFT), automatic test pattern generation (ATPG) techniques, and test power analysis flows, evaluation of their efficacy and ensuring easy/rapid deployment. This paper highlights concerns and challenges in power-aware test, surveys various practices drawn from both academia and industry, and points out critical gaps that need to be addressed in the future.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"39 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76372398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437572
Q. Xu, Yubin Zhang, K. Chakrabarty
As feature sizes continue to shrink for newer process technologies, signal integrity (SI) is emerging as a major concern for core-based system-on-a-chip (SoC) integrated circuits. To effectively test SI faults on core-external interconnects, core test wrappers need to be able to generate appropriate transitions at a wrapper output cell (WOC) on the driving side and detect the signal integrity loss at a wrapper input cell on the receiving side. In current wrapper designs, the WOCs for a victim interconnect and its aggressors make transitions at the same time with a common test clock signal in test mode, which is different from the functional mode. This is not adequate for SI test because the time elapsed between the transition of the victim and the transitions of its aggressors significantly affects the behavior of Si-related errors. To address this problem, we propose new IEEE Std. 1500-compliant wrapper designs that are able to apply SI test at functional mode or make transitions with various pre-defined skews between a victim line and its aggressors. We also introduce a novel overshoot detector inside the proposed wrapper. Experimental results show that the proposed wrapper designs are more effective for detecting Si-related errors when compared to existing techniques, with a moderate amount ofDFT overhead.
{"title":"Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs","authors":"Q. Xu, Yubin Zhang, K. Chakrabarty","doi":"10.1109/TEST.2007.4437572","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437572","url":null,"abstract":"As feature sizes continue to shrink for newer process technologies, signal integrity (SI) is emerging as a major concern for core-based system-on-a-chip (SoC) integrated circuits. To effectively test SI faults on core-external interconnects, core test wrappers need to be able to generate appropriate transitions at a wrapper output cell (WOC) on the driving side and detect the signal integrity loss at a wrapper input cell on the receiving side. In current wrapper designs, the WOCs for a victim interconnect and its aggressors make transitions at the same time with a common test clock signal in test mode, which is different from the functional mode. This is not adequate for SI test because the time elapsed between the transition of the victim and the transitions of its aggressors significantly affects the behavior of Si-related errors. To address this problem, we propose new IEEE Std. 1500-compliant wrapper designs that are able to apply SI test at functional mode or make transitions with various pre-defined skews between a victim line and its aggressors. We also introduce a novel overshoot detector inside the proposed wrapper. Experimental results show that the proposed wrapper designs are more effective for detecting Si-related errors when compared to existing techniques, with a moderate amount ofDFT overhead.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"19 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87480284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider the problem of determining the location of open defects in interconnects of deep submicron (DSM) designs. The target defect sites for this work are the vias in interconnects which are known to be defect prone. It is known that in DSM designs below 90 nm technology the circuit parameters may vary widely from nominal or design values and process variations make them less predictable. Thus it becomes necessary to develop methods for locating defect sites without accurate knowledge of circuit parameters. Logic diagnosis which is based on gate level net lists is one such method but the resolution of defect sites obtained by logic diagnosis is considered to be unacceptably low for locating open vias. We investigate a procedure that uses minimal information beyond the net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure.
{"title":"Interconnect open defect diagnosis with minimal physical information","authors":"Chen Liu, Wei Zou, S. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang","doi":"10.1109/TEST.2007.4437580","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437580","url":null,"abstract":"We consider the problem of determining the location of open defects in interconnects of deep submicron (DSM) designs. The target defect sites for this work are the vias in interconnects which are known to be defect prone. It is known that in DSM designs below 90 nm technology the circuit parameters may vary widely from nominal or design values and process variations make them less predictable. Thus it becomes necessary to develop methods for locating defect sites without accurate knowledge of circuit parameters. Logic diagnosis which is based on gate level net lists is one such method but the resolution of defect sites obtained by logic diagnosis is considered to be unacceptably low for locating open vias. We investigate a procedure that uses minimal information beyond the net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"144 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82620990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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