Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562549
Yimao Cai, Poren Tang, Shiqiang Qin, Ru Huang
We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates from both drain side band-to-band tunneling (∼0.66 V) and source-drain leakage (∼0.4 V) when NOR Flash scales into 65 nm, which means to suppress drain disturb it is important to decrease source-drain leakage as well as drain junction leakage during nanoscale Flash cell design.
{"title":"Investigation of source potential impacts on drain disturb in Nanoscale Flash Memory","authors":"Yimao Cai, Poren Tang, Shiqiang Qin, Ru Huang","doi":"10.1109/SNW.2010.5562549","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562549","url":null,"abstract":"We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates from both drain side band-to-band tunneling (∼0.66 V) and source-drain leakage (∼0.4 V) when NOR Flash scales into 65 nm, which means to suppress drain disturb it is important to decrease source-drain leakage as well as drain junction leakage during nanoscale Flash cell design.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"53 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81507938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562587
M. Bjork, K. Moselund, H. Schmid, H. Ghoneim, S. Karg, E. Lortscher, J. Knoch, W. Riess, H. Riel
Today, the continued miniaturization of field effect transistors (FETs) results in major scaling issues that curtail further voltage reduction. The resultant increase in power consumption density limits the overall performance. Therefore, alternative materials and devices are required that support steep sub-threshold slopes and low-voltage operation. The tunnel FET (TFET) is regarded as the most promising candidate because it is based on gate-controlled band-to-band tunneling in a p-i-n+ structure and thus can break the 60 mV/dec limit of conventional FETs [1]. Implementing the TFET principle in the nanowire (NW) geometry provides optimum electrostatic control. Here we demonstrate controlled in-situ doping of silicon (Si) NWs, the effect of scaling on the active number of doping atoms in the NW and the implementation of a Si NW TFET.
{"title":"VLS-grown silicon nanowires — Dopant deactivation and tunnel FETs","authors":"M. Bjork, K. Moselund, H. Schmid, H. Ghoneim, S. Karg, E. Lortscher, J. Knoch, W. Riess, H. Riel","doi":"10.1109/SNW.2010.5562587","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562587","url":null,"abstract":"Today, the continued miniaturization of field effect transistors (FETs) results in major scaling issues that curtail further voltage reduction. The resultant increase in power consumption density limits the overall performance. Therefore, alternative materials and devices are required that support steep sub-threshold slopes and low-voltage operation. The tunnel FET (TFET) is regarded as the most promising candidate because it is based on gate-controlled band-to-band tunneling in a p-i-n+ structure and thus can break the 60 mV/dec limit of conventional FETs [1]. Implementing the TFET principle in the nanowire (NW) geometry provides optimum electrostatic control. Here we demonstrate controlled in-situ doping of silicon (Si) NWs, the effect of scaling on the active number of doping atoms in the NW and the implementation of a Si NW TFET.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85504832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562569
Qian Xie, Jun Xu
We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.
{"title":"Analysis of SCEs in nanoscale FinFET with high-k gate dielectric","authors":"Qian Xie, Jun Xu","doi":"10.1109/SNW.2010.5562569","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562569","url":null,"abstract":"We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"380 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77760327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562585
H. Ryu, S. Lee, B. Weber, S. Mahapatra, M. Simmons, L. Hollenberg, Gerhard Klimeck
Highly phosphorous-doped nanowires in silicon (Si:P NW) represent the ultimate nanowire scaling limit of 1 atom thickness and a few atoms width. Experimental data are compared to an atomistic full-band model. Charge-potential self-consistency is computed by solving the exchange-correlation LDA corrected Schrödinger-Poisson equation. Transport through donor bands is observed in [110] Si:P NW at low temperature. The semi-metallic conductance computed in the ballistic regime agrees well with the experiment. Sensitivity of the NW properties on doping constant and placement disorder on the channel is addressed. The modeling confirms that the nanowires are semi-metallic and transport can be gate modulated.
{"title":"Quantum transport in ultra-scaled phosphorous-doped silicon nanowires","authors":"H. Ryu, S. Lee, B. Weber, S. Mahapatra, M. Simmons, L. Hollenberg, Gerhard Klimeck","doi":"10.1109/SNW.2010.5562585","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562585","url":null,"abstract":"Highly phosphorous-doped nanowires in silicon (Si:P NW) represent the ultimate nanowire scaling limit of 1 atom thickness and a few atoms width. Experimental data are compared to an atomistic full-band model. Charge-potential self-consistency is computed by solving the exchange-correlation LDA corrected Schrödinger-Poisson equation. Transport through donor bands is observed in [110] Si:P NW at low temperature. The semi-metallic conductance computed in the ballistic regime agrees well with the experiment. Sensitivity of the NW properties on doping constant and placement disorder on the channel is addressed. The modeling confirms that the nanowires are semi-metallic and transport can be gate modulated.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"86 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85068373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562553
Kyung Rok Kim, I. Kang, R. Dutton
We demonstrated RF analysis framework based on tunnel velocity model for Si IBT diodes with ultra-thin tunnel barriers. Microwave and sub-millimeter wave properties of the non-linear NDR characteristics have been investigated in a numerical way with various structural design. The intrinsic cut-off frequency can be obtained up to THz-level for highly doped nanoscale Si tunnel junctions.
{"title":"Modeling and RF analysis of silicon inter-band tunnel diode with THz cut-off frequency","authors":"Kyung Rok Kim, I. Kang, R. Dutton","doi":"10.1109/SNW.2010.5562553","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562553","url":null,"abstract":"We demonstrated RF analysis framework based on tunnel velocity model for Si IBT diodes with ultra-thin tunnel barriers. Microwave and sub-millimeter wave properties of the non-linear NDR characteristics have been investigated in a numerical way with various structural design. The intrinsic cut-off frequency can be obtained up to THz-level for highly doped nanoscale Si tunnel junctions.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"30 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76234888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562568
Jyi-Tsong Lin, Chun-Yu Chen, M. Chiang
Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.
{"title":"Pragmatic study of the nanowire FETs with nonideal gate structures","authors":"Jyi-Tsong Lin, Chun-Yu Chen, M. Chiang","doi":"10.1109/SNW.2010.5562568","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562568","url":null,"abstract":"Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"116 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88083600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562541
E. Hsieh, S. Chung
A new type of inverter built on a specific channel without source/drain junction is proposed. This inverter can be formed by a connected n- and p-doped channel as the substrate and with complementary p- and n-doped gates respectively. The transistor operation is in accumulation mode, different from the conventional CMOS devices with inversion mode of operation. Extensive simulations have been made to demonstrate this transistor with high current density and good short channel control on 10nm technology and beyond. Good inverter characteristics are also shown. This new inverter device will be ready for the 20nm node and beyond.
{"title":"A new type of inverter with Juctionless (J-Less) transistors","authors":"E. Hsieh, S. Chung","doi":"10.1109/SNW.2010.5562541","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562541","url":null,"abstract":"A new type of inverter built on a specific channel without source/drain junction is proposed. This inverter can be formed by a connected n- and p-doped channel as the substrate and with complementary p- and n-doped gates respectively. The transistor operation is in accumulation mode, different from the conventional CMOS devices with inversion mode of operation. Extensive simulations have been made to demonstrate this transistor with high current density and good short channel control on 10nm technology and beyond. Good inverter characteristics are also shown. This new inverter device will be ready for the 20nm node and beyond.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74079721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562579
Kwangseok Lee, W. Choi
In this paper, we propose a novel electromechanical memory cell (T cell). The T cell has been demonstrated successfully by the experimental results of its prototype cell. Also, the operation of a unit cell and that of array have been investigated. The T cell is superior to the previously reported H cell in terms of fabrication process complexity since the T cell needs only two metal layers.
{"title":"Multi-bit electromechanical memory cell for simple fabrication process","authors":"Kwangseok Lee, W. Choi","doi":"10.1109/SNW.2010.5562579","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562579","url":null,"abstract":"In this paper, we propose a novel electromechanical memory cell (T cell). The T cell has been demonstrated successfully by the experimental results of its prototype cell. Also, the operation of a unit cell and that of array have been investigated. The T cell is superior to the previously reported H cell in terms of fabrication process complexity since the T cell needs only two metal layers.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81815767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562588
Y. Morita, S. Migita, W. Mizubayashi, H. Ota
We propose a novel technique for top-down fabrication of Si nanowire (SiNW) field effect transistors (FETs) using active oxidation of the Si channel. The width and line edge roughness of the SiNW channel were simultaneously reduced by active oxidation to 2.8 nm and 1.97 nm (3-σ), respectively. Device performance of ultra-thin SiNW FETs with atomically controlled nanowire-size and nanowire-shape is demonstrated.
{"title":"Novel fabrication technique of sub-10-nm-diameter Si nanowire FET using active oxidation","authors":"Y. Morita, S. Migita, W. Mizubayashi, H. Ota","doi":"10.1109/SNW.2010.5562588","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562588","url":null,"abstract":"We propose a novel technique for top-down fabrication of Si nanowire (SiNW) field effect transistors (FETs) using active oxidation of the Si channel. The width and line edge roughness of the SiNW channel were simultaneously reduced by active oxidation to 2.8 nm and 1.97 nm (3-σ), respectively. Device performance of ultra-thin SiNW FETs with atomically controlled nanowire-size and nanowire-shape is demonstrated.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"45 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73800992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562592
S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, V. Narayanan
Continued miniaturization of transistors has resulted in unprecedented increase in device count leading to high compute capability albeit with increase in energy consumption. Here, we present our research on advanced non silicon electronic material systems and novel device architectures — quantum-well FETs, inter-band tunnel FETs and tunnel-coupled nanodot devices - for heterogeneous integration on Si substrate. The goal is to demonstrate a compelling information processing platform that allows very aggressive scaling of supply voltage, thereby reducing energy consumption in future computing systems.
{"title":"Non-silicon logic elements on silicon for extreme voltage scaling","authors":"S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, V. Narayanan","doi":"10.1109/SNW.2010.5562592","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562592","url":null,"abstract":"Continued miniaturization of transistors has resulted in unprecedented increase in device count leading to high compute capability albeit with increase in energy consumption. Here, we present our research on advanced non silicon electronic material systems and novel device architectures — quantum-well FETs, inter-band tunnel FETs and tunnel-coupled nanodot devices - for heterogeneous integration on Si substrate. The goal is to demonstrate a compelling information processing platform that allows very aggressive scaling of supply voltage, thereby reducing energy consumption in future computing systems.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88141483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：