This paper presents a novel scheme for reversible data hiding with lossless recovery of original image. Scheme applies a method for hiding data in an image before encryption and then utilizes a novel method for encrypting the image using visual cryptography. A modified algorithm for reversible data hiding using difference expansion technique is used in this scheme. The proposed scheme thus increases the amount of data that can be hidden in the image which also guarantees the lossless recovery of an image after the extraction phase. The performance of the proposed reversible data hiding scheme is evaluated using different color images and compared with few existing schemes. The results clearly indicate that the proposed scheme can embed more data with less distortion of encoded image and also promises the lossless recovery of original image after data is extracted from decrypted image.
{"title":"New Approach for Reversible Data Hiding Using Visual Cryptography","authors":"Shruti M. Rakhunde, A. Nikose","doi":"10.1109/CICN.2014.180","DOIUrl":"https://doi.org/10.1109/CICN.2014.180","url":null,"abstract":"This paper presents a novel scheme for reversible data hiding with lossless recovery of original image. Scheme applies a method for hiding data in an image before encryption and then utilizes a novel method for encrypting the image using visual cryptography. A modified algorithm for reversible data hiding using difference expansion technique is used in this scheme. The proposed scheme thus increases the amount of data that can be hidden in the image which also guarantees the lossless recovery of an image after the extraction phase. The performance of the proposed reversible data hiding scheme is evaluated using different color images and compared with few existing schemes. The results clearly indicate that the proposed scheme can embed more data with less distortion of encoded image and also promises the lossless recovery of original image after data is extracted from decrypted image.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87410731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a new design of compact band-reject frequency selective surfaces is proposed. Compared to previous compact structures, the FSS proposed has a better compact performance with the dimension of a unit cell only 0.082λ × 0.082λ where λ represents the wavelength of the resonant frequency. Above design rejects Wimax band (3.3-3.8) GHz. Moreover, the proposed design has a stable response with respect to different polarization characteristics and different incident angles of the incident plane wave. The squashed performance can further be improved by changing width of patch. The design is aimed at the rejection of Wimax band.
{"title":"A Compact Band-Reject Frequency Selective Surface with Stable Response for Wimax Applications","authors":"H. S. Mewara, S. Yadav, Sushila Choudhary","doi":"10.1109/CICN.2014.12","DOIUrl":"https://doi.org/10.1109/CICN.2014.12","url":null,"abstract":"In this letter, a new design of compact band-reject frequency selective surfaces is proposed. Compared to previous compact structures, the FSS proposed has a better compact performance with the dimension of a unit cell only 0.082λ × 0.082λ where λ represents the wavelength of the resonant frequency. Above design rejects Wimax band (3.3-3.8) GHz. Moreover, the proposed design has a stable response with respect to different polarization characteristics and different incident angles of the incident plane wave. The squashed performance can further be improved by changing width of patch. The design is aimed at the rejection of Wimax band.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87454134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diabetic Retinopathy is a severe and wide-spread eye disease, it is the main cause of blindness for the working age population in western countries. For the diagnosis of Diabetic Retinopathy, digital color fundus images are becoming increasingly important. This fact opens the possibility of applying image processing techniques in order to facilitate and improve diagnosis in different ways. As micro aneurysms are earliest sign of DR, therefore an algorithm able to automatically detect the micro aneurysms in fundus image captured is a necessary preprocessing step for a correct diagnosis. Some methods that address this problem can be found in the literature but they have some drawbacks like accuracy or speed. This system aims to develop and test a new method for detecting the micro aneurysms in retina images. Gray level 2D feature based vessel extraction is done using neural network to do preprocessing. The method is evaluated on DRIVE database and prove to be superior than rule based methods. To identify micro aneurysms in an image morphological opening and image enhancement is performed. A MATLAB implementation of the complete algorithm is developed and tests suggest that the diagnosis in an image can be estimated in shorter time than previous techniques with the same or better accuracy.
{"title":"Neural Network Based Method for the Diagnosis of Diabetic Retinopathy","authors":"Dipika Gadriye, Gopichand D. Khandale","doi":"10.1109/CICN.2014.225","DOIUrl":"https://doi.org/10.1109/CICN.2014.225","url":null,"abstract":"Diabetic Retinopathy is a severe and wide-spread eye disease, it is the main cause of blindness for the working age population in western countries. For the diagnosis of Diabetic Retinopathy, digital color fundus images are becoming increasingly important. This fact opens the possibility of applying image processing techniques in order to facilitate and improve diagnosis in different ways. As micro aneurysms are earliest sign of DR, therefore an algorithm able to automatically detect the micro aneurysms in fundus image captured is a necessary preprocessing step for a correct diagnosis. Some methods that address this problem can be found in the literature but they have some drawbacks like accuracy or speed. This system aims to develop and test a new method for detecting the micro aneurysms in retina images. Gray level 2D feature based vessel extraction is done using neural network to do preprocessing. The method is evaluated on DRIVE database and prove to be superior than rule based methods. To identify micro aneurysms in an image morphological opening and image enhancement is performed. A MATLAB implementation of the complete algorithm is developed and tests suggest that the diagnosis in an image can be estimated in shorter time than previous techniques with the same or better accuracy.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75991343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research focuses on the problem of cell edge user coverage in the context of femtocell networks operating within the locality of macro cell border. The macro cell-edge users get assisted by the cognitive-femto base station (FBS) to receive a consistent quality of service (QoS) because of their long distance from the macro base station (MBS). Considering various environment factors such as wall structure, number of walls, distance between macro cell and users, interference effect (i.e., cotier and cross-tier), we compute not only the overall outage probability of single input single output (SISO) system and single input multiple output (SIMO) system users but also based on sub carrier and power allocation the performance of the two tier network is analysed with macro cell throughput as the performance metric. Finally, the effectiveness of the scheme is verified by extensive matlab simulation.
{"title":"Performance Improvement of Outage Users at Cell Edges through Cognitive-Femtocell Deployment over Macrocell Network","authors":"Joydev Ghosh, Sanjay Dhar Roy","doi":"10.1109/CICN.2014.107","DOIUrl":"https://doi.org/10.1109/CICN.2014.107","url":null,"abstract":"This research focuses on the problem of cell edge user coverage in the context of femtocell networks operating within the locality of macro cell border. The macro cell-edge users get assisted by the cognitive-femto base station (FBS) to receive a consistent quality of service (QoS) because of their long distance from the macro base station (MBS). Considering various environment factors such as wall structure, number of walls, distance between macro cell and users, interference effect (i.e., cotier and cross-tier), we compute not only the overall outage probability of single input single output (SISO) system and single input multiple output (SIMO) system users but also based on sub carrier and power allocation the performance of the two tier network is analysed with macro cell throughput as the performance metric. Finally, the effectiveness of the scheme is verified by extensive matlab simulation.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80036302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cloud computing is one of the major technologies which has gained popularity in computer sciences and information technology domain. Cloud computing has changed the way of doing business by an enterprise in general and data management, retrieval & storage within a business enterprise in particular. Smartphone usage has grown rapidly in tandem with cloud computing by providing different services/applications using cloud computing. Most of the Smartphone do run on Android operating system. Android OS is the widely used Smartphone operating systems with huge user base. Everyday hundreds and thousands of application are added to the repository of Android by different vendors and are easily available for installation to android users. As most of the applications are developed by third party giving way to possible loopholes which result in different threats to security & privacy of data. These threats are critical when a user is suing cloud storage or services on Smartphone devices and if the device is stolen it may lead to access of information by an unauthorized user. This unauthorized access to information can be misused which creates distrust among the users of cloud computing on android devices. In this paper a methodology has been proposed to secure data and information from unauthorized access using android cloud application.
{"title":"Anti-theft Cloud Apps for Android Operating System","authors":"A. Wahid, Khaleel Ahmad, Gaurav Tyagi, M. Rizvi","doi":"10.1109/CICN.2014.165","DOIUrl":"https://doi.org/10.1109/CICN.2014.165","url":null,"abstract":"Cloud computing is one of the major technologies which has gained popularity in computer sciences and information technology domain. Cloud computing has changed the way of doing business by an enterprise in general and data management, retrieval & storage within a business enterprise in particular. Smartphone usage has grown rapidly in tandem with cloud computing by providing different services/applications using cloud computing. Most of the Smartphone do run on Android operating system. Android OS is the widely used Smartphone operating systems with huge user base. Everyday hundreds and thousands of application are added to the repository of Android by different vendors and are easily available for installation to android users. As most of the applications are developed by third party giving way to possible loopholes which result in different threats to security & privacy of data. These threats are critical when a user is suing cloud storage or services on Smartphone devices and if the device is stolen it may lead to access of information by an unauthorized user. This unauthorized access to information can be misused which creates distrust among the users of cloud computing on android devices. In this paper a methodology has been proposed to secure data and information from unauthorized access using android cloud application.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86145578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible logic is widely being considered as the probable logic design style for implementation in modern nanotechnology, optical computing and quantum computing with least impact on physical entropy as because of its less power dissipation as well as distinct output assignment for each distinct input. A reversible circuit maps each output vector into a unique input vector, and vice versa. This paper proposes a new reversible gate. This paper represents various classical operations of this proposed reversible gate. It also represents different sequential circuit elements of reversible gate and its application in designing different synchronous cyclic code counters. The proposed reversible gate is better for designing reversible counter compared to those gates reported in the literature in terms of garbage output, quantum cost and complexity of gates. These synchronous reversible counters give the initial threshold to construct the more complex structure having reversible sequential circuits as a primary component and which can implement more complex operations using quantum computers. Since the output of a sequential circuit depends not only on the present inputs but also on the past input conditions, the construction of sequential elements using reversible logic gates is quite complex than that of a combinational circuit. This paper proposes reversible D flip flop, JK flip flop, T flip flop and also represents two types of 4 bit synchronous cyclic code decade counter (SCCDC) and a 4 bit synchronous gray cyclic code counter (SGCCC) using proposed reversible T flip flop. A comparison between these designs in terms of garbage output, number of gates, constant input and total logical calculation also has been made.
{"title":"Efficient Designing Approach of Different Synchronous Cyclic Code Counters by Sequential Circuit Elements of a Novel Reversible Gate","authors":"Shefali Mamataj, B. Das","doi":"10.1109/CICN.2014.217","DOIUrl":"https://doi.org/10.1109/CICN.2014.217","url":null,"abstract":"Reversible logic is widely being considered as the probable logic design style for implementation in modern nanotechnology, optical computing and quantum computing with least impact on physical entropy as because of its less power dissipation as well as distinct output assignment for each distinct input. A reversible circuit maps each output vector into a unique input vector, and vice versa. This paper proposes a new reversible gate. This paper represents various classical operations of this proposed reversible gate. It also represents different sequential circuit elements of reversible gate and its application in designing different synchronous cyclic code counters. The proposed reversible gate is better for designing reversible counter compared to those gates reported in the literature in terms of garbage output, quantum cost and complexity of gates. These synchronous reversible counters give the initial threshold to construct the more complex structure having reversible sequential circuits as a primary component and which can implement more complex operations using quantum computers. Since the output of a sequential circuit depends not only on the present inputs but also on the past input conditions, the construction of sequential elements using reversible logic gates is quite complex than that of a combinational circuit. This paper proposes reversible D flip flop, JK flip flop, T flip flop and also represents two types of 4 bit synchronous cyclic code decade counter (SCCDC) and a 4 bit synchronous gray cyclic code counter (SGCCC) using proposed reversible T flip flop. A comparison between these designs in terms of garbage output, number of gates, constant input and total logical calculation also has been made.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88392730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Area, Speed and power are the basic design constraints which affects the performance of VLSI circuits. The main hurdle in the VLSI implementation of digital circuits is that either the design can be area efficient or power efficient or speed efficient; but not all area-time-speed efficient simultaneously. Optimizing one parameter affects the other. In this paper, an optimal multi-objective approach for VLSI implementation of digital circuit has been suggested; wherein digital low pass symmetric finite impulse response (FIR) filter has been selected as case study. Simulation results with gscl 45 nm tech file on Synopsis Design Vision Tool and Xilinx tool shows that the proposed modification in existing direct form FIR filter structure has reduced area up to 96.52 %, power by 97.44 % and can also improve the circuit latency (or speed) considerably, compared to the existing direct form digital FIR filter structure, and also modified direct form FIR filter structure is efficient than transposed direct form FIR filter structure.
{"title":"Multi-objective Optimization for VLSI Circuits","authors":"Jitesh R. Shinde, S. Salankar","doi":"10.1109/CICN.2014.218","DOIUrl":"https://doi.org/10.1109/CICN.2014.218","url":null,"abstract":"Area, Speed and power are the basic design constraints which affects the performance of VLSI circuits. The main hurdle in the VLSI implementation of digital circuits is that either the design can be area efficient or power efficient or speed efficient; but not all area-time-speed efficient simultaneously. Optimizing one parameter affects the other. In this paper, an optimal multi-objective approach for VLSI implementation of digital circuit has been suggested; wherein digital low pass symmetric finite impulse response (FIR) filter has been selected as case study. Simulation results with gscl 45 nm tech file on Synopsis Design Vision Tool and Xilinx tool shows that the proposed modification in existing direct form FIR filter structure has reduced area up to 96.52 %, power by 97.44 % and can also improve the circuit latency (or speed) considerably, compared to the existing direct form digital FIR filter structure, and also modified direct form FIR filter structure is efficient than transposed direct form FIR filter structure.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88742103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
From the seventies of the last century the all-optical universal logic gate has formed as an unconventional form of computing. It is very new relatively in the area of extensive applications in low power CMOS, quantum computing, DNA computing, digital signal processing (DSP), nanotechnology, communication, computer graphics, etc. Here we present and configure a new universal gate (AG gate) in all-optical domain and also in this paper we have explained their principle of operations and used a theoretical model to fulfil this task, finally supporting through numerical simulations. In the field of ultra-fast all-optical signal processing Mach-Zehnder interferometer (MZI), semiconductor optical amplifier (SOA) -based, has an important function. The different logical (realization of Boolean function) operations can be executed by designed circuits with AG gate in the domain of reversible logic-based information processing.
{"title":"An All-Optical New Universal Gate Using Mach-Zehnder Interferometer","authors":"A. K. Mandal, G. Maity","doi":"10.1109/CICN.2014.219","DOIUrl":"https://doi.org/10.1109/CICN.2014.219","url":null,"abstract":"From the seventies of the last century the all-optical universal logic gate has formed as an unconventional form of computing. It is very new relatively in the area of extensive applications in low power CMOS, quantum computing, DNA computing, digital signal processing (DSP), nanotechnology, communication, computer graphics, etc. Here we present and configure a new universal gate (AG gate) in all-optical domain and also in this paper we have explained their principle of operations and used a theoretical model to fulfil this task, finally supporting through numerical simulations. In the field of ultra-fast all-optical signal processing Mach-Zehnder interferometer (MZI), semiconductor optical amplifier (SOA) -based, has an important function. The different logical (realization of Boolean function) operations can be executed by designed circuits with AG gate in the domain of reversible logic-based information processing.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77526967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ad-hoc network, due to its fundamental characteristics like open environment operation, random topology and capability limitation, is mostly at risk from security point of view. There may be malicious threats during data transmission from one user to another user, which leads to affect the system performance and causing insecurity in data transmission. Many routing protocols consider these security issues as major point of consideration and hence try to overcome the security threats in ad-hoc networks. In this article, a scenario is set up for simulation to evaluate the performance and security issue of two secure routing protocols that are secure ad-hoc on demand vector (SAODV) and secure zone routing protocol (SZRP). In this paper, simulation has been done for number of times with different values of pause time ranging from 0 to 800 seconds for both protocols. And finally, simulation has been done for malicious environment with different numbers of malicious nodes ranging from 2 to 18 nodes for both protocols. Our analysis has been done under two performance metrics-one is packet delivery ratio and second is end to end delay. Experimental results have been obtained using NS-2 (version 2.34) mainly. We have prepared excel graphs from. Tr (trace) files. Based on experimental outcomes paper concluded, that SZRP outperforms SAODV for real time applications.
{"title":"Experimental Security Analysis for SAODV vs SZRP in Ad-Hoc Networks","authors":"M. Yadav, S. Gupta, R. K. Saket","doi":"10.1109/CICN.2014.175","DOIUrl":"https://doi.org/10.1109/CICN.2014.175","url":null,"abstract":"Ad-hoc network, due to its fundamental characteristics like open environment operation, random topology and capability limitation, is mostly at risk from security point of view. There may be malicious threats during data transmission from one user to another user, which leads to affect the system performance and causing insecurity in data transmission. Many routing protocols consider these security issues as major point of consideration and hence try to overcome the security threats in ad-hoc networks. In this article, a scenario is set up for simulation to evaluate the performance and security issue of two secure routing protocols that are secure ad-hoc on demand vector (SAODV) and secure zone routing protocol (SZRP). In this paper, simulation has been done for number of times with different values of pause time ranging from 0 to 800 seconds for both protocols. And finally, simulation has been done for malicious environment with different numbers of malicious nodes ranging from 2 to 18 nodes for both protocols. Our analysis has been done under two performance metrics-one is packet delivery ratio and second is end to end delay. Experimental results have been obtained using NS-2 (version 2.34) mainly. We have prepared excel graphs from. Tr (trace) files. Based on experimental outcomes paper concluded, that SZRP outperforms SAODV for real time applications.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91537222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design and analysis of ultrahigh birefringent photonic crystal fiber having low confinement loss and nearly zero dispersion characteristics has been presented. The suggested design has phosphate glass rectangular slab surrounded by rectangular array of four air holes in core region and circular air holes in the cladding region. Photonic crystal fiber structure is designed, simulated and analyzed by using opti FDTD simulation software. The proposed design shows ultrahigh birefringence (~0.023) and low confinement loss at 1.55μm. Such high value of birefringence eliminates fluctuation in polarization state.
{"title":"Design and Analysis of Polarization Maintaining Ultrahigh Birefringent, Dispersion Flattened Photonic Crystal Fiber Having Low Confinement Loss","authors":"R. Dhaka","doi":"10.1109/CICN.2014.47","DOIUrl":"https://doi.org/10.1109/CICN.2014.47","url":null,"abstract":"Design and analysis of ultrahigh birefringent photonic crystal fiber having low confinement loss and nearly zero dispersion characteristics has been presented. The suggested design has phosphate glass rectangular slab surrounded by rectangular array of four air holes in core region and circular air holes in the cladding region. Photonic crystal fiber structure is designed, simulated and analyzed by using opti FDTD simulation software. The proposed design shows ultrahigh birefringence (~0.023) and low confinement loss at 1.55μm. Such high value of birefringence eliminates fluctuation in polarization state.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91551430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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