Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325600
K. Fischer, M. Agostinelli, C. Allen, D. Bahr, M. Bost, P. Charvat, V. Chikarmane, Q. Fu, C. Ganpule, M. Haran, M. Heckscher, H. Hiramatsu, E. Hwang, P. Jain, I. Jin, R. Kasim, S. Kosaraju, K. Lee, H. Liu, R. McFadden, S. Nigam, R. Patel, C. Pelto, P. Plekhanov, M. Prince, C. Puls, S. Rajamani, D. Rao, P. Reese, A. Rosenbaum, S. Sivakumar, B. Song, M. Uncuer, S. Williams, M. Yang, P. Yashar, S. Natarajan
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.
{"title":"Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing","authors":"K. Fischer, M. Agostinelli, C. Allen, D. Bahr, M. Bost, P. Charvat, V. Chikarmane, Q. Fu, C. Ganpule, M. Haran, M. Heckscher, H. Hiramatsu, E. Hwang, P. Jain, I. Jin, R. Kasim, S. Kosaraju, K. Lee, H. Liu, R. McFadden, S. Nigam, R. Patel, C. Pelto, P. Plekhanov, M. Prince, C. Puls, S. Rajamani, D. Rao, P. Reese, A. Rosenbaum, S. Sivakumar, B. Song, M. Uncuer, S. Williams, M. Yang, P. Yashar, S. Natarajan","doi":"10.1109/IITC-MAM.2015.7325600","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325600","url":null,"abstract":"We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"10 1","pages":"5-8"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87914554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325659
Chang-Chun Lee, Yu-Min Lin, Yan-Yu Liou, C. Zhan, Tao-Chih Chang
To overcome the severe challenges of achieving an extra-thin thickness down to 10 μm for chip stacking of 3D-IC module such as the mechanical damages appear at chip grinding, subsequent steps of wafer handling, and robust assembly, a novel pre-molding technology applied to assembled stacked module prior to chip thinning procedure is presented in this study. Packaging vehicle is fabricated to demonstrate the feasibility of proposed approach. Moreover, failure estimation and mechanical reliability are also implemented by using a 3D nonlinear finite element analysis.
{"title":"Fabrication, assembly, failure estimations of for ultra-thin chips stacking by using pre-molding technology","authors":"Chang-Chun Lee, Yu-Min Lin, Yan-Yu Liou, C. Zhan, Tao-Chih Chang","doi":"10.1109/IITC-MAM.2015.7325659","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325659","url":null,"abstract":"To overcome the severe challenges of achieving an extra-thin thickness down to 10 μm for chip stacking of 3D-IC module such as the mechanical damages appear at chip grinding, subsequent steps of wafer handling, and robust assembly, a novel pre-molding technology applied to assembled stacked module prior to chip thinning procedure is presented in this study. Packaging vehicle is fabricated to demonstrate the feasibility of proposed approach. Moreover, failure estimation and mechanical reliability are also implemented by using a 3D nonlinear finite element analysis.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"74 1","pages":"237-240"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89205174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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