Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325592
Yunlong Li, S. Van Huylenbroeck, P. Roussel, M. Brouri, S. Gopinath, D. M. Anjos, Matthew Thorum, Jengyi Yu, G. Beyer, E. Beyne, K. Croes
In high aspect ratio TSV's, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3 micron and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctri) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.
{"title":"Reliability study of liner/barrier/seed options for via-middle TSV's with 3 micron diameter and below","authors":"Yunlong Li, S. Van Huylenbroeck, P. Roussel, M. Brouri, S. Gopinath, D. M. Anjos, Matthew Thorum, Jengyi Yu, G. Beyer, E. Beyne, K. Croes","doi":"10.1109/IITC-MAM.2015.7325592","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325592","url":null,"abstract":"In high aspect ratio TSV's, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3 micron and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctri) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"327-330"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84779408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325602
Tzu-Hao Fu, Y. Ke, Shi-Chun Tsai, Chun-Ling Lin, Kuo-Wei Chen, M. Huang, Gary Cho, San-Fu Lin, Ting-Jun Wang, A. Cheng
For advance node such as 14nm technology and beyond, back end of line interconnect has implemented self-aligned via (SAV) schemes for better via-metal short process window [1]. A TiN metal hard mask (MHM) is used for the trench pattern definition, after which via lithography and partial via (PV) etch is performed where the TiN was opened. The via etch condition has very good selectivity so that via is formed in a self-aligned fashion by TiN HM [2]. It is indeed to have significant benefit of via to metal short [3]. However, one of the trade off in SAV scheme is the via under etch that whether or not via can well land on an opened oxide area during PV etch. To define the contact area between via resist hole and opened HM oxide as an effective area for via to open successfully. “Fig. 1” shows the effective area change during process variation due to Via alignment, Via photo resist CD variation (Via ADICD) and post hard mask etch CD variation (AMICD). “Fig. 2” shows the mechanism of this under etch failure mode and typical TEM image from 64nm metal pitch test vehicle. In this work, we try to enlarge the process window by an aggressive AMICD targeting in combining with a higher density TiN material to maintain profile.
{"title":"Robust TiN HM process to overcome under etch issue for SAV scheme on 14nm node","authors":"Tzu-Hao Fu, Y. Ke, Shi-Chun Tsai, Chun-Ling Lin, Kuo-Wei Chen, M. Huang, Gary Cho, San-Fu Lin, Ting-Jun Wang, A. Cheng","doi":"10.1109/IITC-MAM.2015.7325602","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325602","url":null,"abstract":"For advance node such as 14nm technology and beyond, back end of line interconnect has implemented self-aligned via (SAV) schemes for better via-metal short process window [1]. A TiN metal hard mask (MHM) is used for the trench pattern definition, after which via lithography and partial via (PV) etch is performed where the TiN was opened. The via etch condition has very good selectivity so that via is formed in a self-aligned fashion by TiN HM [2]. It is indeed to have significant benefit of via to metal short [3]. However, one of the trade off in SAV scheme is the via under etch that whether or not via can well land on an opened oxide area during PV etch. To define the contact area between via resist hole and opened HM oxide as an effective area for via to open successfully. “Fig. 1” shows the effective area change during process variation due to Via alignment, Via photo resist CD variation (Via ADICD) and post hard mask etch CD variation (AMICD). “Fig. 2” shows the mechanism of this under etch failure mode and typical TEM image from 64nm metal pitch test vehicle. In this work, we try to enlarge the process window by an aggressive AMICD targeting in combining with a higher density TiN material to maintain profile.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"60 9 1","pages":"13-16"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81303516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325662
Jongwoo Park, Miji Lee, Hanbyul Kang, Donghwan Lee, Jungin Kim, S. Pae
Enhanced etch rate in the phosphorus enriched area in PTEOS/BPSG stacked interlayer dielectric (ILD) during contact open process were shown to have tungsten notch and micro-crack nucleation at the interface. Subsequent CVD TiN and W deposition can lead to penetration into this micro-crack that can lead to delamination after temperature cycling (TC) stress test. The notch defect was a result of higher etch rate at the PTEOS/BPSG interface due to high phosphorous concentration and profile associated with intrinsic process parameters and SACVD equipment. With further process optimization and tight process control, such defect free and robust production has been archived. Detailed failure mechanism using TEM and TOF-SIMS analyses and critical process parameters will be discussed and then intrinsic attributes of the SACVD equipment will be presented.
{"title":"TC degradation and root-cause analysis of SACVD BPSG film for robust IC fabrication","authors":"Jongwoo Park, Miji Lee, Hanbyul Kang, Donghwan Lee, Jungin Kim, S. Pae","doi":"10.1109/IITC-MAM.2015.7325662","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325662","url":null,"abstract":"Enhanced etch rate in the phosphorus enriched area in PTEOS/BPSG stacked interlayer dielectric (ILD) during contact open process were shown to have tungsten notch and micro-crack nucleation at the interface. Subsequent CVD TiN and W deposition can lead to penetration into this micro-crack that can lead to delamination after temperature cycling (TC) stress test. The notch defect was a result of higher etch rate at the PTEOS/BPSG interface due to high phosphorous concentration and profile associated with intrinsic process parameters and SACVD equipment. With further process optimization and tight process control, such defect free and robust production has been archived. Detailed failure mechanism using TEM and TOF-SIMS analyses and critical process parameters will be discussed and then intrinsic attributes of the SACVD equipment will be presented.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"18 1","pages":"261-264"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88482405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325635
K. Courouble, L. Broussous, S. Zoll, K. Haxaire, M. Mellier, G. Druais
In this paper, wet cleaning solution compatible with cobalt are investigated to achieve low Co etching rate on blankets film and no film attack on patterned 14nm wafer after line and via etching. Proposed solutions are compared to conventional wet cleaning solutions.
{"title":"Cobalt compatible cleaning solutions for 14nm and beyond","authors":"K. Courouble, L. Broussous, S. Zoll, K. Haxaire, M. Mellier, G. Druais","doi":"10.1109/IITC-MAM.2015.7325635","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325635","url":null,"abstract":"In this paper, wet cleaning solution compatible with cobalt are investigated to achieve low Co etching rate on blankets film and no film attack on patterned 14nm wafer after line and via etching. Proposed solutions are compared to conventional wet cleaning solutions.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"397 1","pages":"119-122"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76458339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325611
Renato Aguilera, Eleanor Demis, Kelsey S. Scharnhorst, A. Stieg, M. Aono, J. Gimzewski
We discuss the utility of ASNs as a uniquely scalable physical platform capable of hybrid-CMOS architectures and novel computation. Through a combination of controlled design with spontaneous self-organization, an atomic switch network (ASN) has been produce as a purpose-built complex system. A highly interconnected system of Ag2S resistive switches, the ASN has been shown to produce fault-tolerant switching and a set of complex dynamics similar to biological neural networks.
{"title":"Morphic atomic switch networks for beyond-Moore computing architectures","authors":"Renato Aguilera, Eleanor Demis, Kelsey S. Scharnhorst, A. Stieg, M. Aono, J. Gimzewski","doi":"10.1109/IITC-MAM.2015.7325611","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325611","url":null,"abstract":"We discuss the utility of ASNs as a uniquely scalable physical platform capable of hybrid-CMOS architectures and novel computation. Through a combination of controlled design with spontaneous self-organization, an atomic switch network (ASN) has been produce as a purpose-built complex system. A highly interconnected system of Ag2S resistive switches, the ASN has been shown to produce fault-tolerant switching and a set of complex dynamics similar to biological neural networks.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"24 1","pages":"165-168"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77956053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325631
Shiwei Wang, Yingtao Ding, Huanyu He, Jian-Qiang Lu
This paper reports on the vertical noise coupling between a clock wire in digital IC and channel routing wires in analog IC in 3D mixed signal integration. Full wave electromagnetic simulations are employed to evaluate the vertical noise coupling. The coupling mechanism is discussed with transfer impedance. Insights to vertical noise coupling between interconnects in 3D integration are offered and possible solutions are provided to reduce the noise.
{"title":"Modeling and analysis of vertical noise coupling between clock tree and channel routing wire in 3D mixed signal integration","authors":"Shiwei Wang, Yingtao Ding, Huanyu He, Jian-Qiang Lu","doi":"10.1109/IITC-MAM.2015.7325631","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325631","url":null,"abstract":"This paper reports on the vertical noise coupling between a clock wire in digital IC and channel routing wires in analog IC in 3D mixed signal integration. Full wave electromagnetic simulations are employed to evaluate the vertical noise coupling. The coupling mechanism is discussed with transfer impedance. Insights to vertical noise coupling between interconnects in 3D integration are offered and possible solutions are provided to reduce the noise.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"21 1","pages":"79-82"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78129235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325628
J. Bogan, A. McCoy, C. Byrne, R. O'Connor, G. Hughes
The surface treatment of low-k dielectric layers by exposure to atomic oxygen is presented as an alternative to plasma based treatments prior to barrier layer formation. High carbon content porous low-k dielectric films were subjected to increasing exposures of atomic oxygen and X-ray photoelectron spectroscopy (XPS) studies reveal both the depletion of carbon and the addition of oxygen at the surface. This treatment is shown to be thermally stable up to 400 °C. High resolution electron energy loss spectroscopy (EELS) elemental profiles show the removal of carbon from the surface of the treated films to a depth of ~ 20 nm. In a separate experiment manganese (~1-2 nm) was deposited on an oxygen treated substrate and thermally annealed to form MnSiO3. It is shown that the modification of the low-k surface made the chemical identification of MnSiO3 formation possible by XPS analysis.
{"title":"Atomic oxygen treatment of carbon containing low-k dielectric materials to facilitate manganese silicate barrier formation","authors":"J. Bogan, A. McCoy, C. Byrne, R. O'Connor, G. Hughes","doi":"10.1109/IITC-MAM.2015.7325628","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325628","url":null,"abstract":"The surface treatment of low-k dielectric layers by exposure to atomic oxygen is presented as an alternative to plasma based treatments prior to barrier layer formation. High carbon content porous low-k dielectric films were subjected to increasing exposures of atomic oxygen and X-ray photoelectron spectroscopy (XPS) studies reveal both the depletion of carbon and the addition of oxygen at the surface. This treatment is shown to be thermally stable up to 400 °C. High resolution electron energy loss spectroscopy (EELS) elemental profiles show the removal of carbon from the surface of the treated films to a depth of ~ 20 nm. In a separate experiment manganese (~1-2 nm) was deposited on an oxygen treated substrate and thermally annealed to form MnSiO3. It is shown that the modification of the low-k surface made the chemical identification of MnSiO3 formation possible by XPS analysis.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"29 1","pages":"67-70"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87512377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325589
Shintaro Sato
Nanocarbon materials including graphene and carbon nanotubes (CNTs) are promising candidates for future LSI interconnects. We recently demonstrated sub-10-nm-wide graphene interconnects whose resistivity is lower than that of Cu with similar dimensions. In this paper, we first describe the fabrication and evaluation of such graphene interconnects. We then explain a newly-developed fabrication process for carbon nanotube (CNT) vias and plugs, which relies on implantation of CNTs into sub-micrometer-sized holes. We then point out further issues to be addressed for realizing nanocarbon interconnects.
{"title":"Nanocarbon interconnects: Demonstration of properties better than Cu and remaining issues","authors":"Shintaro Sato","doi":"10.1109/IITC-MAM.2015.7325589","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325589","url":null,"abstract":"Nanocarbon materials including graphene and carbon nanotubes (CNTs) are promising candidates for future LSI interconnects. We recently demonstrated sub-10-nm-wide graphene interconnects whose resistivity is lower than that of Cu with similar dimensions. In this paper, we first describe the fabrication and evaluation of such graphene interconnects. We then explain a newly-developed fabrication process for carbon nanotube (CNT) vias and plugs, which relies on implantation of CNTs into sub-micrometer-sized holes. We then point out further issues to be addressed for realizing nanocarbon interconnects.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"31 1","pages":"313-316"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86026511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325652
J. Derakhshandeh, I. de Preter, K. Vandersmissen, D. Dictus, L. di Piazza, L. Hou, S. Guerrieri, G. Vakanas, S. Armini, R. Daily, A. Lesniewska, Yannick Vandelaer, M. Van De Peer, J. Slabbekoorn, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer and single IMC (intermetallic compounds) and according to calculations using Cobalt as UBM can reduce consumption of UBM material by solder which is attractive for sub 10um pitches of microbumps. However, cobalt oxidizes very fast which results in poor wetting by solder as shown in Figure 1. This Figure shows two SEM images of cross section of 20um (left) and 50um (right) pitches microbumps from IMEC test vehicles where poor solder wetting is observed. It can be seen than in both cases Sn is deformed during TCB (thermo-compression bonding) bonding but due to oxide formation on cobalt bumps there is no reaction between Sn and Co. Such a joints may have weak electrical connection however, it is not suitable for a reliable device. Therefore surface treatment/passivation is required for cobalt bumps.
{"title":"Cobalt UBM for fine pitch microbump applications in 3DIC","authors":"J. Derakhshandeh, I. de Preter, K. Vandersmissen, D. Dictus, L. di Piazza, L. Hou, S. Guerrieri, G. Vakanas, S. Armini, R. Daily, A. Lesniewska, Yannick Vandelaer, M. Van De Peer, J. Slabbekoorn, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/IITC-MAM.2015.7325652","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325652","url":null,"abstract":"In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer and single IMC (intermetallic compounds) and according to calculations using Cobalt as UBM can reduce consumption of UBM material by solder which is attractive for sub 10um pitches of microbumps. However, cobalt oxidizes very fast which results in poor wetting by solder as shown in Figure 1. This Figure shows two SEM images of cross section of 20um (left) and 50um (right) pitches microbumps from IMEC test vehicles where poor solder wetting is observed. It can be seen than in both cases Sn is deformed during TCB (thermo-compression bonding) bonding but due to oxide formation on cobalt bumps there is no reaction between Sn and Co. Such a joints may have weak electrical connection however, it is not suitable for a reliable device. Therefore surface treatment/passivation is required for cobalt bumps.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"221-224"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88147364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325656
Qiran Xiao, Brian L. Watson, R. Dauskardt
The presence of weak Cu-oxides has detrimental implications for the adhesion, moisture sensitivity, stress-and electro-migration of Cu bondlines in advanced packaging, often leading to premature device failure. We report on a novel, low-cost, single-step sol-gel synthetic route capable of reducing the weak Cu-oxide while simultaneously depositing a high-performance hybrid film, which acts both as an adhesion layer at the Cu/epoxy interface, as well as potentially a barrier film that prevents moisture degradation and Cu stress- and electro-migration.
{"title":"Low-cost, single-step hybrid bond/barrier films for Cu bondlines in advanced packaging","authors":"Qiran Xiao, Brian L. Watson, R. Dauskardt","doi":"10.1109/IITC-MAM.2015.7325656","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325656","url":null,"abstract":"The presence of weak Cu-oxides has detrimental implications for the adhesion, moisture sensitivity, stress-and electro-migration of Cu bondlines in advanced packaging, often leading to premature device failure. We report on a novel, low-cost, single-step sol-gel synthetic route capable of reducing the weak Cu-oxide while simultaneously depositing a high-performance hybrid film, which acts both as an adhesion layer at the Cu/epoxy interface, as well as potentially a barrier film that prevents moisture degradation and Cu stress- and electro-migration.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"94 1","pages":"225-228"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83557145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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