Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325596
L. Zhang, J. de Marneffe, N. Heylen, G. Murdoch, Z. Tokei, J. Boemmels, S. De Gendt, M. Baklanov
Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.
{"title":"Alternative integration of ultralow-k dielectrics by template replacement approach","authors":"L. Zhang, J. de Marneffe, N. Heylen, G. Murdoch, Z. Tokei, J. Boemmels, S. De Gendt, M. Baklanov","doi":"10.1109/IITC-MAM.2015.7325596","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325596","url":null,"abstract":"Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"70 1","pages":"345-348"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83271779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325664
E. Ghegin, F. Nemouchi, J. Lábár, S. Favier, C. Perrin, K. Hoummada, S. Gurbán, P. Gergaud
The metallurgical properties of the Ni/n-InP system have been investigated. We report the formation of a compositionally nonuniform Ni-In-P amorphous layer during the DC sputtering metal deposition process which includes an Ar+ cleaning. After RTP and long in situ annealing treatments the simultaneous appearance of the Ni2P and Ni3P binary phases and the Ni2InP ternary phase were observed. Kinetics and nucleation phenomena were highlighted by the precipitation of In during the RTP.
{"title":"Solid state reaction of Ni thin film on n-InP susbtrate for III-V laser contact technology","authors":"E. Ghegin, F. Nemouchi, J. Lábár, S. Favier, C. Perrin, K. Hoummada, S. Gurbán, P. Gergaud","doi":"10.1109/IITC-MAM.2015.7325664","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325664","url":null,"abstract":"The metallurgical properties of the Ni/n-InP system have been investigated. We report the formation of a compositionally nonuniform Ni-In-P amorphous layer during the DC sputtering metal deposition process which includes an Ar+ cleaning. After RTP and long in situ annealing treatments the simultaneous appearance of the Ni2P and Ni3P binary phases and the Ni2InP ternary phase were observed. Kinetics and nucleation phenomena were highlighted by the precipitation of In during the RTP.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"84 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91252931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325628
J. Bogan, A. McCoy, C. Byrne, R. O'Connor, G. Hughes
The surface treatment of low-k dielectric layers by exposure to atomic oxygen is presented as an alternative to plasma based treatments prior to barrier layer formation. High carbon content porous low-k dielectric films were subjected to increasing exposures of atomic oxygen and X-ray photoelectron spectroscopy (XPS) studies reveal both the depletion of carbon and the addition of oxygen at the surface. This treatment is shown to be thermally stable up to 400 °C. High resolution electron energy loss spectroscopy (EELS) elemental profiles show the removal of carbon from the surface of the treated films to a depth of ~ 20 nm. In a separate experiment manganese (~1-2 nm) was deposited on an oxygen treated substrate and thermally annealed to form MnSiO3. It is shown that the modification of the low-k surface made the chemical identification of MnSiO3 formation possible by XPS analysis.
{"title":"Atomic oxygen treatment of carbon containing low-k dielectric materials to facilitate manganese silicate barrier formation","authors":"J. Bogan, A. McCoy, C. Byrne, R. O'Connor, G. Hughes","doi":"10.1109/IITC-MAM.2015.7325628","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325628","url":null,"abstract":"The surface treatment of low-k dielectric layers by exposure to atomic oxygen is presented as an alternative to plasma based treatments prior to barrier layer formation. High carbon content porous low-k dielectric films were subjected to increasing exposures of atomic oxygen and X-ray photoelectron spectroscopy (XPS) studies reveal both the depletion of carbon and the addition of oxygen at the surface. This treatment is shown to be thermally stable up to 400 °C. High resolution electron energy loss spectroscopy (EELS) elemental profiles show the removal of carbon from the surface of the treated films to a depth of ~ 20 nm. In a separate experiment manganese (~1-2 nm) was deposited on an oxygen treated substrate and thermally annealed to form MnSiO3. It is shown that the modification of the low-k surface made the chemical identification of MnSiO3 formation possible by XPS analysis.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"29 1","pages":"67-70"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87512377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325666
T. Horikawa, D. Shimura, Seok-Hwan Jeong, M. Tokushima, K. Kinoshita, T. Mogami
Precise dimension control technology for the fabrication of silicon photonics devices was established. The dimension control technology is based on the devices fabrication using 40-nm-node CMOS technology and in-line process monitoring by optical wafer-level probing system. As the results of process optimization in waveguide formation, superior dimension control in 440-nm-wide / 220-nm-thick waveguides was achieved, in which waveguide width deviation of 1.0 nm and height deviation of0.3 nm were respectively obtained for a single 300-mmφ wafer. In the characterization of 5th-order coupled resonator optical waveguides (CROWs), remarkably small deviation of resonant frequency 0.7 nm in a single wafer was confirmed, which values agreed with the theoretical estimation from the fabrication error. As for the optical wafer-level probing system, quite small deviation less than 0.2 dB in I/O coupling loss between optical devices under test and fiber probe was confirmed. It was successfully shown that the combination of the precise process control and the in-line optical process control monitor is sufficient to the reproducible device fabrication for wide-bandwidth optical interconnection.
{"title":"Process control and monitoring in device fabrication for optical interconnection using silicon photonics technology","authors":"T. Horikawa, D. Shimura, Seok-Hwan Jeong, M. Tokushima, K. Kinoshita, T. Mogami","doi":"10.1109/IITC-MAM.2015.7325666","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325666","url":null,"abstract":"Precise dimension control technology for the fabrication of silicon photonics devices was established. The dimension control technology is based on the devices fabrication using 40-nm-node CMOS technology and in-line process monitoring by optical wafer-level probing system. As the results of process optimization in waveguide formation, superior dimension control in 440-nm-wide / 220-nm-thick waveguides was achieved, in which waveguide width deviation of 1.0 nm and height deviation of0.3 nm were respectively obtained for a single 300-mmφ wafer. In the characterization of 5th-order coupled resonator optical waveguides (CROWs), remarkably small deviation of resonant frequency 0.7 nm in a single wafer was confirmed, which values agreed with the theoretical estimation from the fabrication error. As for the optical wafer-level probing system, quite small deviation less than 0.2 dB in I/O coupling loss between optical devices under test and fiber probe was confirmed. It was successfully shown that the combination of the precise process control and the in-line optical process control monitor is sufficient to the reproducible device fabrication for wide-bandwidth optical interconnection.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"23 2 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75041279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325660
Manseok Park, Sungdong Kim, S. Kim
The development of 3D integration causes the major technology paradigm shift to all of IC devices, interconnects, and packages. Despite the benefits of 3D integration, it faces a key challenge of thermal management, especially for high power and high density devices. Due to the limitation of conventional thermal solutions, a liquid cooling method is of great interest. In this study the direct liquid cooling module with different TSVs and microchannel has been designed and fabricated. Pressure drop and temperature differential of liquid cooling module were investigated experimentally.
{"title":"Experimental characterization of TSV liquid cooling for 3D integration","authors":"Manseok Park, Sungdong Kim, S. Kim","doi":"10.1109/IITC-MAM.2015.7325660","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325660","url":null,"abstract":"The development of 3D integration causes the major technology paradigm shift to all of IC devices, interconnects, and packages. Despite the benefits of 3D integration, it faces a key challenge of thermal management, especially for high power and high density devices. Due to the limitation of conventional thermal solutions, a liquid cooling method is of great interest. In this study the direct liquid cooling module with different TSVs and microchannel has been designed and fabricated. Pressure drop and temperature differential of liquid cooling module were investigated experimentally.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"241-244"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74450854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325594
Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, S. Lim
Despite many predictions that 3D IC is the solution for future low-power electronics, few studies describe how this can happen in real designs. In this paper, we investigate the practical design factors that affect the power consumption of 3D IC using a commercial-grade large-scale benchmark (OpenSPARC T2). In particular, we investigate the impact of power distribution network (PDN) in designer's perspective. Our study shows that PDN significantly affects several important design metrics in addition to the total power.
{"title":"3D IC power benefit study under practical design considerations","authors":"Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, S. Lim","doi":"10.1109/IITC-MAM.2015.7325594","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325594","url":null,"abstract":"Despite many predictions that 3D IC is the solution for future low-power electronics, few studies describe how this can happen in real designs. In this paper, we investigate the practical design factors that affect the power consumption of 3D IC using a commercial-grade large-scale benchmark (OpenSPARC T2). In particular, we investigate the impact of power distribution network (PDN) in designer's perspective. Our study shows that PDN significantly affects several important design metrics in addition to the total power.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"17 1","pages":"335-338"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74332270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325621
E. Ping
Summary form only given. We will review the potentials of several new memory adoptions in market, and their power, performance and reliability expectations from basic operation mechanisms. Challenges of interconnect will be highlighted in the read and programming for PCRAM, STTRAM, OxRAM and CBRAM; and solution spaces in novel materials, processing and integration are discussed to support the operations at product level. Architectures to achieve high memory density such as cross-point and 3D schemes are also shown to demonstrate the need of new materials for interconnect integration, specifically for memories that show high current program required for high temperature data retention.
{"title":"Interconnect for emerging new memories","authors":"E. Ping","doi":"10.1109/IITC-MAM.2015.7325621","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325621","url":null,"abstract":"Summary form only given. We will review the potentials of several new memory adoptions in market, and their power, performance and reliability expectations from basic operation mechanisms. Challenges of interconnect will be highlighted in the read and programming for PCRAM, STTRAM, OxRAM and CBRAM; and solution spaces in novel materials, processing and integration are discussed to support the operations at product level. Architectures to achieve high memory density such as cross-point and 3D schemes are also shown to demonstrate the need of new materials for interconnect integration, specifically for memories that show high current program required for high temperature data retention.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"52 1","pages":"211-212"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87218410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325618
K. Vandersmissen, F. Inoue, D. Velenis, Y. Li, D. Dictus, B. Frees, S. Van Huylenbroeck, M. Kondo, T. Seino, N. Heylen, H. Struyf, M. H. van der Veen
In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 μm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material on the costs for the deposition and chemical mechanical polishing part of the TSV metallization. In addition, we demonstrated a complete TSV filling for the 3.5 nm ALD-Ru case and investigated different kinds of Cu electrodeposition chemistries and their influence on the presence of micro-voids in the TSVs.
{"title":"Demonstration of a cost effective Cu electroless TSV metallization scheme","authors":"K. Vandersmissen, F. Inoue, D. Velenis, Y. Li, D. Dictus, B. Frees, S. Van Huylenbroeck, M. Kondo, T. Seino, N. Heylen, H. Struyf, M. H. van der Veen","doi":"10.1109/IITC-MAM.2015.7325618","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325618","url":null,"abstract":"In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 μm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material on the costs for the deposition and chemical mechanical polishing part of the TSV metallization. In addition, we demonstrated a complete TSV filling for the 3.5 nm ALD-Ru case and investigated different kinds of Cu electrodeposition chemistries and their influence on the presence of micro-voids in the TSVs.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"33 1","pages":"197-200"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85560804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325641
M. Redzheb, L. Prager, M. Krishtab, S. Armini, K. Vanstreels, A. Franquet, P. Van Der Voort, M. Baklanov
Advanced spin-on k 2.3 films with -40% porosity were enabled by liquid phase self-assembly (LPSA) mechanism on Si substrates. UV-assisted thermal template removal is investigated as a faster alternative to the conventional thermal process. The as-deposited films were exposed to narrow-band UV light of 172 nm, 222 nm, 254 nm or 185/254 nm at 400°C for different time. The optical, mechanical, chemical and electrical properties of the resulting films are discussed in this work. Photons with wavelength of about 172 nm from one side are detrimental to the electrical and chemical properties of the low-k films but from the other side notably improve the porous low-k mechanical properties. Exposure to 222 nm light as short as 3 min. is more efficient in terms of template removal when compared to 2h thermal cure, while in both cases similar mechanical and electrical properties are reported. UV-cure using 254 nm or dual band 254/185 nm photons seem to have a minor contribution to the template removal efficiency for the applied doses. Higher doses are necessary in order to better understand the effective contribution of these photon energies. Finally, the HF etching mechanism is discussed.
{"title":"Impact of UV wavelength and curing time on the properties of spin-coated low-k films","authors":"M. Redzheb, L. Prager, M. Krishtab, S. Armini, K. Vanstreels, A. Franquet, P. Van Der Voort, M. Baklanov","doi":"10.1109/IITC-MAM.2015.7325641","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325641","url":null,"abstract":"Advanced spin-on k 2.3 films with -40% porosity were enabled by liquid phase self-assembly (LPSA) mechanism on Si substrates. UV-assisted thermal template removal is investigated as a faster alternative to the conventional thermal process. The as-deposited films were exposed to narrow-band UV light of 172 nm, 222 nm, 254 nm or 185/254 nm at 400°C for different time. The optical, mechanical, chemical and electrical properties of the resulting films are discussed in this work. Photons with wavelength of about 172 nm from one side are detrimental to the electrical and chemical properties of the low-k films but from the other side notably improve the porous low-k mechanical properties. Exposure to 222 nm light as short as 3 min. is more efficient in terms of template removal when compared to 2h thermal cure, while in both cases similar mechanical and electrical properties are reported. UV-cure using 254 nm or dual band 254/185 nm photons seem to have a minor contribution to the template removal efficiency for the applied doses. Higher doses are necessary in order to better understand the effective contribution of these photon energies. Finally, the HF etching mechanism is discussed.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"3 1","pages":"99-102"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82767878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325608
Mariela Menghini, P. Homm, Chen-Yi Su, J. Kittl, R. Tomita, G. Hegde, Joon-Gon Lee, S. Hyun, C. Bowen, M. Rodder, V. Afanas’ev, J. Locquet
Contact schemes for scaled Si, SiGe and Ge channel MOSFETs devices are discussed, consistent with an approach based on SiGe alloys with low Schottky Barrier Height (SBH) for pMOS and Si contacts for nMOS, making reduction of the SBH to nSi critical. Methods for SBH reduction, and their underlying mechanisms, are studied. Accurate cryogenic CV measurements were used to extract SBH. We show that chalcogenide segregation can be effective in lowering the SBH by a dipole effect, while MIS contacts have a partial un-pinning effect. SBH=0.00±0.01 eV was achieved.
{"title":"Modulation of the Schottky barrier height for advanced contact schemes","authors":"Mariela Menghini, P. Homm, Chen-Yi Su, J. Kittl, R. Tomita, G. Hegde, Joon-Gon Lee, S. Hyun, C. Bowen, M. Rodder, V. Afanas’ev, J. Locquet","doi":"10.1109/IITC-MAM.2015.7325608","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325608","url":null,"abstract":"Contact schemes for scaled Si, SiGe and Ge channel MOSFETs devices are discussed, consistent with an approach based on SiGe alloys with low Schottky Barrier Height (SBH) for pMOS and Si contacts for nMOS, making reduction of the SBH to nSi critical. Methods for SBH reduction, and their underlying mechanisms, are studied. Accurate cryogenic CV measurements were used to extract SBH. We show that chalcogenide segregation can be effective in lowering the SBH by a dipole effect, while MIS contacts have a partial un-pinning effect. SBH=0.00±0.01 eV was achieved.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"20 1","pages":"39-42"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78786864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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