Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325666
T. Horikawa, D. Shimura, Seok-Hwan Jeong, M. Tokushima, K. Kinoshita, T. Mogami
Precise dimension control technology for the fabrication of silicon photonics devices was established. The dimension control technology is based on the devices fabrication using 40-nm-node CMOS technology and in-line process monitoring by optical wafer-level probing system. As the results of process optimization in waveguide formation, superior dimension control in 440-nm-wide / 220-nm-thick waveguides was achieved, in which waveguide width deviation of 1.0 nm and height deviation of0.3 nm were respectively obtained for a single 300-mmφ wafer. In the characterization of 5th-order coupled resonator optical waveguides (CROWs), remarkably small deviation of resonant frequency 0.7 nm in a single wafer was confirmed, which values agreed with the theoretical estimation from the fabrication error. As for the optical wafer-level probing system, quite small deviation less than 0.2 dB in I/O coupling loss between optical devices under test and fiber probe was confirmed. It was successfully shown that the combination of the precise process control and the in-line optical process control monitor is sufficient to the reproducible device fabrication for wide-bandwidth optical interconnection.
{"title":"Process control and monitoring in device fabrication for optical interconnection using silicon photonics technology","authors":"T. Horikawa, D. Shimura, Seok-Hwan Jeong, M. Tokushima, K. Kinoshita, T. Mogami","doi":"10.1109/IITC-MAM.2015.7325666","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325666","url":null,"abstract":"Precise dimension control technology for the fabrication of silicon photonics devices was established. The dimension control technology is based on the devices fabrication using 40-nm-node CMOS technology and in-line process monitoring by optical wafer-level probing system. As the results of process optimization in waveguide formation, superior dimension control in 440-nm-wide / 220-nm-thick waveguides was achieved, in which waveguide width deviation of 1.0 nm and height deviation of0.3 nm were respectively obtained for a single 300-mmφ wafer. In the characterization of 5th-order coupled resonator optical waveguides (CROWs), remarkably small deviation of resonant frequency 0.7 nm in a single wafer was confirmed, which values agreed with the theoretical estimation from the fabrication error. As for the optical wafer-level probing system, quite small deviation less than 0.2 dB in I/O coupling loss between optical devices under test and fiber probe was confirmed. It was successfully shown that the combination of the precise process control and the in-line optical process control monitor is sufficient to the reproducible device fabrication for wide-bandwidth optical interconnection.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"23 2 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75041279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325660
Manseok Park, Sungdong Kim, S. Kim
The development of 3D integration causes the major technology paradigm shift to all of IC devices, interconnects, and packages. Despite the benefits of 3D integration, it faces a key challenge of thermal management, especially for high power and high density devices. Due to the limitation of conventional thermal solutions, a liquid cooling method is of great interest. In this study the direct liquid cooling module with different TSVs and microchannel has been designed and fabricated. Pressure drop and temperature differential of liquid cooling module were investigated experimentally.
{"title":"Experimental characterization of TSV liquid cooling for 3D integration","authors":"Manseok Park, Sungdong Kim, S. Kim","doi":"10.1109/IITC-MAM.2015.7325660","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325660","url":null,"abstract":"The development of 3D integration causes the major technology paradigm shift to all of IC devices, interconnects, and packages. Despite the benefits of 3D integration, it faces a key challenge of thermal management, especially for high power and high density devices. Due to the limitation of conventional thermal solutions, a liquid cooling method is of great interest. In this study the direct liquid cooling module with different TSVs and microchannel has been designed and fabricated. Pressure drop and temperature differential of liquid cooling module were investigated experimentally.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"241-244"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74450854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325638
J. Liao, Y. T. Lai, Stan Wan, B. Kuo, P. Gopaladasu, David Wei, S. Yao, Wesley L. Lin, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh
Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.
{"title":"Sub-90nm pitch Cu low-k interconnect etch solution using RF pulsing technology","authors":"J. Liao, Y. T. Lai, Stan Wan, B. Kuo, P. Gopaladasu, David Wei, S. Yao, Wesley L. Lin, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh","doi":"10.1109/IITC-MAM.2015.7325638","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325638","url":null,"abstract":"Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"64 1","pages":"131-134"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91488319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325605
M. H. van der Veen, K. Vandersmissen, D. Dictus, S. Demuynck, R. Liu, X. Bin, P. Nalla, A. Lesniewska, L. Hall, K. Croes, L. Zhao, J. Bommels, A. Kolics, Z. Tokei
This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.
{"title":"Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies","authors":"M. H. van der Veen, K. Vandersmissen, D. Dictus, S. Demuynck, R. Liu, X. Bin, P. Nalla, A. Lesniewska, L. Hall, K. Croes, L. Zhao, J. Bommels, A. Kolics, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325605","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325605","url":null,"abstract":"This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"571 ","pages":"25-28"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91510983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325590
I. Asselberghs, M. Politou, B. Sorée, S. Sayan, D. Lin, P. Pashaei, C. Huyghebaert, P. Raghavan, I. Radu, Z. Tokei
In this paper, we evaluate the material properties of graphene and compare with Cu in order to assess the potential application of graphene to replace copper wires in BEOL interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we measure, a mean-free-path (MFP) of ~150 nm, which exceeds the value for Cu. However, contact engineering will be the key issue for integration of graphene as interconnect.
{"title":"Graphene wires as alternative interconnects","authors":"I. Asselberghs, M. Politou, B. Sorée, S. Sayan, D. Lin, P. Pashaei, C. Huyghebaert, P. Raghavan, I. Radu, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325590","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325590","url":null,"abstract":"In this paper, we evaluate the material properties of graphene and compare with Cu in order to assess the potential application of graphene to replace copper wires in BEOL interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we measure, a mean-free-path (MFP) of ~150 nm, which exceeds the value for Cu. However, contact engineering will be the key issue for integration of graphene as interconnect.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"59 1","pages":"317-320"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90696735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325647
B. Uhlig, J. Calvo, Johannes Koch, X. Thrun, R. Liske
In this work an approach to integrate spin-on deposited ULK in an existing 28 nm BEOL flow is presented. Additionally, this alternative ULK integration avoids any damage by plasma etching, wet cleaning and barrier/seed deposition by employing an alternative integration scheme. This is done by using a sacrificial material and filling the new material in already manufactured dual damascene structures. Critical process steps like the removal of the sacrificial material, filling of the ULK and final planarization are investigated and promising results are presented as a first feasibility study.
{"title":"Alternative ULK integration approach using a sacrificial layer in a standard dual damascene flow","authors":"B. Uhlig, J. Calvo, Johannes Koch, X. Thrun, R. Liske","doi":"10.1109/IITC-MAM.2015.7325647","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325647","url":null,"abstract":"In this work an approach to integrate spin-on deposited ULK in an existing 28 nm BEOL flow is presented. Additionally, this alternative ULK integration avoids any damage by plasma etching, wet cleaning and barrier/seed deposition by employing an alternative integration scheme. This is done by using a sacrificial material and filling the new material in already manufactured dual damascene structures. Critical process steps like the removal of the sacrificial material, filling of the ULK and final planarization are investigated and promising results are presented as a first feasibility study.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"45 4 1","pages":"143-146"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77473467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325632
E. Herth, R. Zeggari, J. Rauch, F. Remy-Martin, W. Boireau
The present study demonstrates that thin layers of amorphous silicon oxide (SiOx) grown by inductively-coupled plasma enhanced chemical vapor deposition (ICPECVD) technology at lower temperatures can be successfully combined with biosensors. In particular, gold-amorphous silica (Au/SiOx) interfaces were investigated for their potential applications as a low-cost Surface Plasmon Resonance (SPR) sensor chip. We report here on the fabrication and characterization of stable and good reliabilities of SiOx deposited at 80°C at different pressures. The refractive index (n) of SiOx varied from 1.456 to 1.462. The results show that the sensitivity and minimum light reflectivity at the resonance angle is extremely sensitive to any changes in the index of refraction and any changes in optical thickness.
{"title":"Thin amorphous silicon oxide ICPECVD layer on gold surface for surface plasmon resonance measurements","authors":"E. Herth, R. Zeggari, J. Rauch, F. Remy-Martin, W. Boireau","doi":"10.1109/IITC-MAM.2015.7325632","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325632","url":null,"abstract":"The present study demonstrates that thin layers of amorphous silicon oxide (SiOx) grown by inductively-coupled plasma enhanced chemical vapor deposition (ICPECVD) technology at lower temperatures can be successfully combined with biosensors. In particular, gold-amorphous silica (Au/SiOx) interfaces were investigated for their potential applications as a low-cost Surface Plasmon Resonance (SPR) sensor chip. We report here on the fabrication and characterization of stable and good reliabilities of SiOx deposited at 80°C at different pressures. The refractive index (n) of SiOx varied from 1.456 to 1.462. The results show that the sensitivity and minimum light reflectivity at the resonance angle is extremely sensitive to any changes in the index of refraction and any changes in optical thickness.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"71 1","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77779418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325636
L. Broussous, M. Lépinay, B. Coasne, C. Licitra, F. Bertin, V. Rouessac, A. Ayral
This study aims to investigate the modified surface porosity of SiOCH low-k porous thin films using statistical mechanics molecular simulations and ellipso-porosimetry. The thin films are modified by plasma etching and wet cleaning. Numerical simulations of solvent adsorption on surfaces highlighted solvent affinity variations depending on chemical surface compositions.
{"title":"Contribution of molecular simulation to the characterization of porous low-k materials","authors":"L. Broussous, M. Lépinay, B. Coasne, C. Licitra, F. Bertin, V. Rouessac, A. Ayral","doi":"10.1109/IITC-MAM.2015.7325636","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325636","url":null,"abstract":"This study aims to investigate the modified surface porosity of SiOCH low-k porous thin films using statistical mechanics molecular simulations and ellipso-porosimetry. The thin films are modified by plasma etching and wet cleaning. Numerical simulations of solvent adsorption on surfaces highlighted solvent affinity variations depending on chemical surface compositions.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"38 1","pages":"123-126"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85815843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325627
S. Zhiou, P. Rodriguez, P. Gergaud, F. Nemouchi, T. Thanh
We studied the solid-state reaction of Ni thin films with InGaAs layers grown on InP or Si substrates. The inter-metallics obtained carried an hexagonal structure, but yielded a difference in orientation regarding either the substrates or the annealing temperature.
{"title":"Influence of the substrate on the solid-state reaction of ultra-thin Ni film with a In0.53Ga0.47As under-layer by means of full 3D reciprocal space mapping","authors":"S. Zhiou, P. Rodriguez, P. Gergaud, F. Nemouchi, T. Thanh","doi":"10.1109/IITC-MAM.2015.7325627","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325627","url":null,"abstract":"We studied the solid-state reaction of Ni thin films with InGaAs layers grown on InP or Si substrates. The inter-metallics obtained carried an hexagonal structure, but yielded a difference in orientation regarding either the substrates or the annealing temperature.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"6 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84787084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325642
M. Krishtab, K. Vanstreels, S. De Gendt, M. Baklanov
In this study we demonstrate an approach for reduction of plasma induced damage in spin-on organosilica low-k dielectric films. These films are deposited from sols containing amphiphilic surfactant molecules as sacrificial phase. Both bulk material hydrophilization and surface roughening caused by etching plasma were significantly lowered. This is related to controlled partial removal of templating organic molecules at the material preparation stage. Short UV-assisted curing with broadband UV-light source (λ > 200 nm) was found to be an efficient strategy for the template residue removal applied after completing the etching process. Three steps of the proposed approach, including initial material pre-formation, etching and cleaning of pore walls from template residue, are investigated on blanket films.
{"title":"Post-etch template removal strategy for reduction of plasma induced damage in spin-on OSG low-k dielectrics","authors":"M. Krishtab, K. Vanstreels, S. De Gendt, M. Baklanov","doi":"10.1109/IITC-MAM.2015.7325642","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325642","url":null,"abstract":"In this study we demonstrate an approach for reduction of plasma induced damage in spin-on organosilica low-k dielectric films. These films are deposited from sols containing amphiphilic surfactant molecules as sacrificial phase. Both bulk material hydrophilization and surface roughening caused by etching plasma were significantly lowered. This is related to controlled partial removal of templating organic molecules at the material preparation stage. Short UV-assisted curing with broadband UV-light source (λ > 200 nm) was found to be an efficient strategy for the template residue removal applied after completing the etching process. Three steps of the proposed approach, including initial material pre-formation, etching and cleaning of pore walls from template residue, are investigated on blanket films.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"5 1","pages":"103-106"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83347830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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