Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325669
Samuel Sofela, Hammad Younes, M. Jelbuldina, I. Saadat, A. Al Ghaferi
We discuss fabrication and characterization of TSVs filled with carbon nano-materials (CNM) for dual function of sensing and vertical interconnect for hostile environment applications (Corrosive High Temperature and Pressure). Nano-composites, made by functionalization of CNTs were integrated using dispersion in epoxy resin and inkjet techniques to fill up the TSVs and provide sensing surface. The results reveal ability for the nano-composite to fill vias with electrical conductivity path and sensing established through the wafer backside.
{"title":"Carbon nanomaterials based TSVs for dual sensing and vertical interconnect application","authors":"Samuel Sofela, Hammad Younes, M. Jelbuldina, I. Saadat, A. Al Ghaferi","doi":"10.1109/IITC-MAM.2015.7325669","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325669","url":null,"abstract":"We discuss fabrication and characterization of TSVs filled with carbon nano-materials (CNM) for dual function of sensing and vertical interconnect for hostile environment applications (Corrosive High Temperature and Pressure). Nano-composites, made by functionalization of CNTs were integrated using dispersion in epoxy resin and inkjet techniques to fill up the TSVs and provide sensing surface. The results reveal ability for the nano-composite to fill vias with electrical conductivity path and sensing established through the wafer backside.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"11 1","pages":"289-292"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81642441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325593
Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, S. Lim
In this paper we study the thermal impact of two high impact design/technology choices for 3D ICs, i.e., block folding and face-to-face bonding. A recent study shows that block folding and face-to-face improve wirelength, power, and performance, but the impact on thermal issue is not studied. Based on commercial-quality 3D IC layouts of large-scale OpenSPARC T2 designs and a highly accurate GDSII-level thermal analysis flow, our results first show that block folding, despite its power density increase, does not worsen thermal issues because of additional TSVs that act as heat conductors. In addition, face-to-face bonding, despite its thermal benefit from the absence of BCB bonding layer and underfill, still does not improve temperature much because of the small F2F via sizes.
{"title":"Thermal impact study of block folding and face-to-face bonding in 3D IC","authors":"Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, S. Lim","doi":"10.1109/IITC-MAM.2015.7325593","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325593","url":null,"abstract":"In this paper we study the thermal impact of two high impact design/technology choices for 3D ICs, i.e., block folding and face-to-face bonding. A recent study shows that block folding and face-to-face improve wirelength, power, and performance, but the impact on thermal issue is not studied. Based on commercial-quality 3D IC layouts of large-scale OpenSPARC T2 designs and a highly accurate GDSII-level thermal analysis flow, our results first show that block folding, despite its power density increase, does not worsen thermal issues because of additional TSVs that act as heat conductors. In addition, face-to-face bonding, despite its thermal benefit from the absence of BCB bonding layer and underfill, still does not improve temperature much because of the small F2F via sizes.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"30 1","pages":"331-334"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85870575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325638
J. Liao, Y. T. Lai, Stan Wan, B. Kuo, P. Gopaladasu, David Wei, S. Yao, Wesley L. Lin, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh
Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.
{"title":"Sub-90nm pitch Cu low-k interconnect etch solution using RF pulsing technology","authors":"J. Liao, Y. T. Lai, Stan Wan, B. Kuo, P. Gopaladasu, David Wei, S. Yao, Wesley L. Lin, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh","doi":"10.1109/IITC-MAM.2015.7325638","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325638","url":null,"abstract":"Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"64 1","pages":"131-134"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91488319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325605
M. H. van der Veen, K. Vandersmissen, D. Dictus, S. Demuynck, R. Liu, X. Bin, P. Nalla, A. Lesniewska, L. Hall, K. Croes, L. Zhao, J. Bommels, A. Kolics, Z. Tokei
This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.
{"title":"Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies","authors":"M. H. van der Veen, K. Vandersmissen, D. Dictus, S. Demuynck, R. Liu, X. Bin, P. Nalla, A. Lesniewska, L. Hall, K. Croes, L. Zhao, J. Bommels, A. Kolics, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325605","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325605","url":null,"abstract":"This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"571 ","pages":"25-28"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91510983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325590
I. Asselberghs, M. Politou, B. Sorée, S. Sayan, D. Lin, P. Pashaei, C. Huyghebaert, P. Raghavan, I. Radu, Z. Tokei
In this paper, we evaluate the material properties of graphene and compare with Cu in order to assess the potential application of graphene to replace copper wires in BEOL interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we measure, a mean-free-path (MFP) of ~150 nm, which exceeds the value for Cu. However, contact engineering will be the key issue for integration of graphene as interconnect.
{"title":"Graphene wires as alternative interconnects","authors":"I. Asselberghs, M. Politou, B. Sorée, S. Sayan, D. Lin, P. Pashaei, C. Huyghebaert, P. Raghavan, I. Radu, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325590","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325590","url":null,"abstract":"In this paper, we evaluate the material properties of graphene and compare with Cu in order to assess the potential application of graphene to replace copper wires in BEOL interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we measure, a mean-free-path (MFP) of ~150 nm, which exceeds the value for Cu. However, contact engineering will be the key issue for integration of graphene as interconnect.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"59 1","pages":"317-320"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90696735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325650
Kyung-Tae Jang, Yong-Jin Park, Min-Woo Jeong, Seung-Min Lim, Han-Wool Ycon, Ju-Young Cho, Jin-Sub Shin, B. Woo, J. Bae, Yuchul Hwang, Young‐Chang Joo
As the design rule for memory devices shrinks, the reliability issue of electromigration (EM) is emerged due 10 the increase of high current density, therefore, the reliability for memory devices can be limited by EM failure of metal lines (Al. Cu. W). But EM reliability with respect to structures of interconnects is still underestimated even though EM behavior for each material has been reported for decades. Therefore, we investigated the kinetics of EM in various metal line and via in memory devices under direct current (DC) stressing because failure of metal interconnects depends not only on metal materials but also on structures of interconnects. Under EM tests, mean time failure of Al with W via was shorter than that of Cu with W via. These results came from abrupt failure behavior due to void nucleation and growth at Al with W via and gradual failure behavior at Cu with W via due to void generation and growth as well as conduction in Ta/TaN. Additionally. Cu with W via showed different behavior compared to Cu with Cu via. It can be explained that the joule heating between W and Cu interface caused lateral void expansion and resistance increases rapidly. And it was observed that W line had the longest lifetime of EM failure but the high resistivity of W should be considered for memory chip design. As the results, we conclude that Al has the weakest reliable property for EM reliability among Al. W and Cu metal lines and W via can affect the degradation of EM reliability. These results mean that reliability of Al and W interconnects beyond nanometer-scale should be improved to guarantee reliability in memory chip. This study could provide the guideline for the optimal materials for interconnects in highly-reliable memory chips.
{"title":"Electromigration-limited reliability of advanced metallization for memory devices","authors":"Kyung-Tae Jang, Yong-Jin Park, Min-Woo Jeong, Seung-Min Lim, Han-Wool Ycon, Ju-Young Cho, Jin-Sub Shin, B. Woo, J. Bae, Yuchul Hwang, Young‐Chang Joo","doi":"10.1109/IITC-MAM.2015.7325650","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325650","url":null,"abstract":"As the design rule for memory devices shrinks, the reliability issue of electromigration (EM) is emerged due 10 the increase of high current density, therefore, the reliability for memory devices can be limited by EM failure of metal lines (Al. Cu. W). But EM reliability with respect to structures of interconnects is still underestimated even though EM behavior for each material has been reported for decades. Therefore, we investigated the kinetics of EM in various metal line and via in memory devices under direct current (DC) stressing because failure of metal interconnects depends not only on metal materials but also on structures of interconnects. Under EM tests, mean time failure of Al with W via was shorter than that of Cu with W via. These results came from abrupt failure behavior due to void nucleation and growth at Al with W via and gradual failure behavior at Cu with W via due to void generation and growth as well as conduction in Ta/TaN. Additionally. Cu with W via showed different behavior compared to Cu with Cu via. It can be explained that the joule heating between W and Cu interface caused lateral void expansion and resistance increases rapidly. And it was observed that W line had the longest lifetime of EM failure but the high resistivity of W should be considered for memory chip design. As the results, we conclude that Al has the weakest reliable property for EM reliability among Al. W and Cu metal lines and W via can affect the degradation of EM reliability. These results mean that reliability of Al and W interconnects beyond nanometer-scale should be improved to guarantee reliability in memory chip. This study could provide the guideline for the optimal materials for interconnects in highly-reliable memory chips.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"11 1","pages":"155-158"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76665187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325647
B. Uhlig, J. Calvo, Johannes Koch, X. Thrun, R. Liske
In this work an approach to integrate spin-on deposited ULK in an existing 28 nm BEOL flow is presented. Additionally, this alternative ULK integration avoids any damage by plasma etching, wet cleaning and barrier/seed deposition by employing an alternative integration scheme. This is done by using a sacrificial material and filling the new material in already manufactured dual damascene structures. Critical process steps like the removal of the sacrificial material, filling of the ULK and final planarization are investigated and promising results are presented as a first feasibility study.
{"title":"Alternative ULK integration approach using a sacrificial layer in a standard dual damascene flow","authors":"B. Uhlig, J. Calvo, Johannes Koch, X. Thrun, R. Liske","doi":"10.1109/IITC-MAM.2015.7325647","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325647","url":null,"abstract":"In this work an approach to integrate spin-on deposited ULK in an existing 28 nm BEOL flow is presented. Additionally, this alternative ULK integration avoids any damage by plasma etching, wet cleaning and barrier/seed deposition by employing an alternative integration scheme. This is done by using a sacrificial material and filling the new material in already manufactured dual damascene structures. Critical process steps like the removal of the sacrificial material, filling of the ULK and final planarization are investigated and promising results are presented as a first feasibility study.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"45 4 1","pages":"143-146"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77473467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325654
Yoonhwan Shin, S. Kim, Sungdong Kim
Thermal management of 3D IC is an important factor in terms of performance and reliability. In this study, the feasibility of Cu TSV as a heat dissipation path was experimentally investigated. 40 μm thick Si wafer was point-heated at 50 °, 100 °, 150 ° and 200 ° and surface temperature profile on the other side was observed using IR microscope. Specimens with TSV showed higher maximum temperature and larger hot area than ones without TSV above 100 °, which implies TSV delivered the heat faster than Si bulk and can be used as a fast heat dissipation path. In a two tier stacked structure, the effect of TSV was not noticeable because of thick substrate wafer.
{"title":"Analysis of thermal effects of through silicon via in 3D IC using Infrared microscopy","authors":"Yoonhwan Shin, S. Kim, Sungdong Kim","doi":"10.1109/IITC-MAM.2015.7325654","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325654","url":null,"abstract":"Thermal management of 3D IC is an important factor in terms of performance and reliability. In this study, the feasibility of Cu TSV as a heat dissipation path was experimentally investigated. 40 μm thick Si wafer was point-heated at 50 °, 100 °, 150 ° and 200 ° and surface temperature profile on the other side was observed using IR microscope. Specimens with TSV showed higher maximum temperature and larger hot area than ones without TSV above 100 °, which implies TSV delivered the heat faster than Si bulk and can be used as a fast heat dissipation path. In a two tier stacked structure, the effect of TSV was not noticeable because of thick substrate wafer.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"8 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81922878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325636
L. Broussous, M. Lépinay, B. Coasne, C. Licitra, F. Bertin, V. Rouessac, A. Ayral
This study aims to investigate the modified surface porosity of SiOCH low-k porous thin films using statistical mechanics molecular simulations and ellipso-porosimetry. The thin films are modified by plasma etching and wet cleaning. Numerical simulations of solvent adsorption on surfaces highlighted solvent affinity variations depending on chemical surface compositions.
{"title":"Contribution of molecular simulation to the characterization of porous low-k materials","authors":"L. Broussous, M. Lépinay, B. Coasne, C. Licitra, F. Bertin, V. Rouessac, A. Ayral","doi":"10.1109/IITC-MAM.2015.7325636","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325636","url":null,"abstract":"This study aims to investigate the modified surface porosity of SiOCH low-k porous thin films using statistical mechanics molecular simulations and ellipso-porosimetry. The thin films are modified by plasma etching and wet cleaning. Numerical simulations of solvent adsorption on surfaces highlighted solvent affinity variations depending on chemical surface compositions.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"38 1","pages":"123-126"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85815843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325616
Haitao Zhang, J. Duchaine, F. Torregrosa, Linjie Liu, B. Hollander, U. Breuer, S. Mantl, Qing-Tai Zhao
We present in this paper high quality thin NiSi contacts on Si for the 16nm node using pre-silicidation CF4 Plasma Immersion Ion Implantation (PIII) The thermal stability, the layer uniformity and the interface roughness of thin NiSi layers are improved by CF4 PIII, which is assumed to be caused by segregation of C, F atoms at the grain boundaries and at the NiSi/Si interface. The Schottky barrier height of NiSi/p-Si is also lowered by CF4 plasma, thus a lower contact resistance on p+ doped Si is expected.
{"title":"Improved NiSi contacts on Si by CF4 plasma immersion ion implantation for 14nm node MOSFETs","authors":"Haitao Zhang, J. Duchaine, F. Torregrosa, Linjie Liu, B. Hollander, U. Breuer, S. Mantl, Qing-Tai Zhao","doi":"10.1109/IITC-MAM.2015.7325616","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325616","url":null,"abstract":"We present in this paper high quality thin NiSi contacts on Si for the 16nm node using pre-silicidation CF4 Plasma Immersion Ion Implantation (PIII) The thermal stability, the layer uniformity and the interface roughness of thin NiSi layers are improved by CF4 PIII, which is assumed to be caused by segregation of C, F atoms at the grain boundaries and at the NiSi/Si interface. The Schottky barrier height of NiSi/p-Si is also lowered by CF4 plasma, thus a lower contact resistance on p+ doped Si is expected.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"17 1","pages":"187-190"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81106259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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