Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325587
K. Cheng, C. Teng, H. Y. Huang, H. C. Chen, C. Shih, T. H. Liu, C. Tsai, C. W. Lu, Y. H. Wu, H. Lee, M. H. Lee, M. Hsieh, B. Lin, S. Hou, C. J. Lee, H. H. Lu, T. Bao, S. Shue, C. H. Yu
High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.
{"title":"A flexible top metal structure to improve ultra low-k reliability","authors":"K. Cheng, C. Teng, H. Y. Huang, H. C. Chen, C. Shih, T. H. Liu, C. Tsai, C. W. Lu, Y. H. Wu, H. Lee, M. H. Lee, M. Hsieh, B. Lin, S. Hou, C. J. Lee, H. H. Lu, T. Bao, S. Shue, C. H. Yu","doi":"10.1109/IITC-MAM.2015.7325587","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325587","url":null,"abstract":"High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"26 1","pages":"303-306"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73577760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325588
H. Matsuyama, Takashi Suzuki, Tomoji Nakamura, M. Shiozu, H. Ehara
We measured Internal residual stress change in the copper interconnect in 12 years to confirm the phenomenon that is occurred in acceleration test are equivalent with that is occurred in use condition or not. We have compared the stress change results and void feature and acceleration test results. With these results, we think same phenomenon (void generate on the surface of the interconnect) occur in the room temperature long time storage with high temperature storage. Also, we reviewed the FEM result of residual stress. There are not so large stress at the surface of the line. However void occurs on the surface especially for the Wide Pattern. That suggests diffusion path plays important role in accelerated and use condition.
{"title":"Re-think stress migration phenomenon with stress measurement in 12 years","authors":"H. Matsuyama, Takashi Suzuki, Tomoji Nakamura, M. Shiozu, H. Ehara","doi":"10.1109/IITC-MAM.2015.7325588","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325588","url":null,"abstract":"We measured Internal residual stress change in the copper interconnect in 12 years to confirm the phenomenon that is occurred in acceleration test are equivalent with that is occurred in use condition or not. We have compared the stress change results and void feature and acceleration test results. With these results, we think same phenomenon (void generate on the surface of the interconnect) occur in the room temperature long time storage with high temperature storage. Also, we reviewed the FEM result of residual stress. There are not so large stress at the surface of the line. However void occurs on the surface especially for the Wide Pattern. That suggests diffusion path plays important role in accelerated and use condition.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"42 1","pages":"307-310"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86866168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325612
Kevin L. Lin, S. Bojarski, C. Carver, M. Chandhok, J. Chawla, J. Clarke, M. Harmes, B. Krist, H. Lang, M. Mayeh, S. Naskar, J. Plombon, S. Sung, H. Yoo
Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.
{"title":"Nickel silicide for interconnects","authors":"Kevin L. Lin, S. Bojarski, C. Carver, M. Chandhok, J. Chawla, J. Clarke, M. Harmes, B. Krist, H. Lang, M. Mayeh, S. Naskar, J. Plombon, S. Sung, H. Yoo","doi":"10.1109/IITC-MAM.2015.7325612","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325612","url":null,"abstract":"Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"12 1","pages":"169-172"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85961720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325623
W. Devulder, K. Opsomer, M. Jurczak, L. Goux, C. Detavernier
Conductive Bridge Random Access Memory (CBRAM) is one of the emerging technologies for future memory devices. However, one of the main challenges is to ensure high temperature data retention. In this work, the use of different copper alloys as cation supply layer and their influence on the retention properties of CBRAM cells are presented. Also the thermal stability of the Cu alloys, which is important to sustain the temperatures applied during device fabrication, is investigated.
{"title":"Influence of alloying the copper supply layer on the retention of CBRAM","authors":"W. Devulder, K. Opsomer, M. Jurczak, L. Goux, C. Detavernier","doi":"10.1109/IITC-MAM.2015.7325623","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325623","url":null,"abstract":"Conductive Bridge Random Access Memory (CBRAM) is one of the emerging technologies for future memory devices. However, one of the main challenges is to ensure high temperature data retention. In this work, the use of different copper alloys as cation supply layer and their influence on the retention properties of CBRAM cells are presented. Also the thermal stability of the Cu alloys, which is important to sustain the temperatures applied during device fabrication, is investigated.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"88 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78174107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325639
J. de Marneffe, L. Zhang, V. Rutigliani, G. Noya, Y. Cao, A. Lesniewska, O. Pedreira, K. Croes, C. Gillot, Z. Tokei, J. Boemmels, M. Baklanov
Plasma processing of porous órgano-silicate Iowie dielectrics, following the damascene approach. remains one the biggest challenge for IC manufacturing. During low-k plasma etching. reactive radicals (O*, F* amongst others) and VUV penetrate easily into the porous low-k structure, reacting with Si-CH3 terminating bonds, ultimately turning the etched low-k hydrophilic and raising the integrated k-value beyond acceptable limits.
{"title":"Optimized pore stuffing for enhanced compatibility with interconnect integration flow","authors":"J. de Marneffe, L. Zhang, V. Rutigliani, G. Noya, Y. Cao, A. Lesniewska, O. Pedreira, K. Croes, C. Gillot, Z. Tokei, J. Boemmels, M. Baklanov","doi":"10.1109/IITC-MAM.2015.7325639","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325639","url":null,"abstract":"Plasma processing of porous órgano-silicate Iowie dielectrics, following the damascene approach. remains one the biggest challenge for IC manufacturing. During low-k plasma etching. reactive radicals (O*, F* amongst others) and VUV penetrate easily into the porous low-k structure, reacting with Si-CH3 terminating bonds, ultimately turning the etched low-k hydrophilic and raising the integrated k-value beyond acceptable limits.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"23 1","pages":"91-94"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78192323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325667
S. Vollebregt, Souri Banerjee, F. Tichelaar, R. Ishihara
Carbon nanotubes (CNT) are an attractive alternative filler material for through silicon vias (TSV) due to their high aspect ratio, attractive mechanical and thermal properties and high current carrying capability. Theoretically they can outperform Cu in terms of via resistance. Until now all CNT TSV reported in the literature were fabricated using electrically isolating catalyst support layers. In this work we demonstrate the growth of CNT with aspect ratios up to 35 on electrically conductive ZrN layers. This was used to fabricate the first CNT TSV which are directly contacted by metal thin-films on both sides of the CNT bundle, instead of resorting to the use of probe needles.
{"title":"Carbon nanotubes TSV grown on an electrically conductive ZrN support layer","authors":"S. Vollebregt, Souri Banerjee, F. Tichelaar, R. Ishihara","doi":"10.1109/IITC-MAM.2015.7325667","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325667","url":null,"abstract":"Carbon nanotubes (CNT) are an attractive alternative filler material for through silicon vias (TSV) due to their high aspect ratio, attractive mechanical and thermal properties and high current carrying capability. Theoretically they can outperform Cu in terms of via resistance. Until now all CNT TSV reported in the literature were fabricated using electrically isolating catalyst support layers. In this work we demonstrate the growth of CNT with aspect ratios up to 35 on electrically conductive ZrN layers. This was used to fabricate the first CNT TSV which are directly contacted by metal thin-films on both sides of the CNT bundle, instead of resorting to the use of probe needles.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"43 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79894410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325607
Matthias M. Minjauw, J. Dendooven, Boris Capon, C. Detavernier, M. Schaekers
A thermal (RuO4/H2-gas) and a plasma enhanced (RuO4/H2-plasma) atomic layer deposition (ALD) process for deposition of Ru are reported. The ALD characteristics and film properties of both processes are presented. The thermal process is compared to the plasma process in terms of film properties as a function of sample temperature. Finally, a discussion about the probable ALD reaction mechanisms is given.
{"title":"Low temperature thermal and plasma enhanced atomic layer deposition of ruthenium using RuO4 and H2/H2-plasma","authors":"Matthias M. Minjauw, J. Dendooven, Boris Capon, C. Detavernier, M. Schaekers","doi":"10.1109/IITC-MAM.2015.7325607","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325607","url":null,"abstract":"A thermal (RuO4/H2-gas) and a plasma enhanced (RuO4/H2-plasma) atomic layer deposition (ALD) process for deposition of Ru are reported. The ALD characteristics and film properties of both processes are presented. The thermal process is compared to the plasma process in terms of film properties as a function of sample temperature. Finally, a discussion about the probable ALD reaction mechanisms is given.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"183 1","pages":"33-36"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77901071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325653
C. Song, K. Xue, S. Yang, Z. Yong, H. Li, X. Jing, U. Lee, W. Zhang
3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10×100 um void-free copper filled TSVs. Mechanical and electrical performances of these liner and barrier/seed are also studied in order to give reliability guidelines for process optimization. It is found that the PECVD TEOS film shows high breakdown voltage, capacitance and low stepcoverage, while the thermal oxide film offers almost 100% stepcoverage and low leakage current. Hence thermal oxide/ PECVD TEOS bi-layer is formed to combine the advantage of each layer. A thin thermal oxide layer can also enlarge the Cu TSV backside reveal process window when Si is etched by HF contained solution. 2.5D integration of functional chips is finally achieved, from which good eye diagram is observed. For further scaling up the aspect ratio of TSV, novel barrier/seed deposition methods are also investigated and void-free Cu plating is successfully achieved.
{"title":"Si interposer with high aspect ratio copper filled TSV for system integration","authors":"C. Song, K. Xue, S. Yang, Z. Yong, H. Li, X. Jing, U. Lee, W. Zhang","doi":"10.1109/IITC-MAM.2015.7325653","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325653","url":null,"abstract":"3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10×100 um void-free copper filled TSVs. Mechanical and electrical performances of these liner and barrier/seed are also studied in order to give reliability guidelines for process optimization. It is found that the PECVD TEOS film shows high breakdown voltage, capacitance and low stepcoverage, while the thermal oxide film offers almost 100% stepcoverage and low leakage current. Hence thermal oxide/ PECVD TEOS bi-layer is formed to combine the advantage of each layer. A thin thermal oxide layer can also enlarge the Cu TSV backside reveal process window when Si is etched by HF contained solution. 2.5D integration of functional chips is finally achieved, from which good eye diagram is observed. For further scaling up the aspect ratio of TSV, novel barrier/seed deposition methods are also investigated and void-free Cu plating is successfully achieved.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"245-248"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81956918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325626
B. Vianne, C. Krauss, S. Escoubas, M. Richard, S. Labaf, G. Chahine, T. Schullli, J. Micha, V. Fiori, A. Farcy, O. Thomas
TSV-induced stress is extensively studied in silicon interposer by using two different submicron resolution X-ray diffraction techniques. Simulations are performed to interpret the experimental strain results. Stress and strain in silicon are found to be small at room temperature, while measurements and simulations at annealing temperature (400 °C) support a plastic behavior of copper in some regions of the TSV.
{"title":"Effect of the temperature on the strain distribution induced in silicon interposer by TSVs: A comparison between micro-Laue and monochromatic nanodiffraction","authors":"B. Vianne, C. Krauss, S. Escoubas, M. Richard, S. Labaf, G. Chahine, T. Schullli, J. Micha, V. Fiori, A. Farcy, O. Thomas","doi":"10.1109/IITC-MAM.2015.7325626","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325626","url":null,"abstract":"TSV-induced stress is extensively studied in silicon interposer by using two different submicron resolution X-ray diffraction techniques. Simulations are performed to interpret the experimental strain results. Stress and strain in silicon are found to be small at room temperature, while measurements and simulations at annealing temperature (400 °C) support a plastic behavior of copper in some regions of the TSV.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"65 1","pages":"59-62"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86328359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325629
D. Mangelinck, M. Putero, M. Descoins, C. Perrin-Pellegrino
In situ sheet resistance and x-ray diffraction measurements were used simultaneously during heat treatment to study Ti electrodes in contact with Ge-Te phase change materials. Ti is found to react with GeTe forming TiTe2 and Ge. Atom probe tomography analyses confirm the presence of these two phases after a 400°C heat treatment.
{"title":"Stability of GeTe-based phase change material stack under thermal stress: Reaction with Ti studied by combined in-situ x-ray diffraction, sheet resistance and atom probe tomography","authors":"D. Mangelinck, M. Putero, M. Descoins, C. Perrin-Pellegrino","doi":"10.1109/IITC-MAM.2015.7325629","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325629","url":null,"abstract":"In situ sheet resistance and x-ray diffraction measurements were used simultaneously during heat treatment to study Ti electrodes in contact with Ge-Te phase change materials. Ti is found to react with GeTe forming TiTe2 and Ge. Atom probe tomography analyses confirm the presence of these two phases after a 400°C heat treatment.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"8 1","pages":"71-74"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87790722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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