Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325654
Yoonhwan Shin, S. Kim, Sungdong Kim
Thermal management of 3D IC is an important factor in terms of performance and reliability. In this study, the feasibility of Cu TSV as a heat dissipation path was experimentally investigated. 40 μm thick Si wafer was point-heated at 50 °, 100 °, 150 ° and 200 ° and surface temperature profile on the other side was observed using IR microscope. Specimens with TSV showed higher maximum temperature and larger hot area than ones without TSV above 100 °, which implies TSV delivered the heat faster than Si bulk and can be used as a fast heat dissipation path. In a two tier stacked structure, the effect of TSV was not noticeable because of thick substrate wafer.
{"title":"Analysis of thermal effects of through silicon via in 3D IC using Infrared microscopy","authors":"Yoonhwan Shin, S. Kim, Sungdong Kim","doi":"10.1109/IITC-MAM.2015.7325654","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325654","url":null,"abstract":"Thermal management of 3D IC is an important factor in terms of performance and reliability. In this study, the feasibility of Cu TSV as a heat dissipation path was experimentally investigated. 40 μm thick Si wafer was point-heated at 50 °, 100 °, 150 ° and 200 ° and surface temperature profile on the other side was observed using IR microscope. Specimens with TSV showed higher maximum temperature and larger hot area than ones without TSV above 100 °, which implies TSV delivered the heat faster than Si bulk and can be used as a fast heat dissipation path. In a two tier stacked structure, the effect of TSV was not noticeable because of thick substrate wafer.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"8 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81922878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325650
Kyung-Tae Jang, Yong-Jin Park, Min-Woo Jeong, Seung-Min Lim, Han-Wool Ycon, Ju-Young Cho, Jin-Sub Shin, B. Woo, J. Bae, Yuchul Hwang, Young‐Chang Joo
As the design rule for memory devices shrinks, the reliability issue of electromigration (EM) is emerged due 10 the increase of high current density, therefore, the reliability for memory devices can be limited by EM failure of metal lines (Al. Cu. W). But EM reliability with respect to structures of interconnects is still underestimated even though EM behavior for each material has been reported for decades. Therefore, we investigated the kinetics of EM in various metal line and via in memory devices under direct current (DC) stressing because failure of metal interconnects depends not only on metal materials but also on structures of interconnects. Under EM tests, mean time failure of Al with W via was shorter than that of Cu with W via. These results came from abrupt failure behavior due to void nucleation and growth at Al with W via and gradual failure behavior at Cu with W via due to void generation and growth as well as conduction in Ta/TaN. Additionally. Cu with W via showed different behavior compared to Cu with Cu via. It can be explained that the joule heating between W and Cu interface caused lateral void expansion and resistance increases rapidly. And it was observed that W line had the longest lifetime of EM failure but the high resistivity of W should be considered for memory chip design. As the results, we conclude that Al has the weakest reliable property for EM reliability among Al. W and Cu metal lines and W via can affect the degradation of EM reliability. These results mean that reliability of Al and W interconnects beyond nanometer-scale should be improved to guarantee reliability in memory chip. This study could provide the guideline for the optimal materials for interconnects in highly-reliable memory chips.
{"title":"Electromigration-limited reliability of advanced metallization for memory devices","authors":"Kyung-Tae Jang, Yong-Jin Park, Min-Woo Jeong, Seung-Min Lim, Han-Wool Ycon, Ju-Young Cho, Jin-Sub Shin, B. Woo, J. Bae, Yuchul Hwang, Young‐Chang Joo","doi":"10.1109/IITC-MAM.2015.7325650","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325650","url":null,"abstract":"As the design rule for memory devices shrinks, the reliability issue of electromigration (EM) is emerged due 10 the increase of high current density, therefore, the reliability for memory devices can be limited by EM failure of metal lines (Al. Cu. W). But EM reliability with respect to structures of interconnects is still underestimated even though EM behavior for each material has been reported for decades. Therefore, we investigated the kinetics of EM in various metal line and via in memory devices under direct current (DC) stressing because failure of metal interconnects depends not only on metal materials but also on structures of interconnects. Under EM tests, mean time failure of Al with W via was shorter than that of Cu with W via. These results came from abrupt failure behavior due to void nucleation and growth at Al with W via and gradual failure behavior at Cu with W via due to void generation and growth as well as conduction in Ta/TaN. Additionally. Cu with W via showed different behavior compared to Cu with Cu via. It can be explained that the joule heating between W and Cu interface caused lateral void expansion and resistance increases rapidly. And it was observed that W line had the longest lifetime of EM failure but the high resistivity of W should be considered for memory chip design. As the results, we conclude that Al has the weakest reliable property for EM reliability among Al. W and Cu metal lines and W via can affect the degradation of EM reliability. These results mean that reliability of Al and W interconnects beyond nanometer-scale should be improved to guarantee reliability in memory chip. This study could provide the guideline for the optimal materials for interconnects in highly-reliable memory chips.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"11 1","pages":"155-158"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76665187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325637
Xu Wang, L. Cao, X. Qu
In this work, an alkaline electrolyte containing copper sulfate and ethanediamine (En) as ligand was used for direct Cu electrodeposition on novel alloy barrier CoxMoy films and comparison was made between alkaline bath and H2SO4-CuSO4 acidic bath. In alkaline bath, the nucleation density of Cu on Co1Mo3 is much higher than that in acidic bath. It is found that the Cu island density increases and the surface roughness decreases with the higher content of Co in CoxMoy films. Results show that adhesion between Cu and Co is better than that between Cu and Mo, which affects initial nucleation behavior and surface roughness of the deposited Cu films. Uniform and conformal copper was successfully electroplated on 5 nm Co1Mo3 layers covered patterned wafers in alkaline bath without additives.
{"title":"Direct copper electrodeposition on novel CoMo diffusion barrier","authors":"Xu Wang, L. Cao, X. Qu","doi":"10.1109/IITC-MAM.2015.7325637","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325637","url":null,"abstract":"In this work, an alkaline electrolyte containing copper sulfate and ethanediamine (En) as ligand was used for direct Cu electrodeposition on novel alloy barrier CoxMoy films and comparison was made between alkaline bath and H2SO4-CuSO4 acidic bath. In alkaline bath, the nucleation density of Cu on Co1Mo3 is much higher than that in acidic bath. It is found that the Cu island density increases and the surface roughness decreases with the higher content of Co in CoxMoy films. Results show that adhesion between Cu and Co is better than that between Cu and Mo, which affects initial nucleation behavior and surface roughness of the deposited Cu films. Uniform and conformal copper was successfully electroplated on 5 nm Co1Mo3 layers covered patterned wafers in alkaline bath without additives.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"24 1","pages":"127-130"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83296991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325616
Haitao Zhang, J. Duchaine, F. Torregrosa, Linjie Liu, B. Hollander, U. Breuer, S. Mantl, Qing-Tai Zhao
We present in this paper high quality thin NiSi contacts on Si for the 16nm node using pre-silicidation CF4 Plasma Immersion Ion Implantation (PIII) The thermal stability, the layer uniformity and the interface roughness of thin NiSi layers are improved by CF4 PIII, which is assumed to be caused by segregation of C, F atoms at the grain boundaries and at the NiSi/Si interface. The Schottky barrier height of NiSi/p-Si is also lowered by CF4 plasma, thus a lower contact resistance on p+ doped Si is expected.
{"title":"Improved NiSi contacts on Si by CF4 plasma immersion ion implantation for 14nm node MOSFETs","authors":"Haitao Zhang, J. Duchaine, F. Torregrosa, Linjie Liu, B. Hollander, U. Breuer, S. Mantl, Qing-Tai Zhao","doi":"10.1109/IITC-MAM.2015.7325616","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325616","url":null,"abstract":"We present in this paper high quality thin NiSi contacts on Si for the 16nm node using pre-silicidation CF4 Plasma Immersion Ion Implantation (PIII) The thermal stability, the layer uniformity and the interface roughness of thin NiSi layers are improved by CF4 PIII, which is assumed to be caused by segregation of C, F atoms at the grain boundaries and at the NiSi/Si interface. The Schottky barrier height of NiSi/p-Si is also lowered by CF4 plasma, thus a lower contact resistance on p+ doped Si is expected.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"17 1","pages":"187-190"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81106259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325622
S. Spiga
Summary form only given. Resistive switching (RS) phenomena in oxides have received a large interest for ultra-scaled and high-density non-volatile memories, and many prototypes have been proposed at industrial level. Recently, RS have been also exploited for new type of applications, such as reconfigurable logic and synaptic electronics. In the latter field, the interest is towards RS devices which can be used to fabricate artificial synapses, able to emulate the synaptic functions of biological synapses, and to be integrated with standard CMOS circuits to build neuromorphic systems. These RS devices, also named memristive systems, are of particular interest due to their simple two terminal structure, low power operation, high-scalability, low thermal budget fabrication and, depending on material system, easy integration into CMOS based platform. This talk will first introduce the current state of the art and materials systems investigated for non-volatile memories as well as synaptic devices for neuromorphic circuits, highlighting the materials/device differences versus target application. Then, the talk will present our recent advancements on HfO2 and Al-doped-HfO2 based RS devices. The oxide layers (binary and doped oxides) are deposited by atomic layer deposition and the resistive switching properties are analysed from micro- to nanoscale. The fabrication of high-density and nanoscale HfOx-based memristive devices is achieved by block-copolymer lithography. Furthermore, in view of application of these devices as synaptic elements, the long term plasticity, as potentiation and depression typical of biological synapses, are characterized by various pulsed operation schemes. Special emphasis is given to programming algorithms based on a train of identical pulses. It will be shown that a careful choice of the pulse amplitude/pulse width combination is fundamental to achieve an analogue modulation of the device.
{"title":"Resistive switching in oxides for nonvolatile memories and neuromorphic computing","authors":"S. Spiga","doi":"10.1109/IITC-MAM.2015.7325622","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325622","url":null,"abstract":"Summary form only given. Resistive switching (RS) phenomena in oxides have received a large interest for ultra-scaled and high-density non-volatile memories, and many prototypes have been proposed at industrial level. Recently, RS have been also exploited for new type of applications, such as reconfigurable logic and synaptic electronics. In the latter field, the interest is towards RS devices which can be used to fabricate artificial synapses, able to emulate the synaptic functions of biological synapses, and to be integrated with standard CMOS circuits to build neuromorphic systems. These RS devices, also named memristive systems, are of particular interest due to their simple two terminal structure, low power operation, high-scalability, low thermal budget fabrication and, depending on material system, easy integration into CMOS based platform. This talk will first introduce the current state of the art and materials systems investigated for non-volatile memories as well as synaptic devices for neuromorphic circuits, highlighting the materials/device differences versus target application. Then, the talk will present our recent advancements on HfO2 and Al-doped-HfO2 based RS devices. The oxide layers (binary and doped oxides) are deposited by atomic layer deposition and the resistive switching properties are analysed from micro- to nanoscale. The fabrication of high-density and nanoscale HfOx-based memristive devices is achieved by block-copolymer lithography. Furthermore, in view of application of these devices as synaptic elements, the long term plasticity, as potentiation and depression typical of biological synapses, are characterized by various pulsed operation schemes. Special emphasis is given to programming algorithms based on a train of identical pulses. It will be shown that a careful choice of the pulse amplitude/pulse width combination is fundamental to achieve an analogue modulation of the device.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"15 1","pages":"213-214"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80755868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325646
Kevin L. Lin, J. Bielefeld, J. Chawla, C. Carver, R. Chebiam, J. Clarke, Jacob Faber, M. Harmes, T. Indukuri, C. Jezewski, R. Kasim, M. Kobrinsky, N. Kabir, B. Krist, Narendra V. Lakamraju, H. Lang, E. Mays, A. Myers, J. Plombon, K. Singh, J. Torres, H. Yoo
Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.
{"title":"Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films","authors":"Kevin L. Lin, J. Bielefeld, J. Chawla, C. Carver, R. Chebiam, J. Clarke, Jacob Faber, M. Harmes, T. Indukuri, C. Jezewski, R. Kasim, M. Kobrinsky, N. Kabir, B. Krist, Narendra V. Lakamraju, H. Lang, E. Mays, A. Myers, J. Plombon, K. Singh, J. Torres, H. Yoo","doi":"10.1109/IITC-MAM.2015.7325646","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325646","url":null,"abstract":"Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"80 1","pages":"139-142"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78630032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325585
K. Croes, C. Wu, D. Kocaay, J. Bommels, Z. Tokei
We review our current understanding of the degradation mechanisms in scaled interconnects. Concerns on the applicability of today's reliability evaluation methods are expressed. Regarding electromigration (EM), both scaling line dimensions and using mechanically weaker intermetal dielectrics (IMDs) have a negative impact on its performance, where remedial measures to overcome this downward trend are discussed. With aggressively scaled barriers, we also show that EM test methodology adaptation towards constant voltage testing might be needed. Regarding dielectric reliability, we quantify the reliability degradation induced by both k-value and spacing reduction. Also, we review the current understanding on lifetime models used for predicting high field data to lower fields. Both for copper and dielectric reliability, we highlight that the development of ways to account for process variability during lifetime prediction will become key in the future.
{"title":"Reliability mechanisms and lifetime extrapolation methods for scaled interconnect technologies","authors":"K. Croes, C. Wu, D. Kocaay, J. Bommels, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325585","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325585","url":null,"abstract":"We review our current understanding of the degradation mechanisms in scaled interconnects. Concerns on the applicability of today's reliability evaluation methods are expressed. Regarding electromigration (EM), both scaling line dimensions and using mechanically weaker intermetal dielectrics (IMDs) have a negative impact on its performance, where remedial measures to overcome this downward trend are discussed. With aggressively scaled barriers, we also show that EM test methodology adaptation towards constant voltage testing might be needed. Regarding dielectric reliability, we quantify the reliability degradation induced by both k-value and spacing reduction. Also, we review the current understanding on lifetime models used for predicting high field data to lower fields. Both for copper and dielectric reliability, we highlight that the development of ways to account for process variability during lifetime prediction will become key in the future.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"40 1","pages":"295-298"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74135410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325643
P. Rodriguez, L. Toselli, E. Ghegin, F. Nemouchi, N. Rochat, E. Martinez
In this work we introduce the use of physical plasmas (e.g. Ar- and He-based plasmas) in order to study the in situ cleaning (prior to metal deposition) of InGaAs layers dedicated to the realisation of self-aligned contacts. For the characterisation of cleaning efficiency, we performed surface analyses like X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy in attenuated total reflection mode. The first results described in this work are encouraging. We have found efficient processes for removing totally or partially III-V native oxides.
{"title":"In situ cleaning/passivation of surfaces for contact technology on III-V materials","authors":"P. Rodriguez, L. Toselli, E. Ghegin, F. Nemouchi, N. Rochat, E. Martinez","doi":"10.1109/IITC-MAM.2015.7325643","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325643","url":null,"abstract":"In this work we introduce the use of physical plasmas (e.g. Ar- and He-based plasmas) in order to study the in situ cleaning (prior to metal deposition) of InGaAs layers dedicated to the realisation of self-aligned contacts. For the characterisation of cleaning efficiency, we performed surface analyses like X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy in attenuated total reflection mode. The first results described in this work are encouraging. We have found efficient processes for removing totally or partially III-V native oxides.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"152 1","pages":"107-110"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77490935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325595
J. Roberts, A. Kaushik, J. Clarke
Resistivity data are presented for lines from 22 nm to 108 nm wide measured at room temperature and at 4.6 K. We also present numerical simulation data for 2-10 nm features. The experimental data are fit with standard Mayadas-Shatzkes and Fuchs-Sondheimer models which indicate that electron scattering from surfaces and from grains are the main contributors to resistivity for small features. The simulation data show that surface scattering dominates resistivity at smaller dimensions. This suggests that improvements in resistivity should focus on minimizing the impact of surfaces and grains, which has implications for interconnect material selection.
{"title":"Resistivity of sub-30 nm copper lines","authors":"J. Roberts, A. Kaushik, J. Clarke","doi":"10.1109/IITC-MAM.2015.7325595","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325595","url":null,"abstract":"Resistivity data are presented for lines from 22 nm to 108 nm wide measured at room temperature and at 4.6 K. We also present numerical simulation data for 2-10 nm features. The experimental data are fit with standard Mayadas-Shatzkes and Fuchs-Sondheimer models which indicate that electron scattering from surfaces and from grains are the main contributors to resistivity for small features. The simulation data show that surface scattering dominates resistivity at smaller dimensions. This suggests that improvements in resistivity should focus on minimizing the impact of surfaces and grains, which has implications for interconnect material selection.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"3 3","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91499163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325640
M. Franz, R. Ecke, C. Kaufmann, J. Kriz, S. Schulz
In this work, we present the recent work on self-forming barriers. Focus on investigation laid on the barrier formation and its stability against copper diffusion. The investigated alloys were Cu(Mn), Cu(Ti) and Cu(Zr) respectively. It can be shown that these alloys are capable to form an enrichment layer on the SiO2 interface. Here the substrate influences mainly the thickness of the generated barrier. Electrical measurements show the barrier stability against copper diffusion. Mn and Ti are promising elements as barrier materials.
{"title":"Investigation of barrier formation and stability of self-forming barriers with CuMn, CuTi and CuZr alloys","authors":"M. Franz, R. Ecke, C. Kaufmann, J. Kriz, S. Schulz","doi":"10.1109/IITC-MAM.2015.7325640","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325640","url":null,"abstract":"In this work, we present the recent work on self-forming barriers. Focus on investigation laid on the barrier formation and its stability against copper diffusion. The investigated alloys were Cu(Mn), Cu(Ti) and Cu(Zr) respectively. It can be shown that these alloys are capable to form an enrichment layer on the SiO2 interface. Here the substrate influences mainly the thickness of the generated barrier. Electrical measurements show the barrier stability against copper diffusion. Mn and Ti are promising elements as barrier materials.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"64 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91266585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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