Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325597
E. T. Ryan, D. Priyadarshini, Stephen M. Gates, Hosadurga Shobha, James Hsueh-Chung Chen, Kumar Virwani, Anita Madan, E. Adams, Elbert E. Huang, E. Liniger, D. Collins, M. Stolfi, Kang Sub Yim, Alexandros T. Demos, Alfred Grill
Increasing circuit density in multilevel back-end-of line (BEOL) interconnects is necessary to improve integrated circuit performance and area scaling. Ultra low-k (ULK) dielectrics are used to minimize capacitance for lower power consumption and better capacitance-resistance (RC) performance. However, these materials pose integration and reliability challenges, which have limited our ability to scale the dielectric constant lower.1 Minimizing porosity, maximizing carbon content, and altering how carbon is bonded in porous SiCOH films reduces plasma-induced damage (PID) to the ULK and improves TDDB reliability, but these improvement must be balanced by maintaining other film properties such as elastic modulus. This paper describes one technique to achieve this combination of high carbon content and low porosity to allow k scaling while meeting integration and reliability requirements.
{"title":"Optimizing ULK film properties to enable BEOL integration with TDDB reliability","authors":"E. T. Ryan, D. Priyadarshini, Stephen M. Gates, Hosadurga Shobha, James Hsueh-Chung Chen, Kumar Virwani, Anita Madan, E. Adams, Elbert E. Huang, E. Liniger, D. Collins, M. Stolfi, Kang Sub Yim, Alexandros T. Demos, Alfred Grill","doi":"10.1109/IITC-MAM.2015.7325597","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325597","url":null,"abstract":"Increasing circuit density in multilevel back-end-of line (BEOL) interconnects is necessary to improve integrated circuit performance and area scaling. Ultra low-k (ULK) dielectrics are used to minimize capacitance for lower power consumption and better capacitance-resistance (RC) performance. However, these materials pose integration and reliability challenges, which have limited our ability to scale the dielectric constant lower.1 Minimizing porosity, maximizing carbon content, and altering how carbon is bonded in porous SiCOH films reduces plasma-induced damage (PID) to the ULK and improves TDDB reliability, but these improvement must be balanced by maintaining other film properties such as elastic modulus. This paper describes one technique to achieve this combination of high carbon content and low porosity to allow k scaling while meeting integration and reliability requirements.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"80 8 1","pages":"349-352"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87990865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325609
O. Kolosov, F. Dinelli, A. Robson, A. Krier, M. Hayne, V. Fal’ko, M. Henini
Multilayer structures of active semiconductor devices (1), novel memories (2) and semiconductor interconnects are becoming increasingly three-dimensional (3D) with simultaneous decrease of dimensions down to the few nanometres length scale (3). Ability to test and explore these 3D nanostructures with nanoscale resolution is vital for the optimization of their operation and improving manufacturing processes of new semiconductor devices. While electron and scanning probe microscopes (SPMs) can provide necessary lateral resolution, their ability to probe underneath the immediate surface is severely limited. Cross-sectioning of the structures via focused ion beam (FIB) to expose the subsurface areas often introduces multiple artefacts that mask the true features of the hidden structures, negating benefits of such approach. In addition, the few tens of micrometre dimension of FIB cut, make it unusable for the SPM investigation.
{"title":"Nanometre scale 3D nanomechanical imaging of semiconductor structures from few nm to sub-micrometre depths","authors":"O. Kolosov, F. Dinelli, A. Robson, A. Krier, M. Hayne, V. Fal’ko, M. Henini","doi":"10.1109/IITC-MAM.2015.7325609","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325609","url":null,"abstract":"Multilayer structures of active semiconductor devices (1), novel memories (2) and semiconductor interconnects are becoming increasingly three-dimensional (3D) with simultaneous decrease of dimensions down to the few nanometres length scale (3). Ability to test and explore these 3D nanostructures with nanoscale resolution is vital for the optimization of their operation and improving manufacturing processes of new semiconductor devices. While electron and scanning probe microscopes (SPMs) can provide necessary lateral resolution, their ability to probe underneath the immediate surface is severely limited. Cross-sectioning of the structures via focused ion beam (FIB) to expose the subsurface areas often introduces multiple artefacts that mask the true features of the hidden structures, negating benefits of such approach. In addition, the few tens of micrometre dimension of FIB cut, make it unusable for the SPM investigation.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"17 1","pages":"43-46"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91185826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325630
H. Zahedmanesh, K. Vanstreels, Mario Gonzalez
In this study, indentation and fracture of compliant low-dielectric constant (low-k) films on silicon substrates was investigated by means of finite element (FE) modelling. Cohesive zone damage models were employed for fracture simulation and damage constitutive parameters and plastic yield stress of organosilicate glass 2.4 (OSG 2.4) low-k films coated on silicon substrates were obtained by correlating the force-displacement and crack growth response with experiments. The model lends itself to characterization of brittle films where the value of the Young's modulus, the maximum cohesive strength, the critical cohesive energy release rate and plastic yield stress of the low-k films can be extracted only by conducting cube corner indentation experiments and employing the finite element model.
{"title":"Numerical simulation of nano-indentation induced fracture of low-k dielectric thin films using the cube corner indenter","authors":"H. Zahedmanesh, K. Vanstreels, Mario Gonzalez","doi":"10.1109/IITC-MAM.2015.7325630","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325630","url":null,"abstract":"In this study, indentation and fracture of compliant low-dielectric constant (low-k) films on silicon substrates was investigated by means of finite element (FE) modelling. Cohesive zone damage models were employed for fracture simulation and damage constitutive parameters and plastic yield stress of organosilicate glass 2.4 (OSG 2.4) low-k films coated on silicon substrates were obtained by correlating the force-displacement and crack growth response with experiments. The model lends itself to characterization of brittle films where the value of the Young's modulus, the maximum cohesive strength, the critical cohesive energy release rate and plastic yield stress of the low-k films can be extracted only by conducting cube corner indentation experiments and employing the finite element model.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"74 1","pages":"75-78"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90651887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325657
P. Gondcharton, B. Imbert, L. Benaissa, M. Verdier
In recent years, a great interest has emerged in the development of new wafer-scale assembly processes. Beside the mechanical strength required, some applications need a vertical conductivity leading to implement metal thin films as bonding layers. For its interesting properties in terms of resistivity and reliability, copper has been already used in metal-metal direct bonding configuration. Initially developed on amorphous silicon dioxide layers, the polycristallinity character of metal films has a direct impact on the direct bonding mechanisms. In this paper, we will study the effect of grain size on direct bonding of polycrystalline copper thin films. More specifically at temperature below 150°C, a fine-grain copper microstructure demonstrates a fast sealing strengthening. For higher temperature application, a larger grain size enables limiting the copper-barrier interface damage and preserves a strong mechanical link between substrates.
{"title":"Copper-copper direct bonding: Impact of grain size","authors":"P. Gondcharton, B. Imbert, L. Benaissa, M. Verdier","doi":"10.1109/IITC-MAM.2015.7325657","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325657","url":null,"abstract":"In recent years, a great interest has emerged in the development of new wafer-scale assembly processes. Beside the mechanical strength required, some applications need a vertical conductivity leading to implement metal thin films as bonding layers. For its interesting properties in terms of resistivity and reliability, copper has been already used in metal-metal direct bonding configuration. Initially developed on amorphous silicon dioxide layers, the polycristallinity character of metal films has a direct impact on the direct bonding mechanisms. In this paper, we will study the effect of grain size on direct bonding of polycrystalline copper thin films. More specifically at temperature below 150°C, a fine-grain copper microstructure demonstrates a fast sealing strengthening. For higher temperature application, a larger grain size enables limiting the copper-barrier interface damage and preserves a strong mechanical link between substrates.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"84 4","pages":"229-232"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91463230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325634
J. C. Lin, H. Liu, W. Lin, C. -. Lin, T. Hung, K. R. Li, J. F. Lin, J. Y. Wang, C. C. Liu, J. Y. Wu
The control of gate height uniformity, especially within-die gate height uniformity, and metal gate surface properties of 14nm technology node replacement metal gate (RMG) chemical mechanical polishing is important for 14nm high-k metal gate (HKMG) process. Good within-die uniformity would benefit for the following Tungsten etching back process(WEB) to have a uniform within-die etching depth, and proper post CMP Tungsten gate surface properties would generate a thinner Tungsten oxide surface to reduce WEB process loading. This study demonstrated the possibility of Tungsten gate CMP(WGCMP) to obtain good within-die gate height uniformity by selection of slurry and proper Tungsten gate surface by post buffing step CMP treatment. Due to high hardness of Tungsten, hardness of polishing pad and abrasive of slurry selection should be not a gap for micro scratch improvement, what the performance focus would put on within-die uniformity and post CMP Tungsten surface properties. In this study, the first result showed the control of erosion was important for within-die gate height uniformity. The criteria of slurry selection for WGCMP were higher Tungsten removal rate and lower oxide removal rate which especially resulted in lower pattern density area of erosion. And the second result showed Chemical-A polish time of post-Tungsten buffing CMP would dominate the Tungsten surface properties and influence WEB behavior.
{"title":"Process development of replacement metal gate Tungsten chemical mechanical polishing on 14nm technology node and beyond","authors":"J. C. Lin, H. Liu, W. Lin, C. -. Lin, T. Hung, K. R. Li, J. F. Lin, J. Y. Wang, C. C. Liu, J. Y. Wu","doi":"10.1109/IITC-MAM.2015.7325634","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325634","url":null,"abstract":"The control of gate height uniformity, especially within-die gate height uniformity, and metal gate surface properties of 14nm technology node replacement metal gate (RMG) chemical mechanical polishing is important for 14nm high-k metal gate (HKMG) process. Good within-die uniformity would benefit for the following Tungsten etching back process(WEB) to have a uniform within-die etching depth, and proper post CMP Tungsten gate surface properties would generate a thinner Tungsten oxide surface to reduce WEB process loading. This study demonstrated the possibility of Tungsten gate CMP(WGCMP) to obtain good within-die gate height uniformity by selection of slurry and proper Tungsten gate surface by post buffing step CMP treatment. Due to high hardness of Tungsten, hardness of polishing pad and abrasive of slurry selection should be not a gap for micro scratch improvement, what the performance focus would put on within-die uniformity and post CMP Tungsten surface properties. In this study, the first result showed the control of erosion was important for within-die gate height uniformity. The criteria of slurry selection for WGCMP were higher Tungsten removal rate and lower oxide removal rate which especially resulted in lower pattern density area of erosion. And the second result showed Chemical-A polish time of post-Tungsten buffing CMP would dominate the Tungsten surface properties and influence WEB behavior.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"233 1","pages":"115-118"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76975770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325625
C. Guedj, G. Auvert, E. Martinez
Electrical characterization during FIB milling of an elementary Pt/NiO/Pt resistive memory cell is used to localize the conducting channels and to estimate the size and shape of the nanofilament. A good agreement is found with cross sectional high resolution Transmission Electron Microscopy images. This methodology is a potential tool to obtain in-operando electrical tomography of conducting paths with subnanometric spatial resolution.
{"title":"In-situ electrical characterization of Pt/NiO/Pt resistive memory elementary cells during FIB milling: A step towards electrical tomography of nanofilaments","authors":"C. Guedj, G. Auvert, E. Martinez","doi":"10.1109/IITC-MAM.2015.7325625","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325625","url":null,"abstract":"Electrical characterization during FIB milling of an elementary Pt/NiO/Pt resistive memory cell is used to localize the conducting channels and to estimate the size and shape of the nanofilament. A good agreement is found with cross sectional high resolution Transmission Electron Microscopy images. This methodology is a potential tool to obtain in-operando electrical tomography of conducting paths with subnanometric spatial resolution.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"38 1","pages":"57-58"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77339940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325658
David Gross, Sabine Haag, M. Reinold, M. Schneider-Ramelow, K. Lang
Thick electroplated Cu bond pads have lately been demonstrated to enable heavy Cu wire-bonding but the Cu oxides necessitate an additional cleaning step after the die-attach. To avoid such cleaning, the use of a thin Al layer is tested for its passivating ability on Cu bond pads and its suitability for the bonding process. Results show a significant improvement of the oxidation resistance and bonding performance.
{"title":"Aluminum-capped copper bond pads for ultrasonic heavy copper wire-bonding on power devices","authors":"David Gross, Sabine Haag, M. Reinold, M. Schneider-Ramelow, K. Lang","doi":"10.1109/IITC-MAM.2015.7325658","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325658","url":null,"abstract":"Thick electroplated Cu bond pads have lately been demonstrated to enable heavy Cu wire-bonding but the Cu oxides necessitate an additional cleaning step after the die-attach. To avoid such cleaning, the use of a thin Al layer is tested for its passivating ability on Cu bond pads and its suitability for the bonding process. Results show a significant improvement of the oxidation resistance and bonding performance.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"10 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74278348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325604
P. Brun, F. Bailly, M. Guillermet, E. Aparico, N. Possémé
With the constant scaling down in dimension, the metal hard mask strategy, integration of choice for porous SiOCH film integration, presents new issues that cannot not been neglected for the 14nm and beyond. These issues and associated solutions are presented from plasma etch point of view for the 14nm node.
{"title":"Plasma etch challenges at 14nm and beyond technology nodes in the BEOL","authors":"P. Brun, F. Bailly, M. Guillermet, E. Aparico, N. Possémé","doi":"10.1109/IITC-MAM.2015.7325604","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325604","url":null,"abstract":"With the constant scaling down in dimension, the metal hard mask strategy, integration of choice for porous SiOCH film integration, presents new issues that cannot not been neglected for the 14nm and beyond. These issues and associated solutions are presented from plasma etch point of view for the 14nm node.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"22 1","pages":"21-24"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74298472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325620
Jengyi Yu, S. Gopinath, P. Nalla, Matthew Thorum, L. Schloss, D. M. Anjos, Prashant Meshram, G. Harm, Joe Richardson, T. Mountsier
Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.
{"title":"Advanced integrated metallization enables 3D-IC TSV scaling","authors":"Jengyi Yu, S. Gopinath, P. Nalla, Matthew Thorum, L. Schloss, D. M. Anjos, Prashant Meshram, G. Harm, Joe Richardson, T. Mountsier","doi":"10.1109/IITC-MAM.2015.7325620","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325620","url":null,"abstract":"Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"29 1","pages":"205-208"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85377307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325617
V. Pore, E. Tois, R. Matero, S. Haukka, M. Tuominen, J. Woodruff, Brennan Milligan, F. Tang, M. Givens
In this work, we demonstrate the preparation of nickel monosilicide (NiSi) layers on silicon using a conformal NiO ALD process and thin sacrificial Ge interlayers. The interlayers protect the underlying Si from oxidizing during the NiO growth, while allowing for Ni diffusion during a silicidation anneal. The NiSi layers prepared have low amounts of impurities and near bulk resistivities, therefore making the processes promising candidates for applications in advanced semiconductor devices where high quality NiSi layers are needed, such as source-drain contacts. Good step coverage provided by ALD enables their use for example in non-planar transistors such as FinFETs and other multi-gate transistors with complex topographies.
{"title":"Nickel silicide for source-drain contacts from ALD NiO films","authors":"V. Pore, E. Tois, R. Matero, S. Haukka, M. Tuominen, J. Woodruff, Brennan Milligan, F. Tang, M. Givens","doi":"10.1109/IITC-MAM.2015.7325617","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325617","url":null,"abstract":"In this work, we demonstrate the preparation of nickel monosilicide (NiSi) layers on silicon using a conformal NiO ALD process and thin sacrificial Ge interlayers. The interlayers protect the underlying Si from oxidizing during the NiO growth, while allowing for Ni diffusion during a silicidation anneal. The NiSi layers prepared have low amounts of impurities and near bulk resistivities, therefore making the processes promising candidates for applications in advanced semiconductor devices where high quality NiSi layers are needed, such as source-drain contacts. Good step coverage provided by ALD enables their use for example in non-planar transistors such as FinFETs and other multi-gate transistors with complex topographies.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"41 1","pages":"191-194"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77669716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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