This panel will bring together a set of experts working in a collaborative project to address at both experimental measurement and simulations all levels of the process leading to system failures induced by soft errors. Several aspects will be discussed, e.g. interaction between energetic particles and the matter, detailed analysis of transient pulse generation and propagation, dependence of the circuit topology and system architecture.
{"title":"From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?","authors":"L. Anghel, M. Nicolaidis, N. Buard","doi":"10.1109/IOLTS.2006.40","DOIUrl":"https://doi.org/10.1109/IOLTS.2006.40","url":null,"abstract":"This panel will bring together a set of experts working in a collaborative project to address at both experimental measurement and simulations all levels of the process leading to system failures induced by soft errors. Several aspects will be discussed, e.g. interaction between energetic particles and the matter, detailed analysis of transient pulse generation and propagation, dependence of the circuit topology and system architecture.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"2 1","pages":"85"},"PeriodicalIF":0.0,"publicationDate":"2006-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88855510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The proliferation of new terminals represents a major growth factor for the semiconductor industry. Multimedia mobile phones, game consoles, digital TV sets combine previously separated products and functions into a single box, often built around a single chip. This convergence of devices that integrate storage, security, multimedia, mobility, connectivity and computing on the same piece of silicon represents an enormous growth opportunity for the global semiconductor industry and is focused on consumer architectures. In this scenario, the reliability of semiconductor devices represents a key issue, where the driving factors are the increasing miniaturization of process lithography, the mechanical shocks to which handheld terminals are subject, the usage of new materials due also to environmental regulations, the shorter time-to-market and the demand for low-cost components. New issues come from the advent nanometric devices: defect and fault tolerance -at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. Semiconductor manufacturers are responding to these challenges by introducing a variety of technical innovations, including new manufacture testing methodologies, virtual testing, prediction models, CAD targeting defect, fault-tolerant nanoelectronic architectures.
{"title":"The Challenge of Reliability in Future Complex Systems","authors":"A. Cuomo","doi":"10.1109/IOLTS.2006.59","DOIUrl":"https://doi.org/10.1109/IOLTS.2006.59","url":null,"abstract":"Summary form only given. The proliferation of new terminals represents a major growth factor for the semiconductor industry. Multimedia mobile phones, game consoles, digital TV sets combine previously separated products and functions into a single box, often built around a single chip. This convergence of devices that integrate storage, security, multimedia, mobility, connectivity and computing on the same piece of silicon represents an enormous growth opportunity for the global semiconductor industry and is focused on consumer architectures. In this scenario, the reliability of semiconductor devices represents a key issue, where the driving factors are the increasing miniaturization of process lithography, the mechanical shocks to which handheld terminals are subject, the usage of new materials due also to environmental regulations, the shorter time-to-market and the demand for low-cost components. New issues come from the advent nanometric devices: defect and fault tolerance -at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. Semiconductor manufacturers are responding to these challenges by introducing a variety of technical innovations, including new manufacture testing methodologies, virtual testing, prediction models, CAD targeting defect, fault-tolerant nanoelectronic architectures.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"18 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2006-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82265108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also been some work at the process level (e.g., SOI), but recently, there is also some research work on circuit level (e.g., cell hardening, BISER), but there has not been a wide spread adoption yet. Can logic SER be solved at the circuit level? Should they be? We have a team of experts from system, architecture and circuit area to debate this topic.
{"title":"Should Logic SER be Solved at the Circuit Level?","authors":"T. M. Mak, S. Mitra","doi":"10.1109/IOLTS.2006.56","DOIUrl":"https://doi.org/10.1109/IOLTS.2006.56","url":null,"abstract":"SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also been some work at the process level (e.g., SOI), but recently, there is also some research work on circuit level (e.g., cell hardening, BISER), but there has not been a wide spread adoption yet. Can logic SER be solved at the circuit level? Should they be? We have a team of experts from system, architecture and circuit area to debate this topic.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"41 1","pages":"199"},"PeriodicalIF":0.0,"publicationDate":"2006-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77839781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Leveugle, Y. Zorian, L. Breveglieri, A. Nieuwland, K. Rothbart, Jean-Pierre Seifert
On-line testing approaches can today be useful when designing circuits with severe security constraints. The reasons are summarized in the introduction to the special session on secure implementations (in these proceedings). The presentations in this special session aimed at introducing the specific concerns related to security as well as some approaches used to protect the circuits and to validate their robustness for certification. This panel aims at discussing in more details how on-line testing techniques can help in improving security and how the achieved level of security can be evaluated at different stages in the design flow. Various aspects are covered by the participants, including: counter-measures for fault attacks in hardware cryptographic primitives, design for test versus design for security, use of fault injection tools in evaluating the robustness against attacks and validation of security at the system level.
{"title":"On-Line Testing for Secure Implementations: Design and Validation","authors":"R. Leveugle, Y. Zorian, L. Breveglieri, A. Nieuwland, K. Rothbart, Jean-Pierre Seifert","doi":"10.1109/IOLTS.2005.52","DOIUrl":"https://doi.org/10.1109/IOLTS.2005.52","url":null,"abstract":"On-line testing approaches can today be useful when designing circuits with severe security constraints. The reasons are summarized in the introduction to the special session on secure implementations (in these proceedings). The presentations in this special session aimed at introducing the specific concerns related to security as well as some approaches used to protect the circuits and to validate their robustness for certification. This panel aims at discussing in more details how on-line testing techniques can help in improving security and how the achieved level of security can be evaluated at different stages in the design flow. Various aspects are covered by the participants, including: counter-measures for fault attacks in hardware cryptographic primitives, design for test versus design for security, use of fault injection tools in evaluating the robustness against attacks and validation of security at the system level.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"41 1","pages":"211"},"PeriodicalIF":0.0,"publicationDate":"2005-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77356679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-07-12DOI: 10.1109/IOLTS.2004.10010
V. Agarwal
Modeling and simulation of time domain faults in digital systems p. 5 Sizing CMOS circuits for increased transient error tolerance p. 11 Low-area on-chip circuit for jitter measurement in a phase-locked loop p. 17 Necessary and sufficient conditions for the existence of totally self-checking circuits p. 25 Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits p. 31 A hierarchical self test scheme for SoCs p. 37 Single-output embedded checkers for systematic unordered codes p. 45 A new dynamic circuit design technique for high performance TSC checker implementations p. 52 New high speed CMOS self-checking voter p. 58 Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks p. 67 Low cost on-line testing of RF circuits p. 73 Hybrid soft error detection by means of infrastructure IP cores p. 79 A comparative study of the design of synchronous and asynchronous self-checking RISC processors p. 89 Testing of hard faults in simultaneous multihreaded processors p. 95 Fault detection enhancement in cache memories using a high performance placement algorithm p. 101 Transient fault emulation of hardened circuits in FPGA platforms p. 109 On the evaluation of SEU sensitiveness in SRAM-based FPGAs p. 115 Asynchronous circuits sensitivity to fault injection p. 121 Designing a high speed decoder for cyclic codes p. 129 Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems p. 135 A signed digit adder with error correction and graceful degradation capabilities p. 141 A novel fault tolerant cache to improve yield in nanometer technologies p. 149 Scrubbing away transients and jiggling around the permanent : long survival of FPGA systems through evolutionary self-repair p. 155 Hardware reconfiguration scheme for high availability systems p. 161 Operating system function reuse to achieve low-cost fault tolerance p. 167 A new code with reduced EMI and partial EC possibilities p. 175 A Matlab based on-chip signal generation and analysis environment for mixed signal circuits p. 176 Automated logic SER analysis and on-line SER reduction p. 177 On the design of long-life reliable systems for ground-based applications p. 178 On-line monitoring capabilities of oscillation test techniques : results demonstration in an OTA p. 179 An intrinsically robust technique for fault tolerance under multiple upsets p. 180 Survey of the algorithms in the column-matching BIST method p. 181 A technique to reduce power and test application time in BIST p. 182
{"title":"A Pragmatic Approach to On-Line Testing","authors":"V. Agarwal","doi":"10.1109/IOLTS.2004.10010","DOIUrl":"https://doi.org/10.1109/IOLTS.2004.10010","url":null,"abstract":"Modeling and simulation of time domain faults in digital systems p. 5 Sizing CMOS circuits for increased transient error tolerance p. 11 Low-area on-chip circuit for jitter measurement in a phase-locked loop p. 17 Necessary and sufficient conditions for the existence of totally self-checking circuits p. 25 Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits p. 31 A hierarchical self test scheme for SoCs p. 37 Single-output embedded checkers for systematic unordered codes p. 45 A new dynamic circuit design technique for high performance TSC checker implementations p. 52 New high speed CMOS self-checking voter p. 58 Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks p. 67 Low cost on-line testing of RF circuits p. 73 Hybrid soft error detection by means of infrastructure IP cores p. 79 A comparative study of the design of synchronous and asynchronous self-checking RISC processors p. 89 Testing of hard faults in simultaneous multihreaded processors p. 95 Fault detection enhancement in cache memories using a high performance placement algorithm p. 101 Transient fault emulation of hardened circuits in FPGA platforms p. 109 On the evaluation of SEU sensitiveness in SRAM-based FPGAs p. 115 Asynchronous circuits sensitivity to fault injection p. 121 Designing a high speed decoder for cyclic codes p. 129 Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems p. 135 A signed digit adder with error correction and graceful degradation capabilities p. 141 A novel fault tolerant cache to improve yield in nanometer technologies p. 149 Scrubbing away transients and jiggling around the permanent : long survival of FPGA systems through evolutionary self-repair p. 155 Hardware reconfiguration scheme for high availability systems p. 161 Operating system function reuse to achieve low-cost fault tolerance p. 167 A new code with reduced EMI and partial EC possibilities p. 175 A Matlab based on-chip signal generation and analysis environment for mixed signal circuits p. 176 Automated logic SER analysis and on-line SER reduction p. 177 On the design of long-life reliable systems for ground-based applications p. 178 On-line monitoring capabilities of oscillation test techniques : results demonstration in an OTA p. 179 An intrinsically robust technique for fault tolerance under multiple upsets p. 180 Survey of the algorithms in the column-matching BIST method p. 181 A technique to reduce power and test application time in BIST p. 182","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"18 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2004-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88332031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern cars exhibit a variety of new functionalitiesconcerning engine management, safety, vehicle dynamicscontrol as well as comfort and convenience. Safetyfeatures like airbags, antilock braking systems (ABS),anti-skid systems, belt tensioners or the electronic stabilityprogram (ESP) are standard fittings of present daycar models and in some cases even stipulated by legislation.These safety systems have led to an increasedavoidance of accidents by actively affecting vehicle dynamicsand to a mitigation of the consequences of accidentson the driver and passengers by innovative restraintsystems.As a rule these systems are mechatronic systems.Mechatronic systems [Mechatronic Systems] today derive their functionalityby an interlocked interaction of mechanics, electronicsand information technology. Their deployment in thesafety-relevant environment requires fault tolerance.Fault tolerant mechatronics is based on redundancy,which must be supervised and tested permanently.Reliability of sensor and actuator technology is essentialfor future motor vehicle systems. Operability andreliability are to be achieved by suitable on-board andon-line test methods. Exemplarily this is shown forfuture X-by-Wire applications.
{"title":"Fault Tolerant Mechatronics","authors":"E. Dilger, R. Karrelmeyer, B. Straube","doi":"10.1109/IOLTS.2004.23","DOIUrl":"https://doi.org/10.1109/IOLTS.2004.23","url":null,"abstract":"Modern cars exhibit a variety of new functionalitiesconcerning engine management, safety, vehicle dynamicscontrol as well as comfort and convenience. Safetyfeatures like airbags, antilock braking systems (ABS),anti-skid systems, belt tensioners or the electronic stabilityprogram (ESP) are standard fittings of present daycar models and in some cases even stipulated by legislation.These safety systems have led to an increasedavoidance of accidents by actively affecting vehicle dynamicsand to a mitigation of the consequences of accidentson the driver and passengers by innovative restraintsystems.As a rule these systems are mechatronic systems.Mechatronic systems [Mechatronic Systems] today derive their functionalityby an interlocked interaction of mechanics, electronicsand information technology. Their deployment in thesafety-relevant environment requires fault tolerance.Fault tolerant mechatronics is based on redundancy,which must be supervised and tested permanently.Reliability of sensor and actuator technology is essentialfor future motor vehicle systems. Operability andreliability are to be achieved by suitable on-board andon-line test methods. Exemplarily this is shown forfuture X-by-Wire applications.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"6 1","pages":"214-218"},"PeriodicalIF":0.0,"publicationDate":"2004-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76007060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Hély, M. Flottes, F. Bancel, B. Rouzeyre, Nicolas Bérard, M. Renovell
Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.
{"title":"Scan Design and Secure Chip","authors":"D. Hély, M. Flottes, F. Bancel, B. Rouzeyre, Nicolas Bérard, M. Renovell","doi":"10.1109/IOLTS.2004.40","DOIUrl":"https://doi.org/10.1109/IOLTS.2004.40","url":null,"abstract":"Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"66 1","pages":"219-226"},"PeriodicalIF":0.0,"publicationDate":"2004-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89150569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-07-12DOI: 10.1109/IOLTS.2004.10006
J. M. Santos
{"title":"On the Design of Long-Life Reliable Systems for Ground-Based Applications","authors":"J. M. Santos","doi":"10.1109/IOLTS.2004.10006","DOIUrl":"https://doi.org/10.1109/IOLTS.2004.10006","url":null,"abstract":"","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"55 5","pages":"178"},"PeriodicalIF":0.0,"publicationDate":"2004-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72587964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Operating System Function Reuse to Achieve Low-Cost Fault Tolerance","authors":"M. Portolan, R. Leveugle","doi":"10.1109/IOLTS.2004.35","DOIUrl":"https://doi.org/10.1109/IOLTS.2004.35","url":null,"abstract":"","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"9 1","pages":"167-174"},"PeriodicalIF":0.0,"publicationDate":"2004-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83156004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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