Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604708
Panagiotis Sismanoglou, D. Nikolos
Single event transient (SET) pulses are a significant cause of soft errors in a circuit. To cope with SET pulses, we propose a new storage cell that is able to operate either as a hard-edge or soft-edge flip-flop depending on the appearance or not of a transition in a time window. The efficiency of the proposed design with respect to the reduction of soft-errors coming from SET pulses was shown with extensive simulations.
{"title":"Conditional soft-edge flip-flop for SET mitigation","authors":"Panagiotis Sismanoglou, D. Nikolos","doi":"10.1109/IOLTS.2016.7604708","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604708","url":null,"abstract":"Single event transient (SET) pulses are a significant cause of soft errors in a circuit. To cope with SET pulses, we propose a new storage cell that is able to operate either as a hard-edge or soft-edge flip-flop depending on the appearance or not of a transition in a time window. The efficiency of the proposed design with respect to the reduction of soft-errors coming from SET pulses was shown with extensive simulations.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"29 1","pages":"227-232"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74934806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604681
Shoba Gopalakrishnan, Virendra Singh
Relentless scaling in CMOS fabrication technology has made contemporary integrated circuits continue to evolve and grow in functionality with high clock frequencies and exponentially increasing transistor counts. However, it also makes them more susceptible to transient faults effectively decreasing their reliability. Therefore, ensuring correct and reliable operation of these microprocessors at low cost has become a challenging task. This paper proposes a light weight error detection method called REMO which aims to incorporate simple fault tolerance mechanisms as part of the basic architecture. It dynamically verifies the execution results of the instructions by exploiting spatial and temporal redundancy and detects soft errors. REMO shows that with minimal area, power and performance overhead, and a very low detection latency, a very high degree of fault coverage can be achieved. Our simulation results shows an increase in area is about 0.4%, power overhead near to 9% and a negligible performance penalty during fault free run.
{"title":"REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture","authors":"Shoba Gopalakrishnan, Virendra Singh","doi":"10.1109/IOLTS.2016.7604681","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604681","url":null,"abstract":"Relentless scaling in CMOS fabrication technology has made contemporary integrated circuits continue to evolve and grow in functionality with high clock frequencies and exponentially increasing transistor counts. However, it also makes them more susceptible to transient faults effectively decreasing their reliability. Therefore, ensuring correct and reliable operation of these microprocessors at low cost has become a challenging task. This paper proposes a light weight error detection method called REMO which aims to incorporate simple fault tolerance mechanisms as part of the basic architecture. It dynamically verifies the execution results of the instructions by exploiting spatial and temporal redundancy and detects soft errors. REMO shows that with minimal area, power and performance overhead, and a very low detection latency, a very high degree of fault coverage can be achieved. Our simulation results shows an increase in area is about 0.4%, power overhead near to 9% and a negligible performance penalty during fault free run.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"357 1","pages":"109-114"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80158973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604660
B. Bhowmik, J. Deka, S. Biswas
This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.
{"title":"An on-line test solution for addressing interconnect shorts in on-chip networks","authors":"B. Bhowmik, J. Deka, S. Biswas","doi":"10.1109/IOLTS.2016.7604660","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604660","url":null,"abstract":"This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"30 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77333999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604664
Romain Champon, V. Beroulle, Athanasios Papadimitriou, D. Hély, Gilles Genévrier, Frédéric Cézilly
Confronted to more and more demanding standards in terms of safety and reliability, aerospace companies are investigating new methodologies to evaluate the robustness of their FPGA designs against energetic particles. In this paper, this evaluation is realized early in the design flow to avoid costly design re-spins. It permits to have a first evaluation of the RTL design robustness and of the design protections efficiency. To deal with the low accuracy of classical RTL fault models, we use a new RTL fault model taking into account the local effects of particles. We compare the fault model characteristics of different high level fault models (RTL) and low level fault models (layout) on a RTL design dedicated to the plane power supply control. These evaluations show that the new RTL fault model have best characteristics than the classical register fault model.
{"title":"Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices","authors":"Romain Champon, V. Beroulle, Athanasios Papadimitriou, D. Hély, Gilles Genévrier, Frédéric Cézilly","doi":"10.1109/IOLTS.2016.7604664","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604664","url":null,"abstract":"Confronted to more and more demanding standards in terms of safety and reliability, aerospace companies are investigating new methodologies to evaluate the robustness of their FPGA designs against energetic particles. In this paper, this evaluation is realized early in the design flow to avoid costly design re-spins. It permits to have a first evaluation of the RTL design robustness and of the design protections efficiency. To deal with the low accuracy of classical RTL fault models, we use a new RTL fault model taking into account the local effects of particles. We compare the fault model characteristics of different high level fault models (RTL) and low level fault models (layout) on a RTL design dedicated to the plane power supply control. These evaluations show that the new RTL fault model have best characteristics than the classical register fault model.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"31 1","pages":"23-24"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77460938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604685
M. Nicolaidis, M. Dimopoulos
Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliability.
{"title":"Advanced double-sampling architectures","authors":"M. Nicolaidis, M. Dimopoulos","doi":"10.1109/IOLTS.2016.7604685","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604685","url":null,"abstract":"Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliability.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"12 1","pages":"130-132"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76830555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604693
A. Savino, S. Carlo, Alessandro Vallero, G. Politano, D. Gizopoulos, A. Evans
This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.
{"title":"RIIF-2: Toward the next generation reliability information interchange format","authors":"A. Savino, S. Carlo, Alessandro Vallero, G. Politano, D. Gizopoulos, A. Evans","doi":"10.1109/IOLTS.2016.7604693","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604693","url":null,"abstract":"This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"16 1","pages":"173-178"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90105185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604675
G. Papadimitriou, Athanasios Chatzidimitriou, D. Gizopoulos, Ronny Morad
Post-silicon validation complements traditional simulation-based pre-silicon verification and offers very high throughput since validation programs run at the speed of the actual hardware. Detection of bugs in the address translation subsystem of a microprocessor is much less straightforward than other hardware blocks because the address translation is an implicit process, which does not have an easily observable output to architecture or program visible locations. Validation of the correctness of the address translation mechanisms (ATMs) of microprocessors is both very important and challenging problem. In this paper, we present an ISA-independent methodology for the post-silicon validation of the ATMs in modern microprocessors. We first capture the effects of design bugs in address translation, by presenting actual bugs scenarios reported for commercial chips. We also describe an effective method for the detection of bugs in all address translation hardware blocks. The validation programs of the method are self-checking, i.e. do not require a bug-free model to compare with. Our experimental evaluation on Gem5 simulator shows the effectiveness of the methodology in detecting bugs in the address translation hardware of an x86-64 microprocessor model.
{"title":"ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors","authors":"G. Papadimitriou, Athanasios Chatzidimitriou, D. Gizopoulos, Ronny Morad","doi":"10.1109/IOLTS.2016.7604675","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604675","url":null,"abstract":"Post-silicon validation complements traditional simulation-based pre-silicon verification and offers very high throughput since validation programs run at the speed of the actual hardware. Detection of bugs in the address translation subsystem of a microprocessor is much less straightforward than other hardware blocks because the address translation is an implicit process, which does not have an easily observable output to architecture or program visible locations. Validation of the correctness of the address translation mechanisms (ATMs) of microprocessors is both very important and challenging problem. In this paper, we present an ISA-independent methodology for the post-silicon validation of the ATMs in modern microprocessors. We first capture the effects of design bugs in address translation, by presenting actual bugs scenarios reported for commercial chips. We also describe an effective method for the detection of bugs in all address translation hardware blocks. The validation programs of the method are self-checking, i.e. do not require a bug-free model to compare with. Our experimental evaluation on Gem5 simulator shows the effectiveness of the methodology in detecting bugs in the address translation hardware of an x86-64 microprocessor model.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"63 1","pages":"72-77"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80678635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604668
Hailong Jiao, Yongmin Qiu, V. Kursun
Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.
{"title":"Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode","authors":"Hailong Jiao, Yongmin Qiu, V. Kursun","doi":"10.1109/IOLTS.2016.7604668","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604668","url":null,"abstract":"Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"86 1","pages":"39-42"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78150583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604694
E. Vatajelu, G. D. Natale, P. Prinetto
A hardware True Random Number Generator (TRNG) yields random numbers from a physical process. Traditionally, such devices are based on statistically random signals such as thermal noise or other quantum phenomena. In this paper we propose an innovative TRNG design using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. We exploit the stochastic nature of the MTJ device switching, and perform on-the-fly temperature/current variation compensation. We show that the proposed solution keeps up with environmental changes and generates random sequences with high probability.
{"title":"STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation","authors":"E. Vatajelu, G. D. Natale, P. Prinetto","doi":"10.1109/IOLTS.2016.7604694","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604694","url":null,"abstract":"A hardware True Random Number Generator (TRNG) yields random numbers from a physical process. Traditionally, such devices are based on statistically random signals such as thermal noise or other quantum phenomena. In this paper we propose an innovative TRNG design using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. We exploit the stochastic nature of the MTJ device switching, and perform on-the-fly temperature/current variation compensation. We show that the proposed solution keeps up with environmental changes and generates random sequences with high probability.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"25 1","pages":"179-184"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74452634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604680
Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski
Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.
{"title":"NBTI aging evaluation of PUF-based differential architectures","authors":"Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski","doi":"10.1109/IOLTS.2016.7604680","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604680","url":null,"abstract":"Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"45 1","pages":"103-108"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73403300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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