Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604686
H. Wunderlich, Claus Braun, A. Schöll
Approximate computing in hardware and software promises significantly improved computational performance combined with very low power and energy consumption. This goal is achieved by both relaxing strict requirements on accuracy and precision, and by allowing a deviating behavior from exact Boolean specifications to a certain extent. Today, approximate computing is often limited to applications with a certain degree of inherent error tolerance, where perfect computational results are not always required. However, in order to fully utilize its benefits, the scope of applications has to be significantly extended to other compute-intensive domains including science and engineering. To meet the often rather strict quality and reliability requirements for computational results in these domains, the use of appropriate characterization and fault tolerance measures is highly required. In this paper, we evaluate some of the available techniques and how they may extend the scope of application for approximate computing.
{"title":"Pushing the limits: How fault tolerance extends the scope of approximate computing","authors":"H. Wunderlich, Claus Braun, A. Schöll","doi":"10.1109/IOLTS.2016.7604686","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604686","url":null,"abstract":"Approximate computing in hardware and software promises significantly improved computational performance combined with very low power and energy consumption. This goal is achieved by both relaxing strict requirements on accuracy and precision, and by allowing a deviating behavior from exact Boolean specifications to a certain extent. Today, approximate computing is often limited to applications with a certain degree of inherent error tolerance, where perfect computational results are not always required. However, in order to fully utilize its benefits, the scope of applications has to be significantly extended to other compute-intensive domains including science and engineering. To meet the often rather strict quality and reliability requirements for computational results in these domains, the use of appropriate characterization and fault tolerance measures is highly required. In this paper, we evaluate some of the available techniques and how they may extend the scope of application for approximate computing.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"40 1","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79384021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604696
Arash Nejat, D. Hély, V. Beroulle
Hardware Trojan (HT), Integrated Circuit (IC) piracy, and overproduction are three important threats which may happen in untrusted foundries. Design changes against HTs, so-called Design-For-Hardware-Trust (DFHT), are used in order to facilitate the HT detection. In addition, logic masking has been proposed against IC piracy and overproduction. In this work, we propose a DFHT method reusing the circuitry dedicated to logic masking in order to improve the HT detection based on the path delay analysis.
{"title":"Reusing logic masking to facilitate path-delay-based hardware Trojan detection","authors":"Arash Nejat, D. Hély, V. Beroulle","doi":"10.1109/IOLTS.2016.7604696","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604696","url":null,"abstract":"Hardware Trojan (HT), Integrated Circuit (IC) piracy, and overproduction are three important threats which may happen in untrusted foundries. Design changes against HTs, so-called Design-For-Hardware-Trust (DFHT), are used in order to facilitate the HT detection. In addition, logic masking has been proposed against IC piracy and overproduction. In this work, we propose a DFHT method reusing the circuitry dedicated to logic masking in order to improve the HT detection based on the path delay analysis.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"55 1","pages":"191-192"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85804712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604701
A. Serrano-Cases, José Isaza-González, S. Cuenca-Asensi, A. Martínez-Álvarez
This paper proposes a method for tuning compilations to improve the size, execution time and reliability of the final application altogether. Our approach implements a genetic strategy with a multi-objective evolution that takes advantage of the NSGA-II algorithm for selecting the best compilations. Experiments show that reliability can be improved by efficiently exploring the compiler optimization options. As a consequence, our method enhances the application fault coverage from 3% to 6% and gets increments of MWTF from 15% to 45%.
{"title":"On the influence of compiler optimizations in the fault tolerance of embedded systems","authors":"A. Serrano-Cases, José Isaza-González, S. Cuenca-Asensi, A. Martínez-Álvarez","doi":"10.1109/IOLTS.2016.7604701","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604701","url":null,"abstract":"This paper proposes a method for tuning compilations to improve the size, execution time and reliability of the final application altogether. Our approach implements a genetic strategy with a multi-objective evolution that takes advantage of the NSGA-II algorithm for selecting the best compilations. Experiments show that reliability can be improved by efficiently exploring the compiler optimization options. As a consequence, our method enhances the application fault coverage from 3% to 6% and gets increments of MWTF from 15% to 45%.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"9 1 1","pages":"207-208"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88517680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604706
Masaru Oya, M. Yanagisawa, N. Togawa
This paper proposes a redesign technique which designs from untrusted netlists to trusted netlists. Our approach consists of two phases, detection phase and invalidation phase. The detection phase picks up suspicious hardware Trojans (HTs) by pattern matching. The invalidation phase modifies the suspicious HTs in order not to activate them. In the invalidation phase, three invalidation techniques are selected by analyzing location of suspicious malicious nets. Applying appropriately the invalidation technique to the nets can correctly invalidate HTs. In our results, the proposed technique can successfully invalidate HTs on several Trust-HUB benchmarks without HT activations. The results clearly demonstrate that our redesign technique is very effective to remove HT risks.
{"title":"Redesign for untrusted gate-level netlists","authors":"Masaru Oya, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2016.7604706","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604706","url":null,"abstract":"This paper proposes a redesign technique which designs from untrusted netlists to trusted netlists. Our approach consists of two phases, detection phase and invalidation phase. The detection phase picks up suspicious hardware Trojans (HTs) by pattern matching. The invalidation phase modifies the suspicious HTs in order not to activate them. In the invalidation phase, three invalidation techniques are selected by analyzing location of suspicious malicious nets. Applying appropriately the invalidation technique to the nets can correctly invalidate HTs. In our results, the proposed technique can successfully invalidate HTs on several Trust-HUB benchmarks without HT activations. The results clearly demonstrate that our redesign technique is very effective to remove HT risks.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"72 1","pages":"219-220"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90399282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604676
Yumin Zhou, O. Bringmann, W. Rosenstiel
Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed flexibly by software in the in-silicon phase. A stand-alone hardware block, called assertion processing unit (APU), is used for implementing the compiled instructions. This unit handles the storage of the checker code, the execution of the checking, and the feedback of checked results in the system run-time environment. We have successfully evaluated this approach on an FPGA-based prototyping board, showing measurable benefits of this approach.
{"title":"Flexible in-silicon checking of run-time programmable assertions","authors":"Yumin Zhou, O. Bringmann, W. Rosenstiel","doi":"10.1109/IOLTS.2016.7604676","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604676","url":null,"abstract":"Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed flexibly by software in the in-silicon phase. A stand-alone hardware block, called assertion processing unit (APU), is used for implementing the compiled instructions. This unit handles the storage of the checker code, the execution of the checking, and the feedback of checked results in the system run-time environment. We have successfully evaluated this approach on an FPGA-based prototyping board, showing measurable benefits of this approach.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"52 1","pages":"78-83"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81380354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604704
Stefano Esposito, M. Violante, M. Sozzi, Marco Terrone, M. Traversone
In this paper a novel technique is proposed for online detection of timing interference in multicore architectures. The technique is aimed at mixed-criticality workloads. This paper describes a method to use hardware performance counters to detect such misbehaviors. Experimental data is gathered, showing the viability of this method. The method can be used as safety-net in several scheduling approaches.
{"title":"Online time interference detection in mixed-criticality applications on multicore architectures using performance counters","authors":"Stefano Esposito, M. Violante, M. Sozzi, Marco Terrone, M. Traversone","doi":"10.1109/IOLTS.2016.7604704","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604704","url":null,"abstract":"In this paper a novel technique is proposed for online detection of timing interference in multicore architectures. The technique is aimed at mixed-criticality workloads. This paper describes a method to use hardware performance counters to detect such misbehaviors. Experimental data is gathered, showing the viability of this method. The method can be used as safety-net in several scheduling approaches.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"31 1","pages":"213-214"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78681233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604672
K. Chibani, M. Portolan, R. Leveugle
Evaluating the robustness of circuits with respect to soft errors has become of utmost importance in many application areas. This evaluation must in most cases be refined taking into account the application characteristics in order to avoid too pessimistic results. The main approach used today at design time is based on fault injection campaigns. Emulation can be used to speed up the evaluations, but requires noticeable effort to implement the circuit prototype. This paper presents an approach based on an automated analysis of register lifetime, requiring only one functional simulation of the target application. The approach has been demonstrated on significant circuits. The results show that the proposed approach can be more efficient than emulation in terms of experimental time, without requiring any specific hardware and achieving a good accuracy. The global intrinsic robustness is evaluated and the most critical registers or execution cycles can also be identified with good confidence.
{"title":"Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations","authors":"K. Chibani, M. Portolan, R. Leveugle","doi":"10.1109/IOLTS.2016.7604672","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604672","url":null,"abstract":"Evaluating the robustness of circuits with respect to soft errors has become of utmost importance in many application areas. This evaluation must in most cases be refined taking into account the application characteristics in order to avoid too pessimistic results. The main approach used today at design time is based on fault injection campaigns. Emulation can be used to speed up the evaluations, but requires noticeable effort to implement the circuit prototype. This paper presents an approach based on an automated analysis of register lifetime, requiring only one functional simulation of the target application. The approach has been demonstrated on significant circuits. The results show that the proposed approach can be more efficient than emulation in terms of experimental time, without requiring any specific hardware and achieving a good accuracy. The global intrinsic robustness is evaluated and the most critical registers or execution cycles can also be identified with good confidence.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"186 1","pages":"54-59"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77013511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604671
B. Ouattara, O. Héron, C. Sandionigi
Integrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits.
{"title":"Fine-grain analysis of the parameters involved in aging of digital circuits","authors":"B. Ouattara, O. Héron, C. Sandionigi","doi":"10.1109/IOLTS.2016.7604671","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604671","url":null,"abstract":"Integrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"54 1","pages":"51-53"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76651369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604683
Konstantin Tscherkaschin, Theodor Hillebrand, Maike Taddiken, S. Paul, D. Peters-Drolshagen
Inverters are one of the most basic logic blocks and exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillators and time to digital converters, both temperature dependencies have to be considered. This work introduces a circuit design for a robust and resilient inverter and an analysis on its temperature-dependent aging characteristic. The implemented inverter is driven by a common-source amplifier to achieve high robustness against temperature variation and aging effects. Based on this, circuit designs for a ring oscillator and an inverter-based delay line for a time to digital converter has been implemented. The results show that the deviation of the delay for an inverter can be minimized from 13.2% for conventional inverter design to less than 2% for the temperature-and aging-resistant design over a wide temperature range from -40° C to 150° C and a stress time of ten years.
{"title":"Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS process","authors":"Konstantin Tscherkaschin, Theodor Hillebrand, Maike Taddiken, S. Paul, D. Peters-Drolshagen","doi":"10.1109/IOLTS.2016.7604683","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604683","url":null,"abstract":"Inverters are one of the most basic logic blocks and exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillators and time to digital converters, both temperature dependencies have to be considered. This work introduces a circuit design for a robust and resilient inverter and an analysis on its temperature-dependent aging characteristic. The implemented inverter is driven by a common-source amplifier to achieve high robustness against temperature variation and aging effects. Based on this, circuit designs for a ring oscillator and an inverter-based delay line for a time to digital converter has been implemented. The results show that the deviation of the delay for an inverter can be minimized from 13.2% for conventional inverter design to less than 2% for the temperature-and aging-resistant design over a wide temperature range from -40° C to 150° C and a stress time of ten years.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"77 1","pages":"121-125"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83394834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604702
Theodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, S. Paul, D. Peters-Drolshagen
Scaled down analog integrated circuits are prone to degradation. This necessitates an online degradation monitoring and sophisticated analysis of degradation for this circuitry. Voltage reference sources such as beta-multiplier are commonly used circuits to set the operating points for downstream circuitry. Thus, the degradation of these sources are crucial for the overall degradation. In this paper the simulation results of the degradation analysis of a beta-multiplier circuit including the startup circuit, implemented in a 65nm CMOS technology, considering the temperature, are shown. A new approach for online degradation monitoring is introduced, utilizing startup circuit components to ensure minimal area and power overhead.
{"title":"Online monitoring of NBTI and HCD in beta-multiplier circuits","authors":"Theodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, S. Paul, D. Peters-Drolshagen","doi":"10.1109/IOLTS.2016.7604702","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604702","url":null,"abstract":"Scaled down analog integrated circuits are prone to degradation. This necessitates an online degradation monitoring and sophisticated analysis of degradation for this circuitry. Voltage reference sources such as beta-multiplier are commonly used circuits to set the operating points for downstream circuitry. Thus, the degradation of these sources are crucial for the overall degradation. In this paper the simulation results of the degradation analysis of a beta-multiplier circuit including the startup circuit, implemented in a 65nm CMOS technology, considering the temperature, are shown. A new approach for online degradation monitoring is introduced, utilizing startup circuit components to ensure minimal area and power overhead.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"12 1","pages":"209-210"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86309371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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