Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604669
A. Bravaix, M. Saliva, F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, E. Kussener, E. Pauly, V. Huard
We use dedicated test structures for high performance low power (LP) CMOS nodes designed with 28nm FDSOI and 28nm LP devices. These allow to distinguish AC high frequency dependence as a function of high temperature (125°C) experiments for Bias Temperature Instability (BTI) and Hot-Carrier Damage (HCD) (1) for inverter chains (buffers) and logic gates in order to obtain AC-DC ratios (2) in standard logic gate paths for timing degradation with activity as a variable. This shows that NBTI remains the worst-case of damage at high temperature with a frequency independence due to the limited effect of relaxation with activity lowering (ton/toff) while HCD still represents a significant damage contribution at lower temperature due to the frequency and pulse shape dependences during transients. An accurate quantitative analysis is checked in a data path example with ELDO simulations that distinguishes each contribution.
{"title":"Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodes","authors":"A. Bravaix, M. Saliva, F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, E. Kussener, E. Pauly, V. Huard","doi":"10.1109/IOLTS.2016.7604669","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604669","url":null,"abstract":"We use dedicated test structures for high performance low power (LP) CMOS nodes designed with 28nm FDSOI and 28nm LP devices. These allow to distinguish AC high frequency dependence as a function of high temperature (125°C) experiments for Bias Temperature Instability (BTI) and Hot-Carrier Damage (HCD) (1) for inverter chains (buffers) and logic gates in order to obtain AC-DC ratios (2) in standard logic gate paths for timing degradation with activity as a variable. This shows that NBTI remains the worst-case of damage at high temperature with a frequency independence due to the limited effect of relaxation with activity lowering (ton/toff) while HCD still represents a significant damage contribution at lower temperature due to the frequency and pulse shape dependences during transients. An accurate quantitative analysis is checked in a data path example with ELDO simulations that distinguishes each contribution.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"17 1","pages":"43-46"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90923275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604709
Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh
Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan RAS) cell.
{"title":"A high performance scan flip-flop design for serial and mixed mode scan test","authors":"Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh","doi":"10.1109/IOLTS.2016.7604709","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604709","url":null,"abstract":"Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan RAS) cell.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"34 1","pages":"233-238"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91008221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604678
B. Alorda, C. Carmona, G. Torrens, S. Bota
SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line Voltage Margin estimator to observe SRAM performance degradation. The proposed on-line estimator approach does not require memory array modification and it can be shared with all embedded memories in a SoC reducing its area overhead.
{"title":"On-line write margin estimator to monitor performance degradation in SRAM cores","authors":"B. Alorda, C. Carmona, G. Torrens, S. Bota","doi":"10.1109/IOLTS.2016.7604678","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604678","url":null,"abstract":"SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line Voltage Margin estimator to observe SRAM performance degradation. The proposed on-line estimator approach does not require memory array modification and it can be shared with all embedded memories in a SoC reducing its area overhead.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"62 1","pages":"90-95"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89080326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604659
Zeinab Mahdavi, Z. Shirmohammadi, S. Miremadi
The severity of timing delay in the communication channels of Network on Chip (NoC) depends on the transition patterns appearing on the wires. An analytical model can estimate the timing delay in NoC channels in the presence of crosstalk faults. However, recently proposed analytical model does not have enough accuracy and is based on 3-wire delay model. In this paper, an Accurate Crosstalk Model (ACM) based on 5-wire delay model is proposed to estimate the delay of communication channels in the presence of crosstalk faults. ACM is more accurate due to considering more wires in the delay model and also considering the overlaps between locations of transition patterns.
片上网络(Network on Chip, NoC)通信信道中时序延迟的严重程度取决于导线上出现的转换模式。一个解析模型可以估计存在串扰故障时NoC信道的时延。然而，目前提出的分析模型基于3线延迟模型，精度不够。本文提出了一种基于5线延迟模型的精确串扰模型(ACM)，用于估计存在串扰故障时通信信道的延迟。由于在延迟模型中考虑了更多的导线，并且考虑了过渡模式位置之间的重叠，ACM更加准确。
{"title":"ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips","authors":"Zeinab Mahdavi, Z. Shirmohammadi, S. Miremadi","doi":"10.1109/IOLTS.2016.7604659","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604659","url":null,"abstract":"The severity of timing delay in the communication channels of Network on Chip (NoC) depends on the transition patterns appearing on the wires. An analytical model can estimate the timing delay in NoC channels in the presence of crosstalk faults. However, recently proposed analytical model does not have enough accuracy and is based on 3-wire delay model. In this paper, an Accurate Crosstalk Model (ACM) based on 5-wire delay model is proposed to estimate the delay of communication channels in the presence of crosstalk faults. ACM is more accurate due to considering more wires in the delay model and also considering the overlaps between locations of transition patterns.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"116 1","pages":"7-8"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86089029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604662
Jiajing Cai, Basel Halak, Daniele Rossi
This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) aging on the delay of level shifters. The latter are indispensable blocks in energy efficient systems with multiple supply voltages. Our results show that conventional level-up shifters exhibit significantly more aging-induced delay degradation compared to standard logic cells. Our experiments performed in a predictive 32nm technology indicate those designs can suffer from more than 200% increase in their delay after 5 years due to BTI aging compared to an average of 20% delay rise in the case of standard CMOS logic. Our investigations show that the reason behind this phenomenon is the differential signaling structure present in the majority of conventional level up shifters, combined with the use of low supply voltages.
{"title":"Analysis of BTI aging of level shifters","authors":"Jiajing Cai, Basel Halak, Daniele Rossi","doi":"10.1109/IOLTS.2016.7604662","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604662","url":null,"abstract":"This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) aging on the delay of level shifters. The latter are indispensable blocks in energy efficient systems with multiple supply voltages. Our results show that conventional level-up shifters exhibit significantly more aging-induced delay degradation compared to standard logic cells. Our experiments performed in a predictive 32nm technology indicate those designs can suffer from more than 200% increase in their delay after 5 years due to BTI aging compared to an average of 20% delay rise in the case of standard CMOS logic. Our investigations show that the reason behind this phenomenon is the differential signaling structure present in the majority of conventional level up shifters, combined with the use of low supply voltages.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"6 1","pages":"17-18"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81702624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604658
A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva
This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.
{"title":"A fault-tolerant sequential circuit design for SAFs and PDFs soft errors","authors":"A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva","doi":"10.1109/IOLTS.2016.7604658","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604658","url":null,"abstract":"This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"35 1","pages":"5-6"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86660193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604711
Lake Bu, M. Karpovsky
In recent years parallel computing has been widely employed for both science research and commercial applications. For parallel systems such as many-core or computer clusters, it is inevitable to have one or more computing node failures due to random errors or injected attacks. Usually a diagnosis mechanism is able to locate several defective nodes through a number of tests and the analysis of those test signatures (syndromes). Although this covers the cases caused by random errors, sophisticated attacks are still able to manipulate the outputs of each node, so that they will be masked and pass the diagnosis. Therefore in this paper we propose a hybrid self-diagnosis mechanism. We adopt a new type of analysis with the linear syndromes, which are able to locate up to a certain number of defective nodes caused by random errors. In addition to this, we introduce a new type of robust analysis of the non-linear syndromes, which is capable of detecting the attacks undetectable by the linear syndromes at a probability close to one. Moreover, since this hybrid self-diagnosis mechanism is on the data level which makes little distinction among different operating systems and programming languages, it can be migrated onto any other platforms conveniently.
{"title":"A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems","authors":"Lake Bu, M. Karpovsky","doi":"10.1109/IOLTS.2016.7604711","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604711","url":null,"abstract":"In recent years parallel computing has been widely employed for both science research and commercial applications. For parallel systems such as many-core or computer clusters, it is inevitable to have one or more computing node failures due to random errors or injected attacks. Usually a diagnosis mechanism is able to locate several defective nodes through a number of tests and the analysis of those test signatures (syndromes). Although this covers the cases caused by random errors, sophisticated attacks are still able to manipulate the outputs of each node, so that they will be masked and pass the diagnosis. Therefore in this paper we propose a hybrid self-diagnosis mechanism. We adopt a new type of analysis with the linear syndromes, which are able to locate up to a certain number of defective nodes caused by random errors. In addition to this, we introduce a new type of robust analysis of the non-linear syndromes, which is capable of detecting the attacks undetectable by the linear syndromes at a probability close to one. Moreover, since this hybrid self-diagnosis mechanism is on the data level which makes little distinction among different operating systems and programming languages, it can be migrated onto any other platforms conveniently.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"28 1","pages":"245-250"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88158578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604712
Mohammad Saleh Samimi, Ehsan Aerabi, Z. Kazemi, M. Fazeli, A. Patooghy
IC design and manufacturing chains show steadily growing complexity which provides different third party roles in between. Reprobate parties can take the opportunity to steal a client's IP or insert their malicious circuits-Hardware Trojans-in the original client's design and trigger them in case of need. Trojans are usually inserted in the most hidden internal signals with the lowest activity which increase their chance for not being activated and revealed by clients or end-users. In this paper we propose a method to reduce the number of signals with low activity and hence the chance of inserting hidden trojans. This method is based on an enhanced Logic Encryption approach and uses a 128-bit key. Encryption can also secure the design against IP piracy. Simulation results show that the proposed method can eliminate 83.17% of low activity signals in the circuit.
{"title":"Hardware enlightening: No where to hide your Hardware Trojans!","authors":"Mohammad Saleh Samimi, Ehsan Aerabi, Z. Kazemi, M. Fazeli, A. Patooghy","doi":"10.1109/IOLTS.2016.7604712","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604712","url":null,"abstract":"IC design and manufacturing chains show steadily growing complexity which provides different third party roles in between. Reprobate parties can take the opportunity to steal a client's IP or insert their malicious circuits-Hardware Trojans-in the original client's design and trigger them in case of need. Trojans are usually inserted in the most hidden internal signals with the lowest activity which increase their chance for not being activated and revealed by clients or end-users. In this paper we propose a method to reduce the number of signals with low activity and hence the chance of inserting hidden trojans. This method is based on an enhanced Logic Encryption approach and uses a 128-bit key. Encryption can also secure the design against IP piracy. Simulation results show that the proposed method can eliminate 83.17% of low activity signals in the circuit.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"86 1","pages":"251-256"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81129992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604699
Patryk Skoncej, F. Mühlbauer, Felix Kubicek, Lukas Schröder, Mario Schölzel
In this paper we evaluate the feasibility of software-based repair for program (NOR flash) memories in tiny embedded systems. Often, in such systems, it is very typical that not the full memory area is used by the application. This paper proposes a software-based self-repair for program memories which utilizes this inherently available redundancy. Our techniques combine application adaptation in respect to faulty memory words and protection of the adapted application with error-correcting code. With our approach we address post-production memory faults and retention- and radiation-related memory faults which can occur in the field. The evaluation of our repair mechanisms was based on the results from post-production and after burn-in tests performed on real 32 and 64 KByte flash memory devices.
{"title":"Feasibility of software-based repair for program memories","authors":"Patryk Skoncej, F. Mühlbauer, Felix Kubicek, Lukas Schröder, Mario Schölzel","doi":"10.1109/IOLTS.2016.7604699","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604699","url":null,"abstract":"In this paper we evaluate the feasibility of software-based repair for program (NOR flash) memories in tiny embedded systems. Often, in such systems, it is very typical that not the full memory area is used by the application. This paper proposes a software-based self-repair for program memories which utilizes this inherently available redundancy. Our techniques combine application adaptation in respect to faulty memory words and protection of the adapted application with error-correcting code. With our approach we address post-production memory faults and retention- and radiation-related memory faults which can occur in the field. The evaluation of our repair mechanisms was based on the results from post-production and after burn-in tests performed on real 32 and 64 KByte flash memory devices.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"65 1","pages":"199-202"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85678833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604705
Chandra K. H. Suresh, Bodhisatwa Mazumdar, Subidh Ali, O. Sinanoglu
Continuous scaling of CMOS technology beyond sub-nanometer region has aggravated short-channel effects, resulting in increased leakage current and high power densities. Furthermore, elevated leakage current and power density render CMOS based security-critical applications vulnerable to power-side-channel attacks. Carbon Nanotubes (CNT) is a promising alternative to CMOS technology. It offers superior transport properties, excellent thermal conductivities, high current capacities, and low power densities. Besides area, power and performance, adherence to hardware security aspects have become an important criteria today. In this work, we present the first study on power-side-channel analysis of ciphers implemented using CNTFETs. Our simulation results show that for 130 power traces, the simple power analysis (SPA) attack success rate is less than 0.35 for CNTFET based ciphers, whereas it is greater than 0.95 for CMOS based ciphers. For correlation power analysis, the difference of correlation coefficient of the correct key and closest wrong key guess is 1.3 for CMOS based design, and less than 0.56 for CNTFET based ciphers for 20,000 power traces, which implies lesser distinguishability of correct key in case of CNTFETs. These results indicate that CNT offers a higher resilience to power-side-channel attacks than CMOS.
{"title":"Power-side-channel analysis of carbon nanotube FET based design","authors":"Chandra K. H. Suresh, Bodhisatwa Mazumdar, Subidh Ali, O. Sinanoglu","doi":"10.1109/IOLTS.2016.7604705","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604705","url":null,"abstract":"Continuous scaling of CMOS technology beyond sub-nanometer region has aggravated short-channel effects, resulting in increased leakage current and high power densities. Furthermore, elevated leakage current and power density render CMOS based security-critical applications vulnerable to power-side-channel attacks. Carbon Nanotubes (CNT) is a promising alternative to CMOS technology. It offers superior transport properties, excellent thermal conductivities, high current capacities, and low power densities. Besides area, power and performance, adherence to hardware security aspects have become an important criteria today. In this work, we present the first study on power-side-channel analysis of ciphers implemented using CNTFETs. Our simulation results show that for 130 power traces, the simple power analysis (SPA) attack success rate is less than 0.35 for CNTFET based ciphers, whereas it is greater than 0.95 for CMOS based ciphers. For correlation power analysis, the difference of correlation coefficient of the correct key and closest wrong key guess is 1.3 for CMOS based design, and less than 0.56 for CNTFET based ciphers for 20,000 power traces, which implies lesser distinguishability of correct key in case of CNTFETs. These results indicate that CNT offers a higher resilience to power-side-channel attacks than CMOS.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"47 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77579229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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