Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604707
R. M. Chen, E. Zhang, B. Bhuva
Differential flip-flop designs for high-speed operations are evaluated for single-event (SE) effects using circuit-level simulations. Results show input dependent SE performance of some differential flip-flop designs. Radiation hardenings by layout optimization for all differential flip-flops and by circuit design for SSTC are discussed.
{"title":"Single-event performance of differential flip-flop designs and hardening implication","authors":"R. M. Chen, E. Zhang, B. Bhuva","doi":"10.1109/IOLTS.2016.7604707","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604707","url":null,"abstract":"Differential flip-flop designs for high-speed operations are evaluated for single-event (SE) effects using circuit-level simulations. Results show input dependent SE performance of some differential flip-flop designs. Radiation hardenings by layout optimization for all differential flip-flops and by circuit design for SSTC are discussed.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"22 1","pages":"221-226"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73803442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604694
E. Vatajelu, G. D. Natale, P. Prinetto
A hardware True Random Number Generator (TRNG) yields random numbers from a physical process. Traditionally, such devices are based on statistically random signals such as thermal noise or other quantum phenomena. In this paper we propose an innovative TRNG design using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. We exploit the stochastic nature of the MTJ device switching, and perform on-the-fly temperature/current variation compensation. We show that the proposed solution keeps up with environmental changes and generates random sequences with high probability.
{"title":"STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation","authors":"E. Vatajelu, G. D. Natale, P. Prinetto","doi":"10.1109/IOLTS.2016.7604694","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604694","url":null,"abstract":"A hardware True Random Number Generator (TRNG) yields random numbers from a physical process. Traditionally, such devices are based on statistically random signals such as thermal noise or other quantum phenomena. In this paper we propose an innovative TRNG design using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. We exploit the stochastic nature of the MTJ device switching, and perform on-the-fly temperature/current variation compensation. We show that the proposed solution keeps up with environmental changes and generates random sequences with high probability.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"25 1","pages":"179-184"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74452634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604688
Xiang Chen, Wenhui Yang, Ming Zhao, Jing Wang
Soft errors induced by space radiation environments seriously influence the reliability of spacecrafts in space and satellite communications, especially with ever shrinking geometries, higher-density circuits, and power saving techniques. Most of the existing soft error mitigation methods depend on triple modular redundancy (TMR) or dual-modular redundancy (DMR) to the original design target directly, which enlarge the resource overhead dramatically. In this paper, the high level synthesis (HLS) is considered to help to reduce the resource consumptions of TMR or DMR. By the HLS on node sensitivity, all design resources can be classified into three types: sensitive submodules, semi-sensitive sub-modules, and insensitive submodules. TMR can be applied for sensitive sub-modules to provide the highest reliability, while gate sizing can be applied for semi-sensitive sub-modules, which can help to mitigate the soft errors and to minimize the overhead introduced by the fault-tolerant techniques efficiently. In order to verify the effectiveness of the above proposal, appropriate scheduling schemes combined with the HLS are performed to an FIR filter. By simulations it is shown that, with the reduction of area relative to TMR over 60% for the FIR design, the reliability can reach over 99.9%.
{"title":"HLS-based sensitivity-inductive soft error mitigation for satellite communication systems","authors":"Xiang Chen, Wenhui Yang, Ming Zhao, Jing Wang","doi":"10.1109/IOLTS.2016.7604688","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604688","url":null,"abstract":"Soft errors induced by space radiation environments seriously influence the reliability of spacecrafts in space and satellite communications, especially with ever shrinking geometries, higher-density circuits, and power saving techniques. Most of the existing soft error mitigation methods depend on triple modular redundancy (TMR) or dual-modular redundancy (DMR) to the original design target directly, which enlarge the resource overhead dramatically. In this paper, the high level synthesis (HLS) is considered to help to reduce the resource consumptions of TMR or DMR. By the HLS on node sensitivity, all design resources can be classified into three types: sensitive submodules, semi-sensitive sub-modules, and insensitive submodules. TMR can be applied for sensitive sub-modules to provide the highest reliability, while gate sizing can be applied for semi-sensitive sub-modules, which can help to mitigate the soft errors and to minimize the overhead introduced by the fault-tolerant techniques efficiently. In order to verify the effectiveness of the above proposal, appropriate scheduling schemes combined with the HLS are performed to an FIR filter. By simulations it is shown that, with the reduction of area relative to TMR over 60% for the FIR design, the reliability can reach over 99.9%.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"12 1","pages":"143-148"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86724844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604690
L. Sterpone, G. Cabodi, S. Finocchiaro, C. Loiacono, F. Savarese, B. Du
The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.
{"title":"Scalable FPGA graph model to detect routing faults","authors":"L. Sterpone, G. Cabodi, S. Finocchiaro, C. Loiacono, F. Savarese, B. Du","doi":"10.1109/IOLTS.2016.7604690","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604690","url":null,"abstract":"The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"45 1","pages":"155-160"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90632275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604710
Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede
Embedded implementations of cryptographic algorithms require countermeasures against side-channel attacks (SCAs), that exploit physical variables measured during the computation. These countermeasures increase cost, power consumption and latency of the device. One class of countermeasures, hiding, consists of a balanced circuit style, including balancing of the capacitances and delays; it requires full connection to avoid memory effect that is an effect caused by repeatedly recharged energy after being only partially discharged at the internal parasitic capacitance. This paper proposes binary decision diagrams (BDDs) to derive complex pull-down networks that fulfill all these requirements while being compact at the same time; it uses sense amplifier-based logic (SABL) to obtain well-balanced pre-charge circuits. An attack based on mutual information analysis (MIA) is applied to the AES S-boxes implemented in our novel secure logic style. After the evaluation at pre-layout SPICE level, the balanced circuit with BDD leaks less information than comparable logic styles, even though the implementation area is reduced by 40.6%, the power consumption up to 46.1% and the delay by 35.2% compared to the classic SABL approach.
加密算法的嵌入式实现需要针对侧信道攻击(sca)的对策，这种攻击利用在计算过程中测量的物理变量。这些对策增加了设备的成本、功耗和延迟。一类对抗措施，隐藏，由平衡电路风格组成，包括平衡电容和延迟;它需要完全连接，以避免记忆效应，即能量在内部寄生电容处仅部分放电后反复充电造成的效应。本文提出了二元决策图(bdd)来推导复杂的下拉网络，该网络在满足所有这些要求的同时又具有紧凑性;它使用基于感测放大器的逻辑(SABL)来获得平衡良好的预充电电路。本文提出了一种基于互信息分析(MIA)的AES s -box攻击方法。经过布局前SPICE水平的评估，与同类逻辑风格相比，BDD平衡电路泄漏的信息更少，尽管与经典SABL方法相比，实现面积减少了40.6%，功耗减少了46.1%，延迟减少了35.2%。
{"title":"Binary decision diagram to design balanced secure logic styles","authors":"Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede","doi":"10.1109/IOLTS.2016.7604710","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604710","url":null,"abstract":"Embedded implementations of cryptographic algorithms require countermeasures against side-channel attacks (SCAs), that exploit physical variables measured during the computation. These countermeasures increase cost, power consumption and latency of the device. One class of countermeasures, hiding, consists of a balanced circuit style, including balancing of the capacitances and delays; it requires full connection to avoid memory effect that is an effect caused by repeatedly recharged energy after being only partially discharged at the internal parasitic capacitance. This paper proposes binary decision diagrams (BDDs) to derive complex pull-down networks that fulfill all these requirements while being compact at the same time; it uses sense amplifier-based logic (SABL) to obtain well-balanced pre-charge circuits. An attack based on mutual information analysis (MIA) is applied to the AES S-boxes implemented in our novel secure logic style. After the evaluation at pre-layout SPICE level, the balanced circuit with BDD leaks less information than comparable logic styles, even though the implementation area is reduced by 40.6%, the power consumption up to 46.1% and the delay by 35.2% compared to the classic SABL approach.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"104 1","pages":"239-244"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76012295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604661
Shuhei Yoshida, Go Matsukawa, S. Izumi, H. Kawaguchi, M. Yoshimoto
This paper presents an accurate soft error propagation analysis technique. Especially, we focus on Single Event Upset (SEU) in flip-flop. The proposed technique can calculate the accurate error propagation probability considering logical masking on re-convergent paths with SAT solver efficiently. Experimental result shows that the proposed technique improves the computation time by 94.6% compared with the method with only SAT solver and the accuracy by 93.3% compared with the conventional method respectively.
{"title":"An soft error propagation analysis considering logical masking effect on re-convergent path","authors":"Shuhei Yoshida, Go Matsukawa, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/IOLTS.2016.7604661","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604661","url":null,"abstract":"This paper presents an accurate soft error propagation analysis technique. Especially, we focus on Single Event Upset (SEU) in flip-flop. The proposed technique can calculate the accurate error propagation probability considering logical masking on re-convergent paths with SAT solver efficiently. Experimental result shows that the proposed technique improves the computation time by 94.6% compared with the method with only SAT solver and the accuracy by 93.3% compared with the conventional method respectively.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"52 1","pages":"13-16"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77786509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604695
M. Andjelković, A. Ilic, V. Petrovic, M. Nenadovic, Z. Stamenkovic, G. Ristić
This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, number of load cells, and duration of the SET current pulse, has been derived. Use of the proposed critical charge model simplifies the analysis of the SPS cell's susceptibility to SETs for custom designs.
{"title":"SET response of a SEL protection switch for 130 and 250 nm CMOS technologies","authors":"M. Andjelković, A. Ilic, V. Petrovic, M. Nenadovic, Z. Stamenkovic, G. Ristić","doi":"10.1109/IOLTS.2016.7604695","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604695","url":null,"abstract":"This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, number of load cells, and duration of the SET current pulse, has been derived. Use of the proposed critical charge model simplifies the analysis of the SPS cell's susceptibility to SETs for custom designs.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"11 1","pages":"185-190"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87042569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-04DOI: 10.1109/IOLTS.2016.7604665
Zhen Gao, P. Reviriego, J. A. Maestro
Parallel matrix processing is a typical operation in many systems, and in particular matrix-vector multiplication is one of the most common operations in modern digital signal processing and digital communication systems. This paper proposes a fault tolerant design for parallel matrix-vector multiplications. The scheme combines ideas from Error Correction Codes with the self-checking capability of matrix-vector multiplication.
{"title":"Efficient fault tolerant parallel matrix-vector multiplications","authors":"Zhen Gao, P. Reviriego, J. A. Maestro","doi":"10.1109/IOLTS.2016.7604665","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604665","url":null,"abstract":"Parallel matrix processing is a typical operation in many systems, and in particular matrix-vector multiplication is one of the most common operations in modern digital signal processing and digital communication systems. This paper proposes a fault tolerant design for parallel matrix-vector multiplications. The scheme combines ideas from Error Correction Codes with the self-checking capability of matrix-vector multiplication.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"9 1","pages":"25-26"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86217571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-01DOI: 10.1109/IOLTS.2016.7604673
Jaime Espinosa, Carles Hernández, J. Abella
Future high-performance safety-relevant applications require microcontrollers delivering higher performance than the existing certified ones. However, means for assessing their dependability are needed so that they can be certified against safety critical certification standars (e.g ISO26262). Dependability assessment analyses performed at high level of abstraction inject single faults to investigate the effects these have in the system. In this work we show that single faults do not comprise the whole picture, due to fault multiplicities and reactivations. Later we prove that, by injecting complex fault models that consider multiplicities and reactivations in higher levels of abstraction, results are substantially different, thus indicating that a change in the methodology is needed.
{"title":"Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection","authors":"Jaime Espinosa, Carles Hernández, J. Abella","doi":"10.1109/IOLTS.2016.7604673","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604673","url":null,"abstract":"Future high-performance safety-relevant applications require microcontrollers delivering higher performance than the existing certified ones. However, means for assessing their dependability are needed so that they can be certified against safety critical certification standars (e.g ISO26262). Dependability assessment analyses performed at high level of abstraction inject single faults to investigate the effects these have in the system. In this work we show that single faults do not comprise the whole picture, due to fault multiplicities and reactivations. Later we prove that, by injecting complex fault models that consider multiplicities and reactivations in higher levels of abstraction, results are substantially different, thus indicating that a change in the methodology is needed.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"5 1","pages":"60-65"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87846855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-05DOI: 10.1109/IOLTS.2016.7604682
Mauricio D. Gutierrez, V. Tenentes, T. Kazmierski
In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.
{"title":"Susceptible workload driven selective fault tolerance using a probabilistic fault model","authors":"Mauricio D. Gutierrez, V. Tenentes, T. Kazmierski","doi":"10.1109/IOLTS.2016.7604682","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604682","url":null,"abstract":"In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"115-120"},"PeriodicalIF":0.0,"publicationDate":"2016-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80127997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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