Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481330
M. García-Vélez, Á. L. Álvarez, C. Coya, G. Alvarado, X. Díez-Betriu, A. de Andrés, J. Jiménez-Trillo
Electric arc erosion performed at low continuous voltages has been recently proven as a successful patterning technique for thin films of different conductive materials. In this work, we present an application of this procedure to materials typically aimed for device electrodes, such as indium tin oxide (ITO), gold (Au), graphene oxide (GO) or aluminum doped zinc oxide (AZO), as well as a more in depth study of the electrical discharge generation at submicron scale, which allows optimizing the procedure.
{"title":"Direct-write patterning of metals and graphene oxide electrodes by arc erosion for organic device manufacturing","authors":"M. García-Vélez, Á. L. Álvarez, C. Coya, G. Alvarado, X. Díez-Betriu, A. de Andrés, J. Jiménez-Trillo","doi":"10.1109/CDE.2013.6481330","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481330","url":null,"abstract":"Electric arc erosion performed at low continuous voltages has been recently proven as a successful patterning technique for thin films of different conductive materials. In this work, we present an application of this procedure to materials typically aimed for device electrodes, such as indium tin oxide (ITO), gold (Au), graphene oxide (GO) or aluminum doped zinc oxide (AZO), as well as a more in depth study of the electrical discharge generation at submicron scale, which allows optimizing the procedure.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"3 1","pages":"13-16"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80879714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481334
Z. Gao, M. Romero, F. Calle
AIGaN/GaN mesa etching using different plasma combinations of Cl2/Ar, Cl2/BCl3 and Cl2/CF4 by inductively coupled plasma was investigated. It was observed that the etch rate of Cl2/Ar increases linearly with the Ar content. In contrast to the Ar-based mixtures, Cl2/BCl3 and Cl2/CF4 plasma combinations show a damage-free surface. Furthermore, the lowest isolation current values achieved in devices with reduced sheet resistance were achieved by using Cl2/BCl3 plasma.
{"title":"Etching of AIGaN/GaN HEMT structures by Cl2-based ICP","authors":"Z. Gao, M. Romero, F. Calle","doi":"10.1109/CDE.2013.6481334","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481334","url":null,"abstract":"AIGaN/GaN mesa etching using different plasma combinations of Cl<sub>2</sub>/Ar, Cl<sub>2</sub>/BCl<sub>3</sub> and Cl<sub>2</sub>/CF<sub>4</sub> by inductively coupled plasma was investigated. It was observed that the etch rate of Cl<sub>2</sub>/Ar increases linearly with the Ar content. In contrast to the Ar-based mixtures, C<sub>l2</sub>/BCl<sub>3</sub> and Cl<sub>2</sub>/CF<sub>4</sub> plasma combinations show a damage-free surface. Furthermore, the lowest isolation current values achieved in devices with reduced sheet resistance were achieved by using C<sub>l2</sub>/BCl<sub>3</sub> plasma.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"39 1","pages":"29-32"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78389277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481343
C. Couso, R. Rengel, M. J. Martín
This paper presents a detailed study (using a 2D Monte Carlo simulator) of the impact on electronic transport of dopant segregation layers in Schottky Barrier MOSFETs operating under the linear regime. It is shown that with a careful control of the layer parameters the performance of the devices are significantly improved, with a boosting of the drive current and an important reduction of the linear resistance (Rds(on)). The origin of these advantages can be related to internal microscopic transport quantities like transit time, distance travelled, scattering mechanisms, etc. The enhanced performance of Schottky Barrier MOSFETs including dopant segregation layers confirms the suitability of this technology to help extending the IRTS roadmap for Silicon MOS devices.
{"title":"Schottky Barrier MOSFETs working in the linear regime: A Monte Carlo study of microscopic transport","authors":"C. Couso, R. Rengel, M. J. Martín","doi":"10.1109/CDE.2013.6481343","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481343","url":null,"abstract":"This paper presents a detailed study (using a 2D Monte Carlo simulator) of the impact on electronic transport of dopant segregation layers in Schottky Barrier MOSFETs operating under the linear regime. It is shown that with a careful control of the layer parameters the performance of the devices are significantly improved, with a boosting of the drive current and an important reduction of the linear resistance (Rds(on)). The origin of these advantages can be related to internal microscopic transport quantities like transit time, distance travelled, scattering mechanisms, etc. The enhanced performance of Schottky Barrier MOSFETs including dopant segregation layers confirms the suitability of this technology to help extending the IRTS roadmap for Silicon MOS devices.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"6 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79042511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481328
M. Pampillón, P. C. Feijoo, E. Andrés, J. Fierro
Gadolinium oxide thin films were deposited on Si by sputtering a metallic gadolinium target at high pressure followed by an in situ plasma oxidation. Different metal deposition times with the same oxidation conditions were studied. The deposition conditions were analyzed by means of glow discharge optical spectroscopy. The oxide films were characterized by X-ray photoelectron spectroscopy, high resolution transmission electron microscopy and Fourier transform infrared spectroscopy. The films resulted stoichiometric and amorphous. Metal-insulator-semiconductor structures were fabricated with two different metal gates: titanium and platinum. The devices were measured before and after temperature treatments in a forming gas atmosphere. The Ti gated devices scavenge the SiOx interlayer while the Pt ones show no metal reaction.
{"title":"Plasma oxidation of metallic gadolinium deposited on silicon by high pressure sputtering as high permittivity dielectric","authors":"M. Pampillón, P. C. Feijoo, E. Andrés, J. Fierro","doi":"10.1109/CDE.2013.6481328","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481328","url":null,"abstract":"Gadolinium oxide thin films were deposited on Si by sputtering a metallic gadolinium target at high pressure followed by an in situ plasma oxidation. Different metal deposition times with the same oxidation conditions were studied. The deposition conditions were analyzed by means of glow discharge optical spectroscopy. The oxide films were characterized by X-ray photoelectron spectroscopy, high resolution transmission electron microscopy and Fourier transform infrared spectroscopy. The films resulted stoichiometric and amorphous. Metal-insulator-semiconductor structures were fabricated with two different metal gates: titanium and platinum. The devices were measured before and after temperature treatments in a forming gas atmosphere. The Ti gated devices scavenge the SiOx interlayer while the Pt ones show no metal reaction.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"214 1","pages":"5-8"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76978950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481370
J. Pau, C. Núñez, A. Marín, E. Ruiz, J. Piqueras
Metal oxide nanowires are promising structures for the development of novel electronic and optoelectronic devices. In this work, we describe the synthesis of ZnO and CuO nanowires by vapor phase transport and Cu oxidation, respectively. After removal from the substrate, the nanowires are deposited on pairs of conductive electrodes previously evaporated on SiO2/Si substrates by dielectrophoresis. Al-doped ZnO (AZO) electrodes present good stability during the process and enable the fabrication of ultraviolet photoconductors and sensors along with ZnO nanowires. On the other hand, the deposition of CuO on AZO electrodes yields rectifying behavior related to the p-type conduction in CuO and the formation a diode-to-diode structure with the n-type electrodes. In contrast to ZnO photoconductors, these structures present optical response under illumination with visible and near-infrared light and short turn-on and recovery times.
{"title":"Metal oxide nanowires as building blocks for light detectors, gas sensors and biosensors","authors":"J. Pau, C. Núñez, A. Marín, E. Ruiz, J. Piqueras","doi":"10.1109/CDE.2013.6481370","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481370","url":null,"abstract":"Metal oxide nanowires are promising structures for the development of novel electronic and optoelectronic devices. In this work, we describe the synthesis of ZnO and CuO nanowires by vapor phase transport and Cu oxidation, respectively. After removal from the substrate, the nanowires are deposited on pairs of conductive electrodes previously evaporated on SiO2/Si substrates by dielectrophoresis. Al-doped ZnO (AZO) electrodes present good stability during the process and enable the fabrication of ultraviolet photoconductors and sensors along with ZnO nanowires. On the other hand, the deposition of CuO on AZO electrodes yields rectifying behavior related to the p-type conduction in CuO and the formation a diode-to-diode structure with the n-type electrodes. In contrast to ZnO photoconductors, these structures present optical response under illumination with visible and near-infrared light and short turn-on and recovery times.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"7 1","pages":"171-174"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75621671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481346
M. Rao, N. Murty
An improved analytical model for the DC characteristics of 4H-SiC MEtal Semiconductor Field Effect Transistors (MESFETs) is proposed. The model takes into account three major effects namely substrate trapping, surface trapping and thermal effects to describe the DC behavior of the device. The analytical model of I-V characteristics incorporate Caughey-Thomas model of field dependence electron mobility, substrate trapping of electrons by multiple deep level traps (which is the characteristic of 4H-SiC) and two-dimensional analysis of charge distribution under the gate. The collapse of drain current is observed on the I-V characteristics. This unique model proposed is a complete model which takes into consideration all the critical material defects and thermal effects with trapping. Hence the model behavior is very close to real time MESFET.
{"title":"An improved I-V model of 4H-SiC MESFETs incorporating substrate trapping, surface trapping and thermal effects","authors":"M. Rao, N. Murty","doi":"10.1109/CDE.2013.6481346","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481346","url":null,"abstract":"An improved analytical model for the DC characteristics of 4H-SiC MEtal Semiconductor Field Effect Transistors (MESFETs) is proposed. The model takes into account three major effects namely substrate trapping, surface trapping and thermal effects to describe the DC behavior of the device. The analytical model of I-V characteristics incorporate Caughey-Thomas model of field dependence electron mobility, substrate trapping of electrons by multiple deep level traps (which is the characteristic of 4H-SiC) and two-dimensional analysis of charge distribution under the gate. The collapse of drain current is observed on the I-V characteristics. This unique model proposed is a complete model which takes into consideration all the critical material defects and thermal effects with trapping. Hence the model behavior is very close to real time MESFET.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"35 1","pages":"75-78"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85187240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481403
V. Parra, T. Carballo, D. Cancillo, B. Moralejo, O. Martínez, J. Jiménez, J. Bullón, J. Míguez, R. Ordás
Photovoltaic (PV) industry is facing one of its worst times ever. The over-capacity and the reduced market worldwide are impacting the supply/demand across the PV value chain, leading to certainly low sell prices, noticeably below the production costs. As a consequence, many factories are going into insolvency in these times. In addition, the insufficient options to install PV modules demand devices based on well-optimized cost/performance (CP) ratios. Crystalline growth of silicon solar wafers for PV silicon devices has a direct influence on this critical relation. Two industrial approaches aiming at improving the CP ratio will be presented in this paper: i) the use of high-grade umg-Si feedstock and ii) the implementation of new seed-growth monocast process.
{"title":"Trends in crystalline silicon growth for low cost and efficient photovoltaic cells","authors":"V. Parra, T. Carballo, D. Cancillo, B. Moralejo, O. Martínez, J. Jiménez, J. Bullón, J. Míguez, R. Ordás","doi":"10.1109/CDE.2013.6481403","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481403","url":null,"abstract":"Photovoltaic (PV) industry is facing one of its worst times ever. The over-capacity and the reduced market worldwide are impacting the supply/demand across the PV value chain, leading to certainly low sell prices, noticeably below the production costs. As a consequence, many factories are going into insolvency in these times. In addition, the insufficient options to install PV modules demand devices based on well-optimized cost/performance (CP) ratios. Crystalline growth of silicon solar wafers for PV silicon devices has a direct influence on this critical relation. Two industrial approaches aiming at improving the CP ratio will be presented in this paper: i) the use of high-grade umg-Si feedstock and ii) the implementation of new seed-growth monocast process.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"63 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73518242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481329
F. Gomez-Folgar, E. Comesaña, R. Valin, A. García-Loureiro, T. F. Pena
It is well-known that nanodevice simulations are a high CPU demanding task. Currently, the environmental concern and the green IT revolution have made necessary to reuse the available computational resources being, at the same time, indispensable to reduce the energy consumption as much as possible. Nowadays, thanks to the cloud technology, it is possible to perform on-demand scaling of computational resources. Facilitating the optimal use of resources as they are required, it is possible to optimize the power consumption. In this paper, the possibilities of a private cloud to deploy and use Sentaurus, a tool for nanodevice simulation, are analysed. The architecture of the infrastructure that is being employed to perform semiconductor device simulations and to reuse the available computational power is also presented.
{"title":"Nanodevice simulations on CloudStack","authors":"F. Gomez-Folgar, E. Comesaña, R. Valin, A. García-Loureiro, T. F. Pena","doi":"10.1109/CDE.2013.6481329","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481329","url":null,"abstract":"It is well-known that nanodevice simulations are a high CPU demanding task. Currently, the environmental concern and the green IT revolution have made necessary to reuse the available computational resources being, at the same time, indispensable to reduce the energy consumption as much as possible. Nowadays, thanks to the cloud technology, it is possible to perform on-demand scaling of computational resources. Facilitating the optimal use of resources as they are required, it is possible to optimize the power consumption. In this paper, the possibilities of a private cloud to deploy and use Sentaurus, a tool for nanodevice simulation, are analysed. The architecture of the infrastructure that is being employed to perform semiconductor device simulations and to reuse the available computational power is also presented.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"86 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76792308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481364
G. Flores, F. Perdigones, J. Quero
This paper reports an inexpensive and simple method to impulse fluid in PCB-based Lab on a Chip (LOC) MEMS devices. This method consists on using pressurized SU-8 chambers, with membranes as cover. The membrane is burst thank to the increase of pressure in the chamber due to the increase of temperature, at constant volume. The increase of temperature is achieved supplying voltage to a Surface-Mounted-Device (SMD) resistor. This method is intended for fabricating autonomous and inexpensive LOC devices.
本文报道了一种在基于pcb的芯片实验室(Lab on a Chip, LOC) MEMS器件中实现流体脉冲的廉价而简单的方法。这种方法包括使用加压的SU-8室，用膜作为覆盖物。在体积不变的情况下，由于温度升高，腔内压力增加，膜破裂。温度的升高是通过向表面贴装器件(SMD)电阻提供电压来实现的。该方法用于制造自主和廉价的LOC器件。
{"title":"Pressurized microvalve with SMD-based activation to drive fluid in low-cost and autonomous MEMS","authors":"G. Flores, F. Perdigones, J. Quero","doi":"10.1109/CDE.2013.6481364","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481364","url":null,"abstract":"This paper reports an inexpensive and simple method to impulse fluid in PCB-based Lab on a Chip (LOC) MEMS devices. This method consists on using pressurized SU-8 chambers, with membranes as cover. The membrane is burst thank to the increase of pressure in the chamber due to the increase of temperature, at constant volume. The increase of temperature is achieved supplying voltage to a Surface-Mounted-Device (SMD) resistor. This method is intended for fabricating autonomous and inexpensive LOC devices.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"11 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85240582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481372
B. Arredondo, B. Romero, C. de Dios, R. Vergaz, R. Criado, J. Sánchez-Pena
Organic bulk heterojunction photodiodes based on a blend of poly(3-hexylthiophene):1-(3-methoxycarbonyl)-propyl-1-1-phenyl-(6, 6)C61 (P3HT:PCBM) have been fabricated with different active layer thicknesses. Current-voltage characteristics and cut-off frequency were measured under Green-LED illumination. Impedance measurements were performed and a simple equivalent circuit was used to fit the resulting Cole-cole diagram. Parameters obtained from the fit were used to estimate the theoretical photodetector cut-off frequency and compared to the experimental one. The material dielectric constant was estimated using the capacitance obtained from the impedance fit.
{"title":"Thickness dependence of organic photodetector bandwidth","authors":"B. Arredondo, B. Romero, C. de Dios, R. Vergaz, R. Criado, J. Sánchez-Pena","doi":"10.1109/CDE.2013.6481372","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481372","url":null,"abstract":"Organic bulk heterojunction photodiodes based on a blend of poly(3-hexylthiophene):1-(3-methoxycarbonyl)-propyl-1-1-phenyl-(6, 6)C61 (P3HT:PCBM) have been fabricated with different active layer thicknesses. Current-voltage characteristics and cut-off frequency were measured under Green-LED illumination. Impedance measurements were performed and a simple equivalent circuit was used to fit the resulting Cole-cole diagram. Parameters obtained from the fit were used to estimate the theoretical photodetector cut-off frequency and compared to the experimental one. The material dielectric constant was estimated using the capacitance obtained from the impedance fit.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"25 1","pages":"179-182"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84109001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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