Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481386
A. Herrera, Y. Jato
One of the industry sectors with the largest revenue in the telecommunication field is the wireless communications field. Wireless operators try to offer products that fulfill the user demands in terms of price, battery life and product quality. All these requirements must be also fulfilled by the designer of the MMIC (Microwave Monolithic Integrated Circuits) circuits that will be used in those wireless terminals, achieving a reliable design, with high performance, low cost and if possible in one or two foundry iterations so as to bring the product out to the market as soon as possible. Silicon based technologies are the lowest cost ones. These technologies don't include some essential components for the design of RF circuits, which leads to measurement results quite different from those simulated. The deep study of the problems presented when designing Si based RF circuits recommends the use of electromagnetic simulation or coo-simulation tools. The paper shows different simulation techniques that help the designer to obtain better designs with a lower cost, as well as reduced foundry iterations.
{"title":"Improving Yield on RF-CMOS ICs","authors":"A. Herrera, Y. Jato","doi":"10.1109/CDE.2013.6481386","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481386","url":null,"abstract":"One of the industry sectors with the largest revenue in the telecommunication field is the wireless communications field. Wireless operators try to offer products that fulfill the user demands in terms of price, battery life and product quality. All these requirements must be also fulfilled by the designer of the MMIC (Microwave Monolithic Integrated Circuits) circuits that will be used in those wireless terminals, achieving a reliable design, with high performance, low cost and if possible in one or two foundry iterations so as to bring the product out to the market as soon as possible. Silicon based technologies are the lowest cost ones. These technologies don't include some essential components for the design of RF circuits, which leads to measurement results quite different from those simulated. The deep study of the problems presented when designing Si based RF circuits recommends the use of electromagnetic simulation or coo-simulation tools. The paper shows different simulation techniques that help the designer to obtain better designs with a lower cost, as well as reduced foundry iterations.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"21 1","pages":"237-240"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90076708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481397
A. Crespo-Yepes, J. Martín-Martínez, V. Iglesias, R. Rodríguez, M. Porti, M. Nafría, X. Aymerich, M. Lanza
Some high-k dielectric materials show two interchangeable conductivity states (a High Resistive State, HRS, and Low Resistive State, LRS) in what is known as Resistive Switching (RS), being the basis of ReRAMs. In this work, the Resistive Switching (RS) phenomenon is studied on ultrathin Hf based high-k dielectrics at the nanoscale, by using the conductive atomic force microscopy (CAFM), and at device level. The CAFM allows analysing the local dielectric properties of the RS phenomenon. At device level, the temperature dependence of the RS-related gate currents during the HRS and LRS has been studied in MOSFETs.
{"title":"Nanoscale and device level analysis of the resistive switching phenomenon in ultra-thin high-k gate dielectrics","authors":"A. Crespo-Yepes, J. Martín-Martínez, V. Iglesias, R. Rodríguez, M. Porti, M. Nafría, X. Aymerich, M. Lanza","doi":"10.1109/CDE.2013.6481397","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481397","url":null,"abstract":"Some high-k dielectric materials show two interchangeable conductivity states (a High Resistive State, HRS, and Low Resistive State, LRS) in what is known as Resistive Switching (RS), being the basis of ReRAMs. In this work, the Resistive Switching (RS) phenomenon is studied on ultrathin Hf based high-k dielectrics at the nanoscale, by using the conductive atomic force microscopy (CAFM), and at device level. The CAFM allows analysing the local dielectric properties of the RS phenomenon. At device level, the temperature dependence of the RS-related gate currents during the HRS and LRS has been studied in MOSFETs.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"62 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85893507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481339
A. Castro-Carranza, M. Cheralathan, B. Iñíguez, J. Pallarès, C. Valla, F. Poullet, G. Depeyrot, M. Estrada
In this work we present the process entailed to implement a model for organic thin-film transistors (OTFTs): from the development of the complete model, to its validation and use in a circuit simulator. For this purpose the current-voltage model (UMEM) and its related charge and capacitance model for OTFTs (UBCM) were applied. The complete model is valid in the sub- and above-threshold regimes, and it is continuous in the transition from linear to saturation conditions. UMEM and UBCCM in Verilog-A are used with the SMASH circuit simulator for the analysis of the DC, small signal and transient behavior of OTFT circuits, and are compared with experimental data showing a good agreement.
{"title":"OTFT modeling: Development and implementation in EDA tools","authors":"A. Castro-Carranza, M. Cheralathan, B. Iñíguez, J. Pallarès, C. Valla, F. Poullet, G. Depeyrot, M. Estrada","doi":"10.1109/CDE.2013.6481339","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481339","url":null,"abstract":"In this work we present the process entailed to implement a model for organic thin-film transistors (OTFTs): from the development of the complete model, to its validation and use in a circuit simulator. For this purpose the current-voltage model (UMEM) and its related charge and capacitance model for OTFTs (UBCM) were applied. The complete model is valid in the sub- and above-threshold regimes, and it is continuous in the transition from linear to saturation conditions. UMEM and UBCCM in Verilog-A are used with the SMASH circuit simulator for the analysis of the DC, small signal and transient behavior of OTFT circuits, and are compared with experimental data showing a good agreement.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"11 1","pages":"49-50"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86149841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481358
F. J. Delgado, J. Quero, J. Garcia, C. L. Tarrida, J. M. Moreno, A. G. Saez, P. Ortega
The design, manufacturing and calibration of an improved miniaturized two axis sun sensor for satellite attitude control will be shown. The high precision is obtained by the subdivision of the field of view (FOV). The FOV and the resolution obtained are ±60° and 0.5° for the coarse measure and ±6° with precision better than 0.05° for the fine measure.
{"title":"SENSOSOL: MultiFOV 4-Quadrant high precision sun sensor for satellite attitude control","authors":"F. J. Delgado, J. Quero, J. Garcia, C. L. Tarrida, J. M. Moreno, A. G. Saez, P. Ortega","doi":"10.1109/CDE.2013.6481358","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481358","url":null,"abstract":"The design, manufacturing and calibration of an improved miniaturized two axis sun sensor for satellite attitude control will be shown. The high precision is obtained by the subdivision of the field of view (FOV). The FOV and the resolution obtained are ±60° and 0.5° for the coarse measure and ±6° with precision better than 0.05° for the fine measure.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"5 1","pages":"123-126"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87069363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481388
Y. Berencén, J. Ramírez, B. Garrido
We report on the electrical and electroluminescence properties of four different layers based on Er-doped silicon oxide (or nitride) with (or without) silicon nanocrystals. Electrical measurements have allowed us to identify that samples composed by silicon nitride matrices present a Poole-Frenkel-type conduction, whereas those ones formed by silicon oxide matrices show a Fowler-Nordheim tunneling mechanism. In addition, infrared power efficiency at 1.54 μm has shown to be two orders of magnitude larger for Er-doped silicon oxide layers than for Er-doped silicon nitrides. Moreover, an interesting trade off between power efficiency at 1.54 μm and device operation lifetime has been observed by comparing both Er-doped silicon oxides and Er-doped silicon nitride layers.
{"title":"Er-doped Si-based electroluminescent capacitors: Role of different host matrices on the electrical and luminescence properties","authors":"Y. Berencén, J. Ramírez, B. Garrido","doi":"10.1109/CDE.2013.6481388","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481388","url":null,"abstract":"We report on the electrical and electroluminescence properties of four different layers based on Er-doped silicon oxide (or nitride) with (or without) silicon nanocrystals. Electrical measurements have allowed us to identify that samples composed by silicon nitride matrices present a Poole-Frenkel-type conduction, whereas those ones formed by silicon oxide matrices show a Fowler-Nordheim tunneling mechanism. In addition, infrared power efficiency at 1.54 μm has shown to be two orders of magnitude larger for Er-doped silicon oxide layers than for Er-doped silicon nitrides. Moreover, an interesting trade off between power efficiency at 1.54 μm and device operation lifetime has been observed by comparing both Er-doped silicon oxides and Er-doped silicon nitride layers.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"74 1","pages":"245-248"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88763284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481353
I. Gràcia, S. Vallejos, R. Cumeras, M. Salleras, E. Figueras, J. Santander, N. Sabaté, J. Esquivel, C. Calaza, L. Fonseca, C. Cané
The needs of the Agrofood sector in terms of fast and low cost analytical devices and systems and the capabilities of the Micro and Nano Technologies are reviewed and main R&D activity carried out in the last years is referenced. Despite the Food sector is very conservative in terms of introducing new technologies in their standard analysis procedures, it is expected that in the near future, sensors and Micro and Nano technologies can play an important role in commercial products.
{"title":"Sensors and Micro and Nano Technologies for the Food Sector","authors":"I. Gràcia, S. Vallejos, R. Cumeras, M. Salleras, E. Figueras, J. Santander, N. Sabaté, J. Esquivel, C. Calaza, L. Fonseca, C. Cané","doi":"10.1109/CDE.2013.6481353","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481353","url":null,"abstract":"The needs of the Agrofood sector in terms of fast and low cost analytical devices and systems and the capabilities of the Micro and Nano Technologies are reviewed and main R&D activity carried out in the last years is referenced. Despite the Food sector is very conservative in terms of introducing new technologies in their standard analysis procedures, it is expected that in the near future, sensors and Micro and Nano technologies can play an important role in commercial products.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"11 1","pages":"103-106"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89678373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481387
J. Martín-Martínez, M. Moras, N. Ayala, V. Velayudhan, R. Rodríguez, M. Nafría, X. Aymerich
In small devices, Bias Temperature Instability (BTI) produces discrete threshold voltage (VT) shifts, which are attributed to the charge and discharge of single defects. A deep knowledge of the properties of these defects is required in order to correctly evaluate the BTI degradation in devices. In this work, these defects are experimentally characterized. Their properties are the input parameters to a previously presented BTI physics-based model that allows the evaluation of the corresponding VT shift. The model has been included in a circuit simulator. As an example the BTI effects on SRAM performance on SRAM cells performance and variability is studied.
{"title":"Modeling of time-dependent variability caused by Bias Temperature Instability","authors":"J. Martín-Martínez, M. Moras, N. Ayala, V. Velayudhan, R. Rodríguez, M. Nafría, X. Aymerich","doi":"10.1109/CDE.2013.6481387","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481387","url":null,"abstract":"In small devices, Bias Temperature Instability (BTI) produces discrete threshold voltage (VT) shifts, which are attributed to the charge and discharge of single defects. A deep knowledge of the properties of these defects is required in order to correctly evaluate the BTI degradation in devices. In this work, these defects are experimentally characterized. Their properties are the input parameters to a previously presented BTI physics-based model that allows the evaluation of the corresponding VT shift. The model has been included in a circuit simulator. As an example the BTI effects on SRAM performance on SRAM cells performance and variability is studied.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"30 1","pages":"241-244"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88096367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481408
E. N. Astorga, E. Martinez, J. Barrado
A low cost spray-coating technique is implemented to study the boron diffusion in n-type silicon wafers. Temperature and diffusion time have been the main factors on the resulting sheet resistance (Rsheet), reaching the highest values at high temperatures and diffusion times due to the formation of a thick borosilicate glass layer on the wafer surface. This layer has been etched off by HF dipping resulting on more doped emitters. Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) measurements have been carried out in order to analyze the correlation of Rsheet with the amount of sprayed precursor.
{"title":"Low cost spray-coating boron diffusion on n-type silicon","authors":"E. N. Astorga, E. Martinez, J. Barrado","doi":"10.1109/CDE.2013.6481408","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481408","url":null,"abstract":"A low cost spray-coating technique is implemented to study the boron diffusion in n-type silicon wafers. Temperature and diffusion time have been the main factors on the resulting sheet resistance (Rsheet), reaching the highest values at high temperatures and diffusion times due to the formation of a thick borosilicate glass layer on the wafer surface. This layer has been etched off by HF dipping resulting on more doped emitters. Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) measurements have been carried out in order to analyze the correlation of Rsheet with the amount of sprayed precursor.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"30 1","pages":"325-328"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87104594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481350
D. Vega, R. Najar, M. Piña, A. Rodríguez
In this paper we propose the use of macroporous silicon for microelectronic devices. We propose and study four different FET transistor structures using macroporous silicon as base material. Macroporous silicon is a novel material whose application most commonly suggested is as photonic crystals. Nevertheless, this is a versatile structured material with applications in many different areas, though microelectronics is not usually cited. We suggest its use for electronics devices as a FET transistor. The presented structures are studied by simulation in device modelling software (TCAD). Two kinds of operation modes have been considered: vertical (axial) and horizontal (transverse) in relation to the etched pores in silicon. One of the notable features of the described structures is the ability to have a massive number of identical unitary-cell transistor devices operating in parallel, having an all-around gate. These features allow driving the gate with low controlling voltages while handling large current density. Furthermore, the external device volume remains small thanks to the very large area-to-volume ratio. Thanks to the considerable amount of active area achievable, we further propose the use of such devices for low-voltage power applications. In this paper we present the obtained results of our simulations of the proposed devices.
{"title":"Macroporous silicon FET transistors for power applications","authors":"D. Vega, R. Najar, M. Piña, A. Rodríguez","doi":"10.1109/CDE.2013.6481350","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481350","url":null,"abstract":"In this paper we propose the use of macroporous silicon for microelectronic devices. We propose and study four different FET transistor structures using macroporous silicon as base material. Macroporous silicon is a novel material whose application most commonly suggested is as photonic crystals. Nevertheless, this is a versatile structured material with applications in many different areas, though microelectronics is not usually cited. We suggest its use for electronics devices as a FET transistor. The presented structures are studied by simulation in device modelling software (TCAD). Two kinds of operation modes have been considered: vertical (axial) and horizontal (transverse) in relation to the etched pores in silicon. One of the notable features of the described structures is the ability to have a massive number of identical unitary-cell transistor devices operating in parallel, having an all-around gate. These features allow driving the gate with low controlling voltages while handling large current density. Furthermore, the external device volume remains small thanks to the very large area-to-volume ratio. Thanks to the considerable amount of active area achievable, we further propose the use of such devices for low-voltage power applications. In this paper we present the obtained results of our simulations of the proposed devices.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"12 1","pages":"91-94"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86354706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481342
J. Garcia, M. J. Martín, R. Rengel
In this paper a particle-based Monte Carlo research of the static performance of double gate Schottky barrier MOSFETs is presented. As the devices simulated have extremely reduced sizes, space quantization phenomena appear within the channel. For describing this effect the effective potential approach is considered. Several static quantities are studied in order to characterize the effects of the inclusion of a second gate in this kind of devices. Besides, the consequences of a drastic reduction of the devices' active layer thickness are also experimented. Results demonstrate that disregarding quantum phenomena leads to a distortion of the electron density profiles and to an overestimation of the current which flows within the devices. The inclusion of a second gate in these devices provokes the growth of the drain current. However, the decrease of the active layer thickness attenuates the drive currents, even though, the tunnel injection current, comparatively, grows.
{"title":"Space quantization effects in double gate SB-MOSFETs: Role of the active layer thickness","authors":"J. Garcia, M. J. Martín, R. Rengel","doi":"10.1109/CDE.2013.6481342","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481342","url":null,"abstract":"In this paper a particle-based Monte Carlo research of the static performance of double gate Schottky barrier MOSFETs is presented. As the devices simulated have extremely reduced sizes, space quantization phenomena appear within the channel. For describing this effect the effective potential approach is considered. Several static quantities are studied in order to characterize the effects of the inclusion of a second gate in this kind of devices. Besides, the consequences of a drastic reduction of the devices' active layer thickness are also experimented. Results demonstrate that disregarding quantum phenomena leads to a distortion of the electron density profiles and to an overestimation of the current which flows within the devices. The inclusion of a second gate in these devices provokes the growth of the drain current. However, the decrease of the active layer thickness attenuates the drive currents, even though, the tunnel injection current, comparatively, grows.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"36 1","pages":"59-62"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78044228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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