Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481413
A. Morales-Vilches, C. Voz, M. Colina, G. López, I. Martín, A. Orpella, J. Puigdollers, M. Garcia, R. Alcubilla
Silicon Heterojunction (SHJ) solar cells are one of the most promising alternatives for high efficiency industrially feasible solar cells. The structure of these devices is based on hydrogenated amorphous silicon (a-Si:H) layers deposited at low temperature on crystalline silicon (c-Si) substrates. This fabrication process reduces the thermal stress on the substrate and is compatible with thinner wafers. In this work, we present our recent progress in the fabrication of SHJ solar cells on p-type c-Si wafers. The deposition conditions of hydrogenated amorphous silicon-carbon (a-SiCx:H) layers obtained by Plasma Enhanced Chemical Vapor Deposition (PECVD) are optimized. We have also applied a novel laser-firing process to contact the rear side of the fabricated devices. In this way, solar cells with point contacts through rear passivating layers can be fabricated without any photolithographic step. Recently, our group has obtained a remarkable conversion efficiency of 17.2 % on 1 cm2 SHJ solar cells fabricated in a fully low temperature process.
{"title":"Progress in silicon heterojunction solar cell fabrication with rear laser-fired contacts","authors":"A. Morales-Vilches, C. Voz, M. Colina, G. López, I. Martín, A. Orpella, J. Puigdollers, M. Garcia, R. Alcubilla","doi":"10.1109/CDE.2013.6481413","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481413","url":null,"abstract":"Silicon Heterojunction (SHJ) solar cells are one of the most promising alternatives for high efficiency industrially feasible solar cells. The structure of these devices is based on hydrogenated amorphous silicon (a-Si:H) layers deposited at low temperature on crystalline silicon (c-Si) substrates. This fabrication process reduces the thermal stress on the substrate and is compatible with thinner wafers. In this work, we present our recent progress in the fabrication of SHJ solar cells on p-type c-Si wafers. The deposition conditions of hydrogenated amorphous silicon-carbon (a-SiCx:H) layers obtained by Plasma Enhanced Chemical Vapor Deposition (PECVD) are optimized. We have also applied a novel laser-firing process to contact the rear side of the fabricated devices. In this way, solar cells with point contacts through rear passivating layers can be fabricated without any photolithographic step. Recently, our group has obtained a remarkable conversion efficiency of 17.2 % on 1 cm2 SHJ solar cells fabricated in a fully low temperature process.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"CE-30 1","pages":"345-348"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84572166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481394
Mario Lanza, Y. Wang, Huiling Duan, M. Porti, M. Nafría, A. Bayerl, X. Aymerich, T. Gao, Zhongfan Liu, Yudao Zhang, H. Liang, Guangyin Jing
Graphene layers can be used as the conductive channel in metal oxide semiconductor field effect transistors, metallic electrodes in capacitors, etc. However, when graphene is grown by chemical vapor deposition (CVD), substrate-induced corrugations and strain-related wrinkles formed on the graphene layer impoverish the properties of these devices by lowering the conductance and increasing their variability. In this work, different nanoscale experimental techniques have been used to investigate the morphology of as-grown and transferred graphene sheets on different substrates. We show that while the compressive strain (from the growth process) in the graphene sheet on flat substrates is minimized by generating wrinkles, on rough substrates it can be minimized by improving the graphene-substrate adhesion, leading to lower densities of wrinkles. This method allows the design of wrinkle-free graphene based devices.
{"title":"Nanoscale morphology of graphene on different substrates","authors":"Mario Lanza, Y. Wang, Huiling Duan, M. Porti, M. Nafría, A. Bayerl, X. Aymerich, T. Gao, Zhongfan Liu, Yudao Zhang, H. Liang, Guangyin Jing","doi":"10.1109/CDE.2013.6481394","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481394","url":null,"abstract":"Graphene layers can be used as the conductive channel in metal oxide semiconductor field effect transistors, metallic electrodes in capacitors, etc. However, when graphene is grown by chemical vapor deposition (CVD), substrate-induced corrugations and strain-related wrinkles formed on the graphene layer impoverish the properties of these devices by lowering the conductance and increasing their variability. In this work, different nanoscale experimental techniques have been used to investigate the morphology of as-grown and transferred graphene sheets on different substrates. We show that while the compressive strain (from the growth process) in the graphene sheet on flat substrates is minimized by generating wrinkles, on rough substrates it can be minimized by improving the graphene-substrate adhesion, leading to lower densities of wrinkles. This method allows the design of wrinkle-free graphene based devices.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"24 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83217555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481417
O. Martinez, B. Moralejo, V. Hortelano, A. Tejero, M. González, J. Jiménez, J. Mass, V. Parra
Multi-crystalline Si is the preferred material in the photovoltaic world market due to the good balance between production costs and efficiency. However, it has a large number of defects acting as recombination centers for the photogenerated carriers. In this work, we use both the fast inspection provided by the photoluminescence imaging technique with the very high spatial resolution of the light beam induced current and electron beam induced current techniques, for obtaining a comprehensive understanding of the electrical activity and distribution of defects in this material.
{"title":"Trapping activity on multicrystalline Si wafers studied by combining fast PL imaging and high resolved electrical techniques","authors":"O. Martinez, B. Moralejo, V. Hortelano, A. Tejero, M. González, J. Jiménez, J. Mass, V. Parra","doi":"10.1109/CDE.2013.6481417","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481417","url":null,"abstract":"Multi-crystalline Si is the preferred material in the photovoltaic world market due to the good balance between production costs and efficiency. However, it has a large number of defects acting as recombination centers for the photogenerated carriers. In this work, we use both the fast inspection provided by the photoluminescence imaging technique with the very high spatial resolution of the light beam induced current and electron beam induced current techniques, for obtaining a comprehensive understanding of the electrical activity and distribution of defects in this material.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"94 1","pages":"361-364"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75914649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481377
E. García-García, Y. Meziani, J. Velazquez-Perez, E. Diez, J. Calvo-Gallcao
In this paper, we performed time domain terahertz spectroscopy (THz- TDS) of two drugs (Paracetamol and Ibuprofen). The THz- TDS is based on a Ti:Sapphire femtosecond laser and a two low-temperature grown GaAs photoconductive antennas for emission and detection of terahertz radiation. A working window from 0.2 to 2.5 THz was obtained. First, spectral response of water vapor absorption is reported and compared to HITRAN database. A good agreement was observed. Finally, the THz spectra of two commercial drugs (paracetamol and ibuprofen) were performed and absorption peaks were observed. Different behavior of the spectrum of both drugs was clearly found. Further simulations are under study to identify the origin of those peaks as well as enhancement of the experimental setup.
{"title":"Terahertz time domain spectroscopy for chemical identification","authors":"E. García-García, Y. Meziani, J. Velazquez-Perez, E. Diez, J. Calvo-Gallcao","doi":"10.1109/CDE.2013.6481377","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481377","url":null,"abstract":"In this paper, we performed time domain terahertz spectroscopy (THz- TDS) of two drugs (Paracetamol and Ibuprofen). The THz- TDS is based on a Ti:Sapphire femtosecond laser and a two low-temperature grown GaAs photoconductive antennas for emission and detection of terahertz radiation. A working window from 0.2 to 2.5 THz was obtained. First, spectral response of water vapor absorption is reported and compared to HITRAN database. A good agreement was observed. Finally, the THz spectra of two commercial drugs (paracetamol and ibuprofen) were performed and absorption peaks were observed. Different behavior of the spectrum of both drugs was clearly found. Further simulations are under study to identify the origin of those peaks as well as enhancement of the experimental setup.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"1 1","pages":"199-202"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78359088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481337
H. Jacquinot, D. Denis
This paper presents an extended wide-band physical scalable model developed at LETI for 3D high density trench decoupling capacitors manufactured by IPDIA. The capacitors provide a density of 80 nF/mm2 and are embedded in a high resistivity silicon substrate. Use of such capacitors for mixed circuits decoupling and filtering applications requires wide-band SPICE models. Therefore, a focus is done on improving the model frequency validity range in the low and high frequency bands. This paper proposes a new 3D trench decoupling capacitor R, L, C circuit topology including interconnects with a frequency range from 10 kHz up to 10 GHz.
{"title":"Wide frequency band scalable modeling of 3D embedded decoupling capacitors","authors":"H. Jacquinot, D. Denis","doi":"10.1109/CDE.2013.6481337","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481337","url":null,"abstract":"This paper presents an extended wide-band physical scalable model developed at LETI for 3D high density trench decoupling capacitors manufactured by IPDIA. The capacitors provide a density of 80 nF/mm2 and are embedded in a high resistivity silicon substrate. Use of such capacitors for mixed circuits decoupling and filtering applications requires wide-band SPICE models. Therefore, a focus is done on improving the model frequency validity range in the low and high frequency bands. This paper proposes a new 3D trench decoupling capacitor R, L, C circuit topology including interconnects with a frequency range from 10 kHz up to 10 GHz.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"16 1","pages":"41-44"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78369238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481376
V. Vijayvargiya, S. Vishvakarma
Tunneling field effect transistor (TFETs) has recently attracted considerable interest because of their potential use in low power logic application. In this paper, we have investigated the effect of uniform doping versus varying doping (Gaussian) profile on TFET performance. We have shown that off-state current and subthreshold slope (SS) in the TFET can be improved by using low doping profile at channel-drain junction. It provides an improved ION/IoFF and subthreshold slope of 1010 and 47 mV/dec respectively. Also by placing small high density layer in the channel near source-channel junction improve the SS to 43 mV/dec and Ion current by a few order. Finally, it is shown that ambipolar behavior is also reduced.
{"title":"Effect of doping profile on tunneling field effect transistor performance","authors":"V. Vijayvargiya, S. Vishvakarma","doi":"10.1109/CDE.2013.6481376","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481376","url":null,"abstract":"Tunneling field effect transistor (TFETs) has recently attracted considerable interest because of their potential use in low power logic application. In this paper, we have investigated the effect of uniform doping versus varying doping (Gaussian) profile on TFET performance. We have shown that off-state current and subthreshold slope (SS) in the TFET can be improved by using low doping profile at channel-drain junction. It provides an improved ION/IoFF and subthreshold slope of 1010 and 47 mV/dec respectively. Also by placing small high density layer in the channel near source-channel junction improve the SS to 43 mV/dec and Ion current by a few order. Finally, it is shown that ambipolar behavior is also reduced.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"7 1","pages":"195-198"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75602111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481389
E. Nogueira, A. Fernandez, A. Flórez, R. A. Santos, E. Mino
The Restriction of Hazardous Substances (RoHS) in electronic equipment imposed by legal considerations does not allow the manufacture of electronic equipments with alloys containing lead. As an ecological alternative, it can be used lead free alloys. Electrochemical migration is a reliability problem in printer circuit boards in high humidity environments. In this paper, the electrochemical migration of one solder that contains lead (Sn36Pb2Ag) and two lead free solder alloys (5n3.5Ag and Sn3.8Ag0.7Cu) were analyzed under presence of distilled water. It was analyzed the failure distribution times of three different types of solder pastes, with three voltages, and three strip spacing. Lead free solder pastes are more reliable than paste that contains lead. Exponential- Weibull model was the more adequate for the test results.
{"title":"Accelerated life tests of lead free solder alloys in presence of distilled water","authors":"E. Nogueira, A. Fernandez, A. Flórez, R. A. Santos, E. Mino","doi":"10.1109/CDE.2013.6481389","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481389","url":null,"abstract":"The Restriction of Hazardous Substances (RoHS) in electronic equipment imposed by legal considerations does not allow the manufacture of electronic equipments with alloys containing lead. As an ecological alternative, it can be used lead free alloys. Electrochemical migration is a reliability problem in printer circuit boards in high humidity environments. In this paper, the electrochemical migration of one solder that contains lead (Sn36Pb2Ag) and two lead free solder alloys (5n3.5Ag and Sn3.8Ag0.7Cu) were analyzed under presence of distilled water. It was analyzed the failure distribution times of three different types of solder pastes, with three voltages, and three strip spacing. Lead free solder pastes are more reliable than paste that contains lead. Exponential- Weibull model was the more adequate for the test results.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"38 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80758185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481374
I. Íñiguez-de-la-Torre, J. Mateos, T. González, V. Kaushal, M. Margala
In this work, a room temperature study of ballistic deflection transistors (BDTs) is performed. By applying various processing steps such as hard mask deposition, e-beam lithography, reactive ion etching, etc., BDTs were fabricated, and the interplay between the geometry and their performance is analyzed. The importance of the top drain terminal is also examined. The application of the BDT for different logic configurations on the basis of its asymmetric biasing behavior is studied. Using this concept, even a single BDT can be used as a logic gate.
{"title":"Ballistic deflection transistor: Geometry dependence and boolean operations","authors":"I. Íñiguez-de-la-Torre, J. Mateos, T. González, V. Kaushal, M. Margala","doi":"10.1109/CDE.2013.6481374","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481374","url":null,"abstract":"In this work, a room temperature study of ballistic deflection transistors (BDTs) is performed. By applying various processing steps such as hard mask deposition, e-beam lithography, reactive ion etching, etc., BDTs were fabricated, and the interplay between the geometry and their performance is analyzed. The importance of the top drain terminal is also examined. The application of the BDT for different logic configurations on the basis of its asymmetric biasing behavior is studied. Using this concept, even a single BDT can be used as a logic gate.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"21 1","pages":"187-190"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83657874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481402
S. Dueñas, E. Perez, H. Castán, H. García, L. Bailón
The performance of commercial solar cells is strongly controlled by the impurities and defects present in the substrates. Defects induce deep energy levels in the semiconductor bandgap, which degrade the carrier lifetime and quantum efficiency of solar cells. A comprehensive knowledge of the properties of defects require electrical characterization techniques providing information about the defect concentration, spatial distribution and physical origin. The experimental techniques available in our laboratory are described in this work. In contrast, the efficiency of single junction solar cells can be drastically improved by the formation of an intermediate band in the midgap of a semiconductor. The intermediate band can be created from deep level defects if their concentration is high enough. Experimental results proving the intermediate band formation are also presented in this work.
{"title":"The role of defects in solar cells: Control and detection defects in solar cells","authors":"S. Dueñas, E. Perez, H. Castán, H. García, L. Bailón","doi":"10.1109/CDE.2013.6481402","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481402","url":null,"abstract":"The performance of commercial solar cells is strongly controlled by the impurities and defects present in the substrates. Defects induce deep energy levels in the semiconductor bandgap, which degrade the carrier lifetime and quantum efficiency of solar cells. A comprehensive knowledge of the properties of defects require electrical characterization techniques providing information about the defect concentration, spatial distribution and physical origin. The experimental techniques available in our laboratory are described in this work. In contrast, the efficiency of single junction solar cells can be drastically improved by the formation of an intermediate band in the midgap of a semiconductor. The intermediate band can be created from deep level defects if their concentration is high enough. Experimental results proving the intermediate band formation are also presented in this work.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"26 1","pages":"301-304"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74088305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-21DOI: 10.1109/CDE.2013.6481351
G. Indalecio, A. García-Loureiro, M. Aldegunde, K. Kalna
A 3D drift-diffusion device simulator with implemented density-gradient quantum corrections is developed to run hundreds of simulations to gather variability characteristics in non-planar transistors. We have included the line edge roughness (LER), random dopants (RD), and metal gate granularity (MGG) induced variabilities, which are considered to be the most important sources of variability in device characteristics. The simulator is then applied to study a threshold voltage variability in a 25 nm gate length Si SOI FinFET due to LER and MGG. We found that the LER induced threshold variability has a mean value of 344.5 mV and σ of 4.7 mV while the MGG induced has a mean value of 349.9 mV and σ of 13.3 mV an order of magnitude greater than the LER variability.
开发了一个三维漂移扩散器件模拟器，实现了密度梯度量子校正，可以运行数百个模拟来收集非平面晶体管的可变性特性。我们包括线边缘粗糙度(LER)、随机掺杂剂(RD)和金属栅粒度(MGG)引起的变化，它们被认为是器件特性变化的最重要来源。然后应用该模拟器研究了由LER和MGG引起的25 nm栅极长度Si SOI FinFET的阈值电压变化。结果表明，LER诱发的阈值变异性均值为344.5 mV， σ值为4.7 mV，而MGG诱发的阈值变异性均值为349.9 mV， σ值为13.3 mV，比LER诱发的阈值变异性大一个数量级。
{"title":"Study of statistical variability in nanoscale transistors introduced by LER, RDF and MGG","authors":"G. Indalecio, A. García-Loureiro, M. Aldegunde, K. Kalna","doi":"10.1109/CDE.2013.6481351","DOIUrl":"https://doi.org/10.1109/CDE.2013.6481351","url":null,"abstract":"A 3D drift-diffusion device simulator with implemented density-gradient quantum corrections is developed to run hundreds of simulations to gather variability characteristics in non-planar transistors. We have included the line edge roughness (LER), random dopants (RD), and metal gate granularity (MGG) induced variabilities, which are considered to be the most important sources of variability in device characteristics. The simulator is then applied to study a threshold voltage variability in a 25 nm gate length Si SOI FinFET due to LER and MGG. We found that the LER induced threshold variability has a mean value of 344.5 mV and σ of 4.7 mV while the MGG induced has a mean value of 349.9 mV and σ of 13.3 mV an order of magnitude greater than the LER variability.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"73 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77398492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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