Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338373
Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, S. Lee, Mau-Chung Frank Chang
This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 1012.
{"title":"A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface","authors":"Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, S. Lee, Mau-Chung Frank Chang","doi":"10.1109/CICC.2015.7338373","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338373","url":null,"abstract":"This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 1012.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"33 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79546641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338432
Amr Lotfy, Syed Feruz Syed Farooq, Qi Wang, Soner Yaldiz, P. Mosalikanti, N. Kurd
This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The proposed model exploits the sampled nature of the PLL where most of its analog behavior takes effect during the phase detection, and remains almost constant during the rest of the reference cycle. The PLL model simulation run time takes only 1 second, which makes it a perfect fit for pre-silicon digital validation as well as top-down design methodology. Compared to transistor-level Spice simulations, the proposed model shows a correlation of more than 97% for the PLL locking behavior, jitter, and phase noise. The PLL model is used to exercise critical features like spread-spectrum clocking (SSC) and adaptive frequency system (AFS). In addition, the model was integrated in a pre-silicon validation environment and enabled catching design bugs.
{"title":"A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology","authors":"Amr Lotfy, Syed Feruz Syed Farooq, Qi Wang, Soner Yaldiz, P. Mosalikanti, N. Kurd","doi":"10.1109/CICC.2015.7338432","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338432","url":null,"abstract":"This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The proposed model exploits the sampled nature of the PLL where most of its analog behavior takes effect during the phase detection, and remains almost constant during the rest of the reference cycle. The PLL model simulation run time takes only 1 second, which makes it a perfect fit for pre-silicon digital validation as well as top-down design methodology. Compared to transistor-level Spice simulations, the proposed model shows a correlation of more than 97% for the PLL locking behavior, jitter, and phase noise. The PLL model is used to exercise critical features like spread-spectrum clocking (SSC) and adaptive frequency system (AFS). In addition, the model was integrated in a pre-silicon validation environment and enabled catching design bugs.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77973082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338380
Jeffrey Fredenburg, M. Flynn
The performance of ADCs continues to improve with process scaling. For low to moderate resolutions, SAR ADCs deliver the best energy efficiency. Interleaved SAR converters have become popular for very high sampling speeds. The SAR assisted scheme has dramatically improved the energy efficiency of higher resolution pipeline ADCs. This paper reviews the fundamental limits of the energy efficiency of the SAR architecture, considering the energy consumption of the capacitor array and of the comparator. ADCs. ADC yield as a function of capacitor matching is also considered.
{"title":"ADC trends and impact on SAR ADC architecture and analysis","authors":"Jeffrey Fredenburg, M. Flynn","doi":"10.1109/CICC.2015.7338380","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338380","url":null,"abstract":"The performance of ADCs continues to improve with process scaling. For low to moderate resolutions, SAR ADCs deliver the best energy efficiency. Interleaved SAR converters have become popular for very high sampling speeds. The SAR assisted scheme has dramatically improved the energy efficiency of higher resolution pipeline ADCs. This paper reviews the fundamental limits of the energy efficiency of the SAR architecture, considering the energy consumption of the capacitor array and of the comparator. ADCs. ADC yield as a function of capacitor matching is also considered.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"118 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77993178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338398
D. Sadana, C. Cheng, B. Wacaser, W. Spratt, K. Shiu, S. Bedell
This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost reduction, scalability with Si wafer diameter, and accessibility to highly scaled integrated circuits next to III-V devices. With the current focus on CMOS the pace of progress on monolithic integration has accelerated by leaps and bounds partly because of its vast impact on CMOS scaling, and partly due to the aggressive CMOS roadmap requirements. The discussion below concentrates on In0.53Ga0.47As channel which is the dominant III-V material being pursued for future technology. Despite the narrow focus, fundamental and engineering challenges posed by this material encompass a broad range of material topics including epitaxial growth, crystallographic defects and their dynamics during growth and subsequent processing, clever device architecture to alleviate adverse impact of defects on device leakage, and innovative engineering for material improvement.
{"title":"Materials challenges for III-V/Si co-integrated CMOS","authors":"D. Sadana, C. Cheng, B. Wacaser, W. Spratt, K. Shiu, S. Bedell","doi":"10.1109/CICC.2015.7338398","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338398","url":null,"abstract":"This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost reduction, scalability with Si wafer diameter, and accessibility to highly scaled integrated circuits next to III-V devices. With the current focus on CMOS the pace of progress on monolithic integration has accelerated by leaps and bounds partly because of its vast impact on CMOS scaling, and partly due to the aggressive CMOS roadmap requirements. The discussion below concentrates on In0.53Ga0.47As channel which is the dominant III-V material being pursued for future technology. Despite the narrow focus, fundamental and engineering challenges posed by this material encompass a broad range of material topics including epitaxial growth, crystallographic defects and their dynamics during growth and subsequent processing, clever device architecture to alleviate adverse impact of defects on device leakage, and innovative engineering for material improvement.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"22 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73180986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338367
F. Hsiao, A. Tang, Y. Kim, B. Drouin, G. Chattopadhyay, Mau-Chung Frank Chang
The paper presents a 2.2 GS/s (1.1 GHz Nyquist bandwidth), 188 mW 512-channel spectrometer processor developed to support of future science observations on NASA planetary missions, where payload size, weight, and power consumption are extremely limited. The presented spectrometer processor chip contains a pair of 7 bit ADC IQ converters coupled with a 512 point PSD processor, and averaging accumulator, allowing it to be sensitive enough to detect trace gases like NH3, HCN, and CO2 when coupled to the appropriate band RF front-end receiver. The bandwidth and resolution of the presented processor make it suitable for exploring the composition of planets, moons and their atmospheres throughout our solar system.
{"title":"A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments","authors":"F. Hsiao, A. Tang, Y. Kim, B. Drouin, G. Chattopadhyay, Mau-Chung Frank Chang","doi":"10.1109/CICC.2015.7338367","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338367","url":null,"abstract":"The paper presents a 2.2 GS/s (1.1 GHz Nyquist bandwidth), 188 mW 512-channel spectrometer processor developed to support of future science observations on NASA planetary missions, where payload size, weight, and power consumption are extremely limited. The presented spectrometer processor chip contains a pair of 7 bit ADC IQ converters coupled with a 512 point PSD processor, and averaging accumulator, allowing it to be sensitive enough to detect trace gases like NH3, HCN, and CO2 when coupled to the appropriate band RF front-end receiver. The bandwidth and resolution of the presented processor make it suitable for exploring the composition of planets, moons and their atmospheres throughout our solar system.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"17 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86644229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338448
B. Erbagci, N. E. C. Akkaya, Craig Teegarden, K. Mai
The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27°C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.
{"title":"A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm","authors":"B. Erbagci, N. E. C. Akkaya, Craig Teegarden, K. Mai","doi":"10.1109/CICC.2015.7338448","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338448","url":null,"abstract":"The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27°C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89731089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338443
Derui Kong, Sang Min Lee, S. M. Taleie, M. J. McGowan, Dongwon Seo
A transconductance amplifier with extended bandwidth, which is a critical block in various applications including amplifiers, filters and DACs, is presented. The presented technique introduces a differential-mode negative capacitance while introduces the common-mode positive capacitance such that it extends the differential-mode bandwidth and compensates the common-mode stability. The proposed transconductance amplifier has been implemented for a DAC in CMOS 20nm to improve the distortion performance as a negative transconductance circuit, but the proposed technique is applicable to the wide range of circuits with a transconductor.
{"title":"A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensation","authors":"Derui Kong, Sang Min Lee, S. M. Taleie, M. J. McGowan, Dongwon Seo","doi":"10.1109/CICC.2015.7338443","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338443","url":null,"abstract":"A transconductance amplifier with extended bandwidth, which is a critical block in various applications including amplifiers, filters and DACs, is presented. The presented technique introduces a differential-mode negative capacitance while introduces the common-mode positive capacitance such that it extends the differential-mode bandwidth and compensates the common-mode stability. The proposed transconductance amplifier has been implemented for a DAC in CMOS 20nm to improve the distortion performance as a negative transconductance circuit, but the proposed technique is applicable to the wide range of circuits with a transconductor.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"14 8","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91427268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338434
C. R. Chappidi, K. Sengupta
Impedance transformation using on-chip passive elements is ubiquitously used in RF and mm-Wave circuits and systems for optimal power matching, interstage and noise matching, and high-efficiency power delivery to the antenna by power amplifiers. While conjugate matching gives optimal efficiency for lossless passives, the results are markedly different when constituent passives have finite quality factors. Given the load and source impedances, there may be infinite ways to achieve the transformation, albeit each incurring different loss. In this paper, we investigate the methods to deduce the global maximum efficiency of power transfer between two arbitrary impedances with lossy passives. This paper also proposes methods to combine this with nonlinear load-pull simulations for optimal efficiency combiner and matching network for integrated PAs. To the best of the authors' knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives.
{"title":"Methods for finding globally maximum-efficiency impedance matching networks with lossy passives","authors":"C. R. Chappidi, K. Sengupta","doi":"10.1109/CICC.2015.7338434","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338434","url":null,"abstract":"Impedance transformation using on-chip passive elements is ubiquitously used in RF and mm-Wave circuits and systems for optimal power matching, interstage and noise matching, and high-efficiency power delivery to the antenna by power amplifiers. While conjugate matching gives optimal efficiency for lossless passives, the results are markedly different when constituent passives have finite quality factors. Given the load and source impedances, there may be infinite ways to achieve the transformation, albeit each incurring different loss. In this paper, we investigate the methods to deduce the global maximum efficiency of power transfer between two arbitrary impedances with lossy passives. This paper also proposes methods to combine this with nonlinear load-pull simulations for optimal efficiency combiner and matching network for integrated PAs. To the best of the authors' knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"85 3 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81349569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338374
Hyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae
An on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) for background adaptive equalization is presented. The proposed SSEOM detects the BER-related eye opening area accurately with a feasible degree of time/area efficiency without an external microcontroller. In addition, the SSEOM determines the BER-optimal equalization parameters for both CTLE and DFE by incorporating a pattern-dependent eye-tracking scheme. Auxiliary data samplers are employed in parallel with data samplers to track link variations and adjust the equalization parameters in the background. A 28-Gb/s CDR including a SSEOM-based adaptive equalizer is fabricated in 40nm CMOS for an evaluation.
{"title":"An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization","authors":"Hyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae","doi":"10.1109/CICC.2015.7338374","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338374","url":null,"abstract":"An on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) for background adaptive equalization is presented. The proposed SSEOM detects the BER-related eye opening area accurately with a feasible degree of time/area efficiency without an external microcontroller. In addition, the SSEOM determines the BER-optimal equalization parameters for both CTLE and DFE by incorporating a pattern-dependent eye-tracking scheme. Auxiliary data samplers are employed in parallel with data samplers to track link variations and adjust the equalization parameters in the background. A 28-Gb/s CDR including a SSEOM-based adaptive equalizer is fabricated in 40nm CMOS for an evaluation.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"194 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77942588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338369
Jinghua Yang, Joseph Davis, Niranjan S. Kulkarni, Jae-sun Seo, S. Vrudhula
This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.
{"title":"Dynamic and leakage power reduction of ASICs using configurable threshold logic gates","authors":"Jinghua Yang, Joseph Davis, Niranjan S. Kulkarni, Jae-sun Seo, S. Vrudhula","doi":"10.1109/CICC.2015.7338369","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338369","url":null,"abstract":"This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88807993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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