Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338362
Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang
This paper presents a highly linear dual-band mixed-mode polar power amplifier fully integrated in a standard 65nm bulk CMOS process. An ultra-compact single-transformer passive network provides dual-band optimum load-pull impedance matching, parallel power combining, and double even-harmonic rejection without any tunable element or band selection switch. The mixed-mode architecture leverages both digital and analog techniques to suppress the AM-AM and AM-PM distortions and achieves high linearity. As a proof-of-concept design, the dual-band mixed-mode polar power amplifier is implemented in a 65nm CMOS process. We demonstrate the peak output power of +28.1dBm/+26.0dBm with the PA drain efficiency of 40.7%/27.0% at 2.6/4.5GHz. Measurement with 1MSym/s 256-QAM signal achieves rms EVM of 2.05%/1.03% with the average output power of +21.51dBm/+19.27dBm at 2.35/4.7GHz. The measured 2nd-harmonic rejection for the 2.35GHz signal is 37.7dB.
{"title":"A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network","authors":"Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang","doi":"10.1109/CICC.2015.7338362","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338362","url":null,"abstract":"This paper presents a highly linear dual-band mixed-mode polar power amplifier fully integrated in a standard 65nm bulk CMOS process. An ultra-compact single-transformer passive network provides dual-band optimum load-pull impedance matching, parallel power combining, and double even-harmonic rejection without any tunable element or band selection switch. The mixed-mode architecture leverages both digital and analog techniques to suppress the AM-AM and AM-PM distortions and achieves high linearity. As a proof-of-concept design, the dual-band mixed-mode polar power amplifier is implemented in a 65nm CMOS process. We demonstrate the peak output power of +28.1dBm/+26.0dBm with the PA drain efficiency of 40.7%/27.0% at 2.6/4.5GHz. Measurement with 1MSym/s 256-QAM signal achieves rms EVM of 2.05%/1.03% with the average output power of +21.51dBm/+19.27dBm at 2.35/4.7GHz. The measured 2nd-harmonic rejection for the 2.35GHz signal is 37.7dB.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85572978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338385
Jie Fang, S. Thirunakkarasu, Xuefeng Yu, F. Silva-Rivas, Kwang Young Kim, Chaoming Zhang, Frank W. Singor
This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for sampling network, comparator and highspeed reference buffer are illustrated to achieve a high-efficient ADC. The scheme for the reference voltages optimizes the input of comparator to reduce decision errors during LSB conversion cycles. Gain and offset mismatches are corrected by a digital background calibration. Timing-skew mismatches are estimated offline, then calibrated by the programmable delay of the sampling clock. The ADC achieves 49dB SNR, 52dB THD and 42dB SNDR up to Nyquist frequency at 5GS/s, consumes 76mW from 1V supply, and occupies 0.57mm2 in 28nm CMOS technology.
{"title":"A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS","authors":"Jie Fang, S. Thirunakkarasu, Xuefeng Yu, F. Silva-Rivas, Kwang Young Kim, Chaoming Zhang, Frank W. Singor","doi":"10.1109/CICC.2015.7338385","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338385","url":null,"abstract":"This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for sampling network, comparator and highspeed reference buffer are illustrated to achieve a high-efficient ADC. The scheme for the reference voltages optimizes the input of comparator to reduce decision errors during LSB conversion cycles. Gain and offset mismatches are corrected by a digital background calibration. Timing-skew mismatches are estimated offline, then calibrated by the programmable delay of the sampling clock. The ADC achieves 49dB SNR, 52dB THD and 42dB SNDR up to Nyquist frequency at 5GS/s, consumes 76mW from 1V supply, and occupies 0.57mm2 in 28nm CMOS technology.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"13 2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86827037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338399
N. Kolias
GaN MMIC technology is now in production and is revolutionizing microwave Radar and Communication systems. In this paper we present an overview of GaN MMIC technology, focusing on device characteristics, reliability, and high frequency performance. We also introduce emerging GaN technologies such as GaN-on-diamond and the heterogeneous integration of GaN with Silicon.
GaN MMIC技术现已投入生产，正在彻底改变微波雷达和通信系统。在本文中，我们介绍了GaN MMIC技术的概述，重点是器件特性，可靠性和高频性能。我们还介绍了新兴的氮化镓技术，如金刚石上的氮化镓和氮化镓与硅的异质集成。
{"title":"Recent advances in Ga N MMIC technology","authors":"N. Kolias","doi":"10.1109/CICC.2015.7338399","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338399","url":null,"abstract":"GaN MMIC technology is now in production and is revolutionizing microwave Radar and Communication systems. In this paper we present an overview of GaN MMIC technology, focusing on device characteristics, reliability, and high frequency performance. We also introduce emerging GaN technologies such as GaN-on-diamond and the heterogeneous integration of GaN with Silicon.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 6","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91475808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338427
Yu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, K. Hsieh, Tung-Tsun Chen
This paper presents a high-gain and large-scale CMOS ion-sensitive field effect transistor (ISFET) sensor. The high-gain readout is achieved by a novel pH-to-Time-to-Voltage conversion (pH-TVC), which can greatly increase pixel density (small pixel size) with a high sensitivity. The proposed pH sensor consists of 512×576 pixel array with 3.9um×3.9um chemical sensing area, and is integrated with column-paralleled 10-bit single-slope ADCs to speed up data readout. It is fabricated in traditional TSMC 65nm process with 201mV/pH sensitivity and 375 fps readout speed, targeted for DNA sequencing.
{"title":"A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology","authors":"Yu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, K. Hsieh, Tung-Tsun Chen","doi":"10.1109/CICC.2015.7338427","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338427","url":null,"abstract":"This paper presents a high-gain and large-scale CMOS ion-sensitive field effect transistor (ISFET) sensor. The high-gain readout is achieved by a novel pH-to-Time-to-Voltage conversion (pH-TVC), which can greatly increase pixel density (small pixel size) with a high sensitivity. The proposed pH sensor consists of 512×576 pixel array with 3.9um×3.9um chemical sensing area, and is integrated with column-paralleled 10-bit single-slope ADCs to speed up data readout. It is fabricated in traditional TSMC 65nm process with 201mV/pH sensitivity and 375 fps readout speed, targeted for DNA sequencing.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84806768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338366
V. Vashishtha, L. Clark, S. Chellappa, Anudeep R. Gogulamudi, A. Gujja, Chad Farnsworth
An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.
{"title":"A soft-error hardened process portable embedded microprocessor","authors":"V. Vashishtha, L. Clark, S. Chellappa, Anudeep R. Gogulamudi, A. Gujja, Chad Farnsworth","doi":"10.1109/CICC.2015.7338366","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338366","url":null,"abstract":"An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"79 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84119642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338433
Zhimiao Chen, Zhixing Liu, Lei Liao, R. Wunderlich, S. Heinen
This paper introduces a mixed domain event-driven modeling method for RF systems. The circuit behaviors are modeled in time/frequency domain adaptively combining with the equivalent baseband representation of each spectral component. Comparing to traditional baseband modeling methods or harmonic balance simulation techniques, this mixed domain method loose the requirements of relations among carrier frequencies of spectral components, and therefore can be widely used in mixed-signal circuit modeling. Furthermore, this method brings in a great simulation speed up over the simulation in passband signal abstraction, while the modeling accuracy can be guaranteed to meet the requirements of functional verifications.
{"title":"A mixed-domain modeling method for RF systems","authors":"Zhimiao Chen, Zhixing Liu, Lei Liao, R. Wunderlich, S. Heinen","doi":"10.1109/CICC.2015.7338433","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338433","url":null,"abstract":"This paper introduces a mixed domain event-driven modeling method for RF systems. The circuit behaviors are modeled in time/frequency domain adaptively combining with the equivalent baseband representation of each spectral component. Comparing to traditional baseband modeling methods or harmonic balance simulation techniques, this mixed domain method loose the requirements of relations among carrier frequencies of spectral components, and therefore can be widely used in mixed-signal circuit modeling. Furthermore, this method brings in a great simulation speed up over the simulation in passband signal abstraction, while the modeling accuracy can be guaranteed to meet the requirements of functional verifications.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84400545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338424
R. Harjani, Rakesh Kumar Palani
The design of differential pair based OTAs is becoming increasingly difficult in finer geometries due to lower supply voltages. Inverter based designs have proven to have better transconductance efficiency, higher swing and better linearity but have degraded CMRR, worse PSRR and limited PVT tolerance. In this tutorial, we discuss traditional amplifiers and why inverter based amplifiers are better suited for lower supplies. We then describe the design procedure for inverter based OTA designs with an emphasis on improving their performance, including PVT tolerance, CMRR and PSRR. In particular, we introduce new biasing techniques for inverters to improve their PVT tolerance. We finally validate our designs using measurement results from a number of fabricated designs.
{"title":"Design of PVT tolerant inverter based circuits for low supply voltages","authors":"R. Harjani, Rakesh Kumar Palani","doi":"10.1109/CICC.2015.7338424","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338424","url":null,"abstract":"The design of differential pair based OTAs is becoming increasingly difficult in finer geometries due to lower supply voltages. Inverter based designs have proven to have better transconductance efficiency, higher swing and better linearity but have degraded CMRR, worse PSRR and limited PVT tolerance. In this tutorial, we discuss traditional amplifiers and why inverter based amplifiers are better suited for lower supplies. We then describe the design procedure for inverter based OTA designs with an emphasis on improving their performance, including PVT tolerance, CMRR and PSRR. In particular, we introduce new biasing techniques for inverters to improve their PVT tolerance. We finally validate our designs using measurement results from a number of fabricated designs.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"25 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86514013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338464
F. Dai, S. Sankaran
This session presents techniques for frequency locking and schemes for phase generation with full 2π coverage at RF/mm-wave frequencies.
本次会议介绍了频率锁定技术和在RF/毫米波频率下具有完全2π覆盖的相位产生方案。
{"title":"Session 4 — Frequency and phase generation techniques","authors":"F. Dai, S. Sankaran","doi":"10.1109/CICC.2015.7338464","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338464","url":null,"abstract":"This session presents techniques for frequency locking and schemes for phase generation with full 2π coverage at RF/mm-wave frequencies.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86614593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338480
Loai G. Salem, P. Mercier
This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, realizing the widest resonant operating range reported in CMOS. A frequency-scaled gear train SC topology is introduced that enables soft-charging of all flying capacitors through one inductor at any arbitrary binary ratio by eliminating the inter-stage decoupling required in prior-art. Gear ratio modulation is proposed to control the resonance Q-factor, and hence the regulator can be gracefully transitioned from a resonant converter to a fully-capacitive SC, enabling > 24,000x output current range. For the same footprint, the converter achieves up to 14.4% and 12% efficiency improvements over co-fabricated SC and 3-level buck converters, respectively, while operating with a peak efficiency of 73.3% and current density of 0.14 A/mm2 in 0.18 μm bulk.
本文演示了第一个仅使用单个电感的7比谐振开关电容(SC)变换器，实现了CMOS中报道的最宽谐振工作范围。介绍了一种频率缩放的齿轮系SC拓扑结构，通过消除现有技术所需的级间去耦，可以通过一个电感器以任意二进制比对所有飞行电容器进行软充电。提出了齿轮比调制来控制谐振q因子，因此调节器可以从谐振变换器优雅地过渡到全电容SC，实现> 24000倍输出电流范围。在相同的封装面积下，该变换器的效率比共制SC变换器和3电平降压变换器分别提高了14.4%和12%，同时在0.18 μm体积下的峰值效率为73.3%，电流密度为0.14 a /mm2。
{"title":"A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range","authors":"Loai G. Salem, P. Mercier","doi":"10.1109/CICC.2015.7338480","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338480","url":null,"abstract":"This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, realizing the widest resonant operating range reported in CMOS. A frequency-scaled gear train SC topology is introduced that enables soft-charging of all flying capacitors through one inductor at any arbitrary binary ratio by eliminating the inter-stage decoupling required in prior-art. Gear ratio modulation is proposed to control the resonance Q-factor, and hence the regulator can be gracefully transitioned from a resonant converter to a fully-capacitive SC, enabling > 24,000x output current range. For the same footprint, the converter achieves up to 14.4% and 12% efficiency improvements over co-fabricated SC and 3-level buck converters, respectively, while operating with a peak efficiency of 73.3% and current density of 0.14 A/mm2 in 0.18 μm bulk.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"30 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80547273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338400
F. Yazdani
Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct assembly of silicon interposer on PCB, resulting in reduced cost and increased performance for 2.5D/3D applications as well as wafer-level fan-out applications. We investigate effect of under-fill on solder joint reliability during direct assembly of silicon interposer on PCB. A 10×10mm2 interposer test vehicle was designed and fabricated on 310um thick rigid silicon substrate. BGA of side of the interposer was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50×50mm2 FR-4 PCB through a reflow process. We present cost analysis, design flow, and direct assembly of rigid silicon interposer on PCB. Effect of under-fill on the solder joint reliability is demonstrated using CSAM images during temperature cycles at 250, 500, 750 and 1000 intervals. It is shown that all samples successfully passed the temperature cycle stress test.
{"title":"A novel low cost, high performance and reliable silicon interposer","authors":"F. Yazdani","doi":"10.1109/CICC.2015.7338400","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338400","url":null,"abstract":"Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct assembly of silicon interposer on PCB, resulting in reduced cost and increased performance for 2.5D/3D applications as well as wafer-level fan-out applications. We investigate effect of under-fill on solder joint reliability during direct assembly of silicon interposer on PCB. A 10×10mm2 interposer test vehicle was designed and fabricated on 310um thick rigid silicon substrate. BGA of side of the interposer was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50×50mm2 FR-4 PCB through a reflow process. We present cost analysis, design flow, and direct assembly of rigid silicon interposer on PCB. Effect of under-fill on the solder joint reliability is demonstrated using CSAM images during temperature cycles at 250, 500, 750 and 1000 intervals. It is shown that all samples successfully passed the temperature cycle stress test.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"66 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73572647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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