Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338482
A. Hussein, Shadi Saberi, J. Paramesh
This paper presents a wide tuning range mm-wave digitally controlled oscillator (DCO) with very fine frequency tuning granularity. Switched coupled-inductor and switched-capacitor banks provide the coarse tuning to achieve 24% tuning range from 48.1 GHz to 61.3 GHz. A fine frequency tuning resolution of 39 kHz is achieved using capacitive degeneration. The 65 nm CMOS DCO consumes 10mA from 1V supply voltage, and the DCO with output shunt-peaking buffer occupy an active area of 0.0322mm2. The measured max/average/min phase noise at 1 MHz and 10MHz offset are -88.8/-91.9/-95.1dBc/Hz and -114/-116.8/-119.5dBc/Hz respectively. The figure-of-merit varies from -186.4dB to -182.2dB which is better than figure-of-merit of recent mm-wave DCO benchmarks.
{"title":"A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularity","authors":"A. Hussein, Shadi Saberi, J. Paramesh","doi":"10.1109/CICC.2015.7338482","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338482","url":null,"abstract":"This paper presents a wide tuning range mm-wave digitally controlled oscillator (DCO) with very fine frequency tuning granularity. Switched coupled-inductor and switched-capacitor banks provide the coarse tuning to achieve 24% tuning range from 48.1 GHz to 61.3 GHz. A fine frequency tuning resolution of 39 kHz is achieved using capacitive degeneration. The 65 nm CMOS DCO consumes 10mA from 1V supply voltage, and the DCO with output shunt-peaking buffer occupy an active area of 0.0322mm2. The measured max/average/min phase noise at 1 MHz and 10MHz offset are -88.8/-91.9/-95.1dBc/Hz and -114/-116.8/-119.5dBc/Hz respectively. The figure-of-merit varies from -186.4dB to -182.2dB which is better than figure-of-merit of recent mm-wave DCO benchmarks.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"32 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73122963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338379
P. Weckx, B. Kaczer, P. Raghavan, J. Franco, Marko Simicic, P. Roussel, D. Linten, A. Thean, D. Verkest, F. Catthoor, G. Groeseneken
This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.
{"title":"Characterization and simulation methodology for time-dependent variability in advanced technologies","authors":"P. Weckx, B. Kaczer, P. Raghavan, J. Franco, Marko Simicic, P. Roussel, D. Linten, A. Thean, D. Verkest, F. Catthoor, G. Groeseneken","doi":"10.1109/CICC.2015.7338379","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338379","url":null,"abstract":"This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"22 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74917488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338387
Zhidong Liu, Hoi Lee
A wide-input-range (5-115V) DC-DC based synchronous LED driver is presented in this paper. The proposed LED driver can automatically operate in the soft-switching mode to minimize the converter's switching loss in the HV condition. An adaptive resonate timing control (ARTC) is developed to generate optimal dead-time for establishing zero-voltage switching of both high- and low-side power FETs under different input and output voltages. Two high-speed HV body-diode-based zero-voltage detectors are also proposed to realize high-frequency soft switching. Implemented in a 0.5μm 120V CMOS process, the proposed LED driver can support up to 25 series-connected high-brightness LEDs. The LED driver can operate up to 1.6MHz and achieve a peak power efficiency of 94.4% in the soft-switching mode. Compared to the prior arts, the proposed LED driver is the first to demonstrate auto-configurable hard-and soft-switching capability by the ARTC to achieve high power efficiency and current accuracy over both widest ranges of the input voltage and the number of output LEDs.
{"title":"A 5–115V efficiency-enhanced synchronous LED driver with adaptive resonant timing control","authors":"Zhidong Liu, Hoi Lee","doi":"10.1109/CICC.2015.7338387","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338387","url":null,"abstract":"A wide-input-range (5-115V) DC-DC based synchronous LED driver is presented in this paper. The proposed LED driver can automatically operate in the soft-switching mode to minimize the converter's switching loss in the HV condition. An adaptive resonate timing control (ARTC) is developed to generate optimal dead-time for establishing zero-voltage switching of both high- and low-side power FETs under different input and output voltages. Two high-speed HV body-diode-based zero-voltage detectors are also proposed to realize high-frequency soft switching. Implemented in a 0.5μm 120V CMOS process, the proposed LED driver can support up to 25 series-connected high-brightness LEDs. The LED driver can operate up to 1.6MHz and achieve a peak power efficiency of 94.4% in the soft-switching mode. Compared to the prior arts, the proposed LED driver is the first to demonstrate auto-configurable hard-and soft-switching capability by the ARTC to achieve high power efficiency and current accuracy over both widest ranges of the input voltage and the number of output LEDs.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75020666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338453
Jianxun Zhu, P. Kinget
A field-programmable noise-canceling wide-band receiver front end with high performance LNTAs is presented. The common-source (CS) and common-gate (CG) LNTAs are split into several cells whose bias point can be individually programmed in class AB or C yielding a highly linear hybrid class-AB-C LNTA. The 40nm LP CMOS receiver prototype can be programmed on the fly to adapt to different RF environments; it was tested in a low noise mode, a high linearity mode and a low power mode. Across these modes, the receiver has maximum gain of 53dB, a minimum NF of 2.2dB, a maximum B1 dB of +11dBm, and a maximum OB-IIP3 of +21dBm; the signal path consumes between 15 and 40mA from a 2.5V supply and the LO current varies from 2.2 to 20mA from a 1.1V supply across operating frequencies. The measured LO emission at the antenna port is <;-84dBm.
{"title":"A field-programmable noise-canceling wideband receiver with high-linearity hybrid class-AB-C LNTAs","authors":"Jianxun Zhu, P. Kinget","doi":"10.1109/CICC.2015.7338453","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338453","url":null,"abstract":"A field-programmable noise-canceling wide-band receiver front end with high performance LNTAs is presented. The common-source (CS) and common-gate (CG) LNTAs are split into several cells whose bias point can be individually programmed in class AB or C yielding a highly linear hybrid class-AB-C LNTA. The 40nm LP CMOS receiver prototype can be programmed on the fly to adapt to different RF environments; it was tested in a low noise mode, a high linearity mode and a low power mode. Across these modes, the receiver has maximum gain of 53dB, a minimum NF of 2.2dB, a maximum B1 dB of +11dBm, and a maximum OB-IIP3 of +21dBm; the signal path consumes between 15 and 40mA from a 2.5V supply and the LO current varies from 2.2 to 20mA from a 1.1V supply across operating frequencies. The measured LO emission at the antenna port is <;-84dBm.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75283865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338364
S. Y. Mortazavi, Kwang-Jin Koh
This paper presents a 28 GHz class-F1 power amplifier in 0.13-μm SiGe BiCMOS technology. The PA adopts a coupled-inductor based harmonic impedance modulator in order to terminate 2nd and 3rd harmonic load impedances appropriately for class-F1 operation. The coupled coils essentially provide frequency-dependent inductance that is optimal to resonate out 2nd and 3rd harmonic reactive impedance. The PA achieve 40-42% PAE over 27.5 GHz to 29 GHz, peak 42% PAE at 28 GHz with 50 mW OP-1db power, one of the highest PAEs ever reported in silicon-based PAs. At 6-dB backoff output power, the PAE is as high as 20% Psat is 16.6 dBm. The PA occupies 0.55×0.96 mm2.
{"title":"A 28-GHz inverse class-F power amplifier with coupled-inductor based harmonic impedance modulator","authors":"S. Y. Mortazavi, Kwang-Jin Koh","doi":"10.1109/CICC.2015.7338364","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338364","url":null,"abstract":"This paper presents a 28 GHz class-F<sup>1</sup> power amplifier in 0.13-μm SiGe BiCMOS technology. The PA adopts a coupled-inductor based harmonic impedance modulator in order to terminate 2<sup>nd</sup> and 3<sup>rd</sup> harmonic load impedances appropriately for class-F<sup>1</sup> operation. The coupled coils essentially provide frequency-dependent inductance that is optimal to resonate out 2<sup>nd</sup> and 3<sup>rd</sup> harmonic reactive impedance. The PA achieve 40-42% PAE over 27.5 GHz to 29 GHz, peak 42% PAE at 28 GHz with 50 mW OP-1db power, one of the highest PAEs ever reported in silicon-based PAs. At 6-dB backoff output power, the PAE is as high as 20% Psat is 16.6 dBm. The PA occupies 0.55×0.96 mm<sup>2</sup>.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"75 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79198823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338357
Dong-Uk Lee, Kangseol Lee, Yong-jun Lee, Kyung Whan Kim, Jong Kang, Jaejin Lee, J. Chun
Recently, the 3D stacked memory, which is known as HBM (high bandwidth memory), using TSV process has been developed. The stacked memory structure provides increased bandwidth, low power consumption, as well as small form factor. There are many design challenges, such as multi-channel operation, microbump test and TSV connection scan. Various design methodology make it possible to overcome the difficulties in the development of TSV technology. Vertical stacking enables more diverse memory architecture than the flat architecture. The next generation of HBM focuses on not only the bandwidth but also the system performance enhancement by adopting pseudo channel and 8-Hi stacking. The architecture applied to the second generation HBM are introduced in this paper.
{"title":"Design considerations of HBM stacked DRAM and the memory architecture extension","authors":"Dong-Uk Lee, Kangseol Lee, Yong-jun Lee, Kyung Whan Kim, Jong Kang, Jaejin Lee, J. Chun","doi":"10.1109/CICC.2015.7338357","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338357","url":null,"abstract":"Recently, the 3D stacked memory, which is known as HBM (high bandwidth memory), using TSV process has been developed. The stacked memory structure provides increased bandwidth, low power consumption, as well as small form factor. There are many design challenges, such as multi-channel operation, microbump test and TSV connection scan. Various design methodology make it possible to overcome the difficulties in the development of TSV technology. Vertical stacking enables more diverse memory architecture than the flat architecture. The next generation of HBM focuses on not only the bandwidth but also the system performance enhancement by adopting pseudo channel and 8-Hi stacking. The architecture applied to the second generation HBM are introduced in this paper.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"58 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85818301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338492
Wenjuan Guo, Youngchun Kim, A. Tewfik, Nan Sun
Based on the recently emerging compressive sensing theory, the paper proposes an ultra-low power multichannel data conversion system whose architecture is almost as simple as a single SAR ADC. The proposed architecture is capable of simultaneously converting multi-channel sparse signals while running at the Nyquist rate of only one channel. A chip is fabricated in a 0.13μm CMOS process. Operating at 1MS/s, the SAR ADC itself achieves a 66dB SNDR and a 25fJ/step FoM at 0.8V. Using convex optimization methods, 4-channel 500kHz-bandwidth signals can be reconstructed with a 66dB peak SNDR and a 41% max occupancy, leading to an effective FoM per channel of 6.25 fJ/step.
基于近年来新兴的压缩感知理论，提出了一种超低功耗多通道数据转换系统，其结构几乎与单个SAR ADC一样简单。该架构能够在仅以一个信道的奈奎斯特速率运行的情况下同时转换多信道稀疏信号。该芯片采用0.13μm CMOS工艺制备。工作速度为1MS/s, SAR ADC本身在0.8V下实现66dB SNDR和25fJ/step FoM。采用凸优化方法，重构4通道500khz带宽信号，峰值SNDR为66dB，最大占用率为41%，每通道有效FoM为6.25 fJ/步。
{"title":"Ultra-low power multi-channel data conversion with a single SAR ADC for mobile sensing applications","authors":"Wenjuan Guo, Youngchun Kim, A. Tewfik, Nan Sun","doi":"10.1109/CICC.2015.7338492","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338492","url":null,"abstract":"Based on the recently emerging compressive sensing theory, the paper proposes an ultra-low power multichannel data conversion system whose architecture is almost as simple as a single SAR ADC. The proposed architecture is capable of simultaneously converting multi-channel sparse signals while running at the Nyquist rate of only one channel. A chip is fabricated in a 0.13μm CMOS process. Operating at 1MS/s, the SAR ADC itself achieves a 66dB SNDR and a 25fJ/step FoM at 0.8V. Using convex optimization methods, 4-channel 500kHz-bandwidth signals can be reconstructed with a 66dB peak SNDR and a 41% max occupancy, leading to an effective FoM per channel of 6.25 fJ/step.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82452969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338489
Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee
An ultra-low power and wide tuning range LC-VCO is presented, where the performances are improved by identifying and avoiding the Q-factor degradation factors in the LC-tank. By the positioning analysis and adoption of MIM capacitor arrays along with minimum size varactors, the proposed VCO with a high-Q inductor, implemented in a 65-nm CMOS technology, operates from 2.35GHz to 2.64GHz (11.7% tuning) with phase noise of -132.92 dBc/Hz at 1MHz offset while dissipating only 72μW from a 0.6-V supply. The FoM of the proposed VCO is 212dBc/Hz and the widest tuning range is shown in the high-Q oscillators.
{"title":"A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS","authors":"Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee","doi":"10.1109/CICC.2015.7338489","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338489","url":null,"abstract":"An ultra-low power and wide tuning range LC-VCO is presented, where the performances are improved by identifying and avoiding the Q-factor degradation factors in the LC-tank. By the positioning analysis and adoption of MIM capacitor arrays along with minimum size varactors, the proposed VCO with a high-Q inductor, implemented in a 65-nm CMOS technology, operates from 2.35GHz to 2.64GHz (11.7% tuning) with phase noise of -132.92 dBc/Hz at 1MHz offset while dissipating only 72μW from a 0.6-V supply. The FoM of the proposed VCO is 212dBc/Hz and the widest tuning range is shown in the high-Q oscillators.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87023164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338429
Vahid Behravan, S. Li, Neil E. Glover, Chia-Hung Chen, M. Shoaib, G. Temes, P. Chiang
Reconstructing signals accurately is a critical aspect of compressed sensing. We propose a compressed-sensing sensor-on-chip that compresses and also extracts key statistics of the input signal at sampling time. These statistics can be used at the receiver to significantly improve the accuracy of reconstruction. When compared against a conventional compressed-sensing system, our experimental measured results demonstrate an improvement of as much as 9-18 dB in the signal-to-error (SER) of the reconstructed signal, depending on input data type and compression factor.
{"title":"A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance","authors":"Vahid Behravan, S. Li, Neil E. Glover, Chia-Hung Chen, M. Shoaib, G. Temes, P. Chiang","doi":"10.1109/CICC.2015.7338429","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338429","url":null,"abstract":"Reconstructing signals accurately is a critical aspect of compressed sensing. We propose a compressed-sensing sensor-on-chip that compresses and also extracts key statistics of the input signal at sampling time. These statistics can be used at the receiver to significantly improve the accuracy of reconstruction. When compared against a conventional compressed-sensing system, our experimental measured results demonstrate an improvement of as much as 9-18 dB in the signal-to-error (SER) of the reconstructed signal, depending on input data type and compression factor.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86271469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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