This paper describes a dual-band 802.11abgn/ac compliant transceiver in a 4-in-l combo connectivity SoC. It integrates the PAs, LNAs, T/R switches, and the 5GHz Balun. Due to the transmitter architecture and adaptive biasing scheme both are tailored for wide bandwidth, the 5GHz transmitter achieves 18.2dBm average output power for 802.11ac VHT80 MCS9 (Modulation and Coding Scheme 9). Within the 80MHz channel bandwidth, the IQ mismatch becomes frequency dependent, and is compensated through calibration. In the 2.4GHz transmitter, its PA load-line is adjustable. The power efficiency is thus remained similarly regardless the output power is at 20dBm for long range operation, or 8dBm for short range operation. By controlling the turn-on resistance of power island switch in digital baseband, and properly sizing the filler cap, the switching noise can be well controlled. The chip occupies 24.9mm2 in 55nm 1P6M CMOS technology, where 1.3mm2 is for 5GHz WLAN and 2.1mm2 is for 2.4GHz WLAN/BT.
{"title":"A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC","authors":"Y. Chung, Che-Hung Liao, Chun-Wei Lin, Y. Shih, Chin-Fu Li, Meng-Hsiung Hung, Mingchung Liu, Pi-An Wu, Jui-Lin Hsu, Ming-Yeh Hsu, Sheng-Hao Chen, Po-Yu Chang, Chih-Hao Chen, Yu-Hsien Chang, Jun-Yu Chen, Tao-Yao Chang, G. Chien","doi":"10.1109/CICC.2015.7338361","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338361","url":null,"abstract":"This paper describes a dual-band 802.11abgn/ac compliant transceiver in a 4-in-l combo connectivity SoC. It integrates the PAs, LNAs, T/R switches, and the 5GHz Balun. Due to the transmitter architecture and adaptive biasing scheme both are tailored for wide bandwidth, the 5GHz transmitter achieves 18.2dBm average output power for 802.11ac VHT80 MCS9 (Modulation and Coding Scheme 9). Within the 80MHz channel bandwidth, the IQ mismatch becomes frequency dependent, and is compensated through calibration. In the 2.4GHz transmitter, its PA load-line is adjustable. The power efficiency is thus remained similarly regardless the output power is at 20dBm for long range operation, or 8dBm for short range operation. By controlling the turn-on resistance of power island switch in digital baseband, and properly sizing the filler cap, the switching noise can be well controlled. The chip occupies 24.9mm2 in 55nm 1P6M CMOS technology, where 1.3mm2 is for 5GHz WLAN and 2.1mm2 is for 2.4GHz WLAN/BT.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"36 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77067844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338488
Chundong Wu, W. Goh, C. Kok, Wanlan Yang, L. Siek
This paper presents a 10-μA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature. Based on the proposed structure, a 130 ppm/°C temperature coefficient current reference across -40°C to 80°C temperature range is achieved. The proposed circuit can work at supply voltage varying from 2.4 to 3.0 V, while only has 30-nA drift at room temperature. The proposed current reference is implemented in 0.18-μm CMOS process occupying an area of 0.005 mm2.
{"title":"A low TC, supply independent and process compensated current reference","authors":"Chundong Wu, W. Goh, C. Kok, Wanlan Yang, L. Siek","doi":"10.1109/CICC.2015.7338488","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338488","url":null,"abstract":"This paper presents a 10-μA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature. Based on the proposed structure, a 130 ppm/°C temperature coefficient current reference across -40°C to 80°C temperature range is achieved. The proposed circuit can work at supply voltage varying from 2.4 to 3.0 V, while only has 30-nA drift at room temperature. The proposed current reference is implemented in 0.18-μm CMOS process occupying an area of 0.005 mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82278661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338487
Ahmad Sharkia, S. Aniruddhan, S. Shekhar, S. Mirabbasi
Analog Type-II phase-locked loops (PLLs) consume large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pump (CP). All-digital PLLs have strict jitter requirements on time-to-digital converters (TDCs). We propose a Type-I PLL that consumes small LF area, requires no bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies - limited lock-range and large reference spur - are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and further improve the lock-range and lock-time. A prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm2 in 0.13-um CMOS and achieves 490 fsrms random jitter, -103.4 dBc/Hz in-band phase noise, -65 dBc reference spur, 2.5 (is worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.
{"title":"A high-performance, yet simple to design, digital-friendly type-I PLL","authors":"Ahmad Sharkia, S. Aniruddhan, S. Shekhar, S. Mirabbasi","doi":"10.1109/CICC.2015.7338487","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338487","url":null,"abstract":"Analog Type-II phase-locked loops (PLLs) consume large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pump (CP). All-digital PLLs have strict jitter requirements on time-to-digital converters (TDCs). We propose a Type-I PLL that consumes small LF area, requires no bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies - limited lock-range and large reference spur - are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and further improve the lock-range and lock-time. A prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm2 in 0.13-um CMOS and achieves 490 fsrms random jitter, -103.4 dBc/Hz in-band phase noise, -65 dBc reference spur, 2.5 (is worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86863257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338368
Jeffrey Tyhach, M. Hutton, Sean Atsatt, Arifur Rahman, B. Vest, D. Lewis, M. Langhammer, Sergey Shumarayev, T. Hoang, Allen Chan, D. Choi, D. Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, B. Ang
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.
本文介绍了基于台积电20SOC工艺的高密度FPGA系列Arria 10的架构。该器件的设计包括一个嵌入式双核1.5 GHz ARM A9子系统和外设，超过1M个逻辑元件(LEs)和1.7M用户触发器，以及64Mb的嵌入式内存组织成可配置的内存块。Arria 10系列也是第一个包含强化单精度IEEE 754浮点数的主流FPGA系列，总吞吐量为1.3 TFLOPs。设备I/O由28G可编程收发器组成，具有增强的PMA架构强化的PCIe子块和强化的DDR外部存储器控制器。采用数字辅助模拟校准的新方法来解决工艺变化问题。该结构针对28纳米fpga进行了优化，可大幅减小芯片尺寸和提高功耗，包括用于微重定时的借时ff、用于改善可达性的三状态长线、实验室集群粒度的可编程反向偏置以及用于平衡整个工艺分布的泄漏和性能的Smart-VID等电源管理功能。
{"title":"Arria™ 10 device architecture","authors":"Jeffrey Tyhach, M. Hutton, Sean Atsatt, Arifur Rahman, B. Vest, D. Lewis, M. Langhammer, Sergey Shumarayev, T. Hoang, Allen Chan, D. Choi, D. Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, B. Ang","doi":"10.1109/CICC.2015.7338368","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338368","url":null,"abstract":"This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"64 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86086038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338460
A. Nguyen, Jian Xu, Zhi Yang
This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μm×620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.
{"title":"A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording","authors":"A. Nguyen, Jian Xu, Zhi Yang","doi":"10.1109/CICC.2015.7338460","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338460","url":null,"abstract":"This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μm×620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4-6 times, respectively.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83048482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338410
A. Niknejad, S. V. Thyagarajan, E. Alon, Yanjie Wang, C. Hull
The fourth generation mobile phone standards (4G) in widespread use include Long Term Evolution (LTE) and LTE-A (Advanced), which support up to 44 bands internationally, or an aggregate bandwidth of about 1 GHz in TDD and FDD modes. Techniques such as carrier aggregation allow the mobile operator to maximize bandwidth and deliver high data rate to users. As demand for wireless connectivity continues to grow exponentially, a fifth generation (5G) standard is envisioned, with the requirement to deliver higher throughputs, more spectrum-particularly in the mm-wave bands-higher capacity through spatial diversity, and lower latency. The projected deployment date of 5G is in 2019, and various proposals are under consideration. This paper will highlight important implications for the design of transceivers for 5G, particularly those targeting the mm-wave bands.
目前广泛使用的第四代移动电话标准(4G)包括LTE (Long Term Evolution)和LTE- a (Advanced)，在国际上支持多达44个频段，在TDD和FDD模式下，总带宽约为1ghz。载波聚合等技术允许移动运营商最大化带宽并向用户提供高数据速率。随着对无线连接的需求持续呈指数级增长，人们设想了第五代(5G)标准，要求提供更高的吞吐量、更多的频谱(特别是在毫米波频段)、通过空间多样性提供更高的容量和更低的延迟。预计5G的部署日期是2019年，目前正在考虑各种提案。本文将重点介绍5G收发器设计的重要意义，特别是针对毫米波频段的收发器设计。
{"title":"A circuit designer's guide to 5G mm-wave","authors":"A. Niknejad, S. V. Thyagarajan, E. Alon, Yanjie Wang, C. Hull","doi":"10.1109/CICC.2015.7338410","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338410","url":null,"abstract":"The fourth generation mobile phone standards (4G) in widespread use include Long Term Evolution (LTE) and LTE-A (Advanced), which support up to 44 bands internationally, or an aggregate bandwidth of about 1 GHz in TDD and FDD modes. Techniques such as carrier aggregation allow the mobile operator to maximize bandwidth and deliver high data rate to users. As demand for wireless connectivity continues to grow exponentially, a fifth generation (5G) standard is envisioned, with the requirement to deliver higher throughputs, more spectrum-particularly in the mm-wave bands-higher capacity through spatial diversity, and lower latency. The projected deployment date of 5G is in 2019, and various proposals are under consideration. This paper will highlight important implications for the design of transceivers for 5G, particularly those targeting the mm-wave bands.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"3 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83821702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338479
Pavan Kumar, V. Vaidya, H. Krishnamurthy, Stephen T. Kim, G. Matthew, Sheldon Weng, Bharani Thiruvengadam, W. Proefrock, K. Ravichandran, V. De
Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range Dynamic Voltage & Frequency Scaling (DVFS) over traditional solutions like linear regulators & Buck VRs are demonstrated.
{"title":"A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS","authors":"Pavan Kumar, V. Vaidya, H. Krishnamurthy, Stephen T. Kim, G. Matthew, Sheldon Weng, Bharani Thiruvengadam, W. Proefrock, K. Ravichandran, V. De","doi":"10.1109/CICC.2015.7338479","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338479","url":null,"abstract":"Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range Dynamic Voltage & Frequency Scaling (DVFS) over traditional solutions like linear regulators & Buck VRs are demonstrated.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"124 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77291536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338483
Sungmin Ock, Hyejeong Song, R. Gharpurey
A transmitter architecture based on Cartesian feedback-feedforward is described. A Cartesian feedback loop is used to linearize a transmitter and PA, and the error signal is utilized in a feedforward path to further enhance linearity. A proof-of-concept prototype transmitter IC that is used to linearize an external PA is demonstrated in a 130nm CMOS process. The implementation allows for a 8.7 dB ACLR improvement, compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16 QAM LTE signal with 1.4 MHz bandwidth.
{"title":"A Cartesian feedback-feedforward transmitter IC in 130nm CMOS","authors":"Sungmin Ock, Hyejeong Song, R. Gharpurey","doi":"10.1109/CICC.2015.7338483","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338483","url":null,"abstract":"A transmitter architecture based on Cartesian feedback-feedforward is described. A Cartesian feedback loop is used to linearize a transmitter and PA, and the error signal is utilized in a feedforward path to further enhance linearity. A proof-of-concept prototype transmitter IC that is used to linearize an external PA is demonstrated in a 130nm CMOS process. The implementation allows for a 8.7 dB ACLR improvement, compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16 QAM LTE signal with 1.4 MHz bandwidth.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78009668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338446
Raveesh Magod, Naveen Suda, V. Ivanov, Ravi Balasingam, B. Bakkaloglu
Achieving low noise is becoming an important requirement in linear supply regulators for RF and mixed-signal SoC applications. A low-noise, low dropout regulator using switched-RC bandgap reference and a multi-loop, unconditionally stable error amplifier for output capacitor-less operation is presented. Switched-RC sample-and-hold filtered bandgap reference and current-mode chopped error amplifier techniques are used for reducing output noise of the LDO. A switched capacitor notch filter is used to ensure chopping ripple free output voltage. The proposed techniques reduce the 10Hz to 100kHz integrated output noise of the LDO from 95.3uVrms to 14.8μVrms. The LDO delivers a maximum load current of 100mA with a dropout voltage of 230mV and quiescent current consumption of 40μA. It achieves a PSR of 50dB at 10kHz for programmable output voltage range of 1V-3.3V. Fabricated in a 0.25μm CMOS process, the LDO core occupies an area of 0.18mm2.
{"title":"A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference","authors":"Raveesh Magod, Naveen Suda, V. Ivanov, Ravi Balasingam, B. Bakkaloglu","doi":"10.1109/CICC.2015.7338446","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338446","url":null,"abstract":"Achieving low noise is becoming an important requirement in linear supply regulators for RF and mixed-signal SoC applications. A low-noise, low dropout regulator using switched-RC bandgap reference and a multi-loop, unconditionally stable error amplifier for output capacitor-less operation is presented. Switched-RC sample-and-hold filtered bandgap reference and current-mode chopped error amplifier techniques are used for reducing output noise of the LDO. A switched capacitor notch filter is used to ensure chopping ripple free output voltage. The proposed techniques reduce the 10Hz to 100kHz integrated output noise of the LDO from 95.3uVrms to 14.8μVrms. The LDO delivers a maximum load current of 100mA with a dropout voltage of 230mV and quiescent current consumption of 40μA. It achieves a PSR of 50dB at 10kHz for programmable output voltage range of 1V-3.3V. Fabricated in a 0.25μm CMOS process, the LDO core occupies an area of 0.18mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80672452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338477
M. Amourah, M. Whately
A new low-area and fast-locking Phase Locked Loop (PLL) is presented. The proposed PLL employs a new switched capacitor (SC) filter that uses fractional charge integration to implement capacitor multiplication effect. The proposed (SC) filter has a time response similar to the traditional passive filter response while occupying much smaller area and without any impact on other PLL blocks design. The proposed PLL was built in a 65nm CMOS process with a capacitance multiplication factor of 16 in parallel with a traditional filter for performance comparison. The PLL has an operating frequency range of 200MHz to 2.0GHz. Using a ring oscillator the PLL has period jitter in the order of 0.9ps RMS with acquisition time less than 10uS. Traditional LPF area is 180μm × 340μm while the (SC) LPF area is only 104μm × 84μm cutting LPF area by a factor 7.
{"title":"A novel switched-capacitor-filter based low-area and fast-locking PLL","authors":"M. Amourah, M. Whately","doi":"10.1109/CICC.2015.7338477","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338477","url":null,"abstract":"A new low-area and fast-locking Phase Locked Loop (PLL) is presented. The proposed PLL employs a new switched capacitor (SC) filter that uses fractional charge integration to implement capacitor multiplication effect. The proposed (SC) filter has a time response similar to the traditional passive filter response while occupying much smaller area and without any impact on other PLL blocks design. The proposed PLL was built in a 65nm CMOS process with a capacitance multiplication factor of 16 in parallel with a traditional filter for performance comparison. The PLL has an operating frequency range of 200MHz to 2.0GHz. Using a ring oscillator the PLL has period jitter in the order of 0.9ps RMS with acquisition time less than 10uS. Traditional LPF area is 180μm × 340μm while the (SC) LPF area is only 104μm × 84μm cutting LPF area by a factor 7.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80370604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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