Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338459
Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, D. Markovic, R. Harjani
We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of an 8-point A-FFT for an analysis filter bank, a VGA bank and a sub-ADC bank in the analog domain, and an inverse VGA bank, calibration and inverse FFT for the synthesis filter in the digital domain. The proposed structure enables the signals in each channel of the 450MHz wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in TSMC's 40nm CMOS GP process. A hybrid filter bank ADC does not have a constant average noise floor and is best used when both large and small signals are present. After calibration, the reconstructed signal with an asymmetric (40dB difference) two tone input, i.e., one large at 1MHz and one small at 225.05MHz shows 55.7dB of image rejection. The SNDR of the smaller signal improves by 6.0dB in comparison to a non-channelized ADC. The total power consumption for both the analog and digital sections is 90.4mW. As far as we are aware this is the first integrated implementation of the full hybrid filter bank principle.
{"title":"An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS","authors":"Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, D. Markovic, R. Harjani","doi":"10.1109/CICC.2015.7338459","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338459","url":null,"abstract":"We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of an 8-point A-FFT for an analysis filter bank, a VGA bank and a sub-ADC bank in the analog domain, and an inverse VGA bank, calibration and inverse FFT for the synthesis filter in the digital domain. The proposed structure enables the signals in each channel of the 450MHz wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in TSMC's 40nm CMOS GP process. A hybrid filter bank ADC does not have a constant average noise floor and is best used when both large and small signals are present. After calibration, the reconstructed signal with an asymmetric (40dB difference) two tone input, i.e., one large at 1MHz and one small at 225.05MHz shows 55.7dB of image rejection. The SNDR of the smaller signal improves by 6.0dB in comparison to a non-channelized ADC. The total power consumption for both the analog and digital sections is 90.4mW. As far as we are aware this is the first integrated implementation of the full hybrid filter bank principle.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87563437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338423
Tso-Wei Li, Hua Wang
This paper presents a millimeter-wave fully differential compact transformer-based passive reflective-type phase shifter (RTPS). The proposed RTPS design employs two transformer-based 90° couplers and two transformer-based multi-resonance reflective loads, offering low-loss and an ultra-compact chip size. A proof-of-concept design at 62GHz is implemented in a standard 130nm BiCMOS process with a core area of 480μm-by-340μm. It achieves a wide phase shifting range (up to 367°) and a low insertion loss (IL) (3.7dB<;|IL|<;10.2dB) at 62GHz. It also performs phase shifting with a constant insertion loss at a loss variation of less than 0.7dB. Full-span 360° phase interpolation is achieved from 58GHz to 64GHz with a worst-case minimum IL of 10.72dB. Compared with the reported 60GHz RTPS integrated in silicon, our design is the first to achieve a full-span 360° phase shift, has the lowest IL and the smallest IL variation, and presents the best figure-of-merit (FoM) of 36.26°/dB.
{"title":"A millimeter-wave fully differential transformer-based passive reflective-type phase shifter","authors":"Tso-Wei Li, Hua Wang","doi":"10.1109/CICC.2015.7338423","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338423","url":null,"abstract":"This paper presents a millimeter-wave fully differential compact transformer-based passive reflective-type phase shifter (RTPS). The proposed RTPS design employs two transformer-based 90° couplers and two transformer-based multi-resonance reflective loads, offering low-loss and an ultra-compact chip size. A proof-of-concept design at 62GHz is implemented in a standard 130nm BiCMOS process with a core area of 480μm-by-340μm. It achieves a wide phase shifting range (up to 367°) and a low insertion loss (IL) (3.7dB<;|IL|<;10.2dB) at 62GHz. It also performs phase shifting with a constant insertion loss at a loss variation of less than 0.7dB. Full-span 360° phase interpolation is achieved from 58GHz to 64GHz with a worst-case minimum IL of 10.72dB. Compared with the reported 60GHz RTPS integrated in silicon, our design is the first to achieve a full-span 360° phase shift, has the lowest IL and the smallest IL variation, and presents the best figure-of-merit (FoM) of 36.26°/dB.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87464503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338452
Yun Yin, Yanqiang Gao, Zhihua Wang, B. Chi
A 0.1-5.0GHz self-calibrated SDR transmitter is presented. A complete self-calibration scheme is proposed to alleviate non-ideal effects, including RF operation frequency deviation, output power control, LO leakage and image rejection. A power mixer front-end and a V-I converter with 3rd-order nonlinearity cancellation are introduced to achieve -62.6dBc CIM3 at 5.3dBm output power in LTE band42. A Class-AB/F dual-mode PA is integrated for narrowband applications. With the self-calibration, the transmitter has obtained good robustness in RF operation frequency self-tuning, LO leakage and image rejection performance over 0.1-5.0GHz, and achieved 24.5dBm Pout with 0.7% EVM, 20dBm Pout with 1.6% EVM, 6.2dBm Pout with 2.1% EVM for GSM/EDGE/LTE signals, respectively.
{"title":"A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS","authors":"Yun Yin, Yanqiang Gao, Zhihua Wang, B. Chi","doi":"10.1109/CICC.2015.7338452","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338452","url":null,"abstract":"A 0.1-5.0GHz self-calibrated SDR transmitter is presented. A complete self-calibration scheme is proposed to alleviate non-ideal effects, including RF operation frequency deviation, output power control, LO leakage and image rejection. A power mixer front-end and a V-I converter with 3rd-order nonlinearity cancellation are introduced to achieve -62.6dBc CIM3 at 5.3dBm output power in LTE band42. A Class-AB/F dual-mode PA is integrated for narrowband applications. With the self-calibration, the transmitter has obtained good robustness in RF operation frequency self-tuning, LO leakage and image rejection performance over 0.1-5.0GHz, and achieved 24.5dBm Pout with 0.7% EVM, 20dBm Pout with 1.6% EVM, 6.2dBm Pout with 2.1% EVM for GSM/EDGE/LTE signals, respectively.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"86 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88113996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338465
J. Yang, A. Raychowdhury
Summary form only given. This session presents state-of-the-art techniques for implementing analog circuits using digital cells and cell library elements. The first paper is an invited paper that discusses design opportunities using inverter based amplifier cells. The authors demonstrate PVT tolerant biasing of inverter based OTAs and validate the theory with experimental data. This is an invited paper in this session. The second paper discussed the design of an 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16× TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2. This third paper in the session presents a fully synthesized 0.4V analog Biquad filter in a 0.13μm technology using digital standard cells. A reconfigurable multi-state op-amp using has been proposed. The filter is implemented using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17dB peak SFDR and a tunable bandwidth of 1.7-2.5MHz while consuming 0.8mW power from a 0.4V analog supply and 1V supply for the switches.
{"title":"Session 6 — Analog circuits using digital cells","authors":"J. Yang, A. Raychowdhury","doi":"10.1109/CICC.2015.7338465","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338465","url":null,"abstract":"Summary form only given. This session presents state-of-the-art techniques for implementing analog circuits using digital cells and cell library elements. The first paper is an invited paper that discusses design opportunities using inverter based amplifier cells. The authors demonstrate PVT tolerant biasing of inverter based OTAs and validate the theory with experimental data. This is an invited paper in this session. The second paper discussed the design of an 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16× TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2. This third paper in the session presents a fully synthesized 0.4V analog Biquad filter in a 0.13μm technology using digital standard cells. A reconfigurable multi-state op-amp using has been proposed. The filter is implemented using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17dB peak SFDR and a tunable bandwidth of 1.7-2.5MHz while consuming 0.8mW power from a 0.4V analog supply and 1V supply for the switches.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"60 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84540729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/CICC.2015.7338457
Golam R. Chowdhury, A. Hassibi
This work presents a CMOS temperature sensor designed specifically for distributed thermal monitoring systems of high-performance system-on-chips (SoCs). The sensor uses the temperature-dependent reverse-bias current of a p-n diode to monitor on-chip thermal profile. It occupies a small footprint of 550μm2 in a 0.18μm process. The compact size of the sensor allows its usage as a “standard cell" at different on-chip coordinates to monitor localized heating due to potential hotspots on the SoC die. The sensor demonstrates measurement inaccuracies of ±0.1°C (3σ) with calibration, and +0.5°C (3σ) without any calibration, over 35°C-100°C measured temperature range. It consumes 4μW from a single 1.8V supply.
{"title":"A 550μm2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuracies","authors":"Golam R. Chowdhury, A. Hassibi","doi":"10.1109/CICC.2015.7338457","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338457","url":null,"abstract":"This work presents a CMOS temperature sensor designed specifically for distributed thermal monitoring systems of high-performance system-on-chips (SoCs). The sensor uses the temperature-dependent reverse-bias current of a p-n diode to monitor on-chip thermal profile. It occupies a small footprint of 550μm<sup>2</sup> in a 0.18μm process. The compact size of the sensor allows its usage as a “standard cell\" at different on-chip coordinates to monitor localized heating due to potential hotspots on the SoC die. The sensor demonstrates measurement inaccuracies of ±0.1°C (3σ) with calibration, and +0.5°C (3σ) without any calibration, over 35°C-100°C measured temperature range. It consumes 4μW from a single 1.8V supply.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86481323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/CICC.2015.7338493
Long Chen, Xiyuan Tang, A. Sanyal, Yeonam Yoon, Jie Cong, Nan Sun
This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.
{"title":"A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction","authors":"Long Chen, Xiyuan Tang, A. Sanyal, Yeonam Yoon, Jie Cong, Nan Sun","doi":"10.1109/CICC.2015.7338493","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338493","url":null,"abstract":"This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78459704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/CICC.2015.7338494
Kareem Ragab, Nan Sun
A direct digital background calibration technique to correct nonlinearity errors in VCO-based 0-1 MASH ΣΔ ADCs is presented. The proposed technique altogether corrects VCO gain error, nonlinearity, and capacitor mismatch of the residue generating DAC. It improves SNDR of the prototype ADC from 60dB to 73.4dB in 2.5MHz signal bandwidth. The ADC consumes 4.8mW from 1.8V supply in 180nm CMOS. The measured convergence time is only 64ms.
{"title":"A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0–1 MASH ADC with direct digital background nonlinearity calibration","authors":"Kareem Ragab, Nan Sun","doi":"10.1109/CICC.2015.7338494","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338494","url":null,"abstract":"A direct digital background calibration technique to correct nonlinearity errors in VCO-based 0-1 MASH ΣΔ ADCs is presented. The proposed technique altogether corrects VCO gain error, nonlinearity, and capacitor mismatch of the residue generating DAC. It improves SNDR of the prototype ADC from 60dB to 73.4dB in 2.5MHz signal bandwidth. The ADC consumes 4.8mW from 1.8V supply in 180nm CMOS. The measured convergence time is only 64ms.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"116 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75999856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/CICC.2015.7338391
Cheng Huang, T. Kawajiri, H. Ishikuro
This paper presents a 13.56MHz active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) for high-current biomedical implants. Near-optimum operation with compensated circuit delays is achieved by the proposed real-time NMOS on/off calibrations, which minimize the reverse current and maximize the transistor conduction time under various process, voltage, temperature and loading conditions. Adaptive sizing (AS) is also introduced to optimize the PCE over a wide loading range. Measurements in TSMC 65nm show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. With 2.5V input amplitude, the rectifier achieves a peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with a 1kΩ loading, and a maximum output power of 248.1mW.
{"title":"A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants","authors":"Cheng Huang, T. Kawajiri, H. Ishikuro","doi":"10.1109/CICC.2015.7338391","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338391","url":null,"abstract":"This paper presents a 13.56MHz active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) for high-current biomedical implants. Near-optimum operation with compensated circuit delays is achieved by the proposed real-time NMOS on/off calibrations, which minimize the reverse current and maximize the transistor conduction time under various process, voltage, temperature and loading conditions. Adaptive sizing (AS) is also introduced to optimize the PCE over a wide loading range. Measurements in TSMC 65nm show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. With 2.5V input amplitude, the rectifier achieves a peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with a 1kΩ loading, and a maximum output power of 248.1mW.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"224 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87209466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/CICC.2015.7338461
Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun
This paper presents a low-power and small-area VCO-based closed-loop ΔΣ ADC with two highlights. First, the ADC has a distributed modular architecture. It consists of repetitive slices, which simplifies both schematic and layout design. It allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked averaging (CLA) capability of dual VCO-based integrator. It ensures high linearity in the presence of large DAC mismatches. A prototype ADC in 130nm CMOS occupies only 0.04mm2. It achieves 71dB SNDR over 1.7MHz BW while sampling at 250MS/s and consuming 0.9mW under a 1.2V supply.
{"title":"A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration","authors":"Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun","doi":"10.1109/CICC.2015.7338461","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338461","url":null,"abstract":"This paper presents a low-power and small-area VCO-based closed-loop ΔΣ ADC with two highlights. First, the ADC has a distributed modular architecture. It consists of repetitive slices, which simplifies both schematic and layout design. It allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked averaging (CLA) capability of dual VCO-based integrator. It ensures high linearity in the presence of large DAC mismatches. A prototype ADC in 130nm CMOS occupies only 0.04mm2. It achieves 71dB SNDR over 1.7MHz BW while sampling at 250MS/s and consuming 0.9mW under a 1.2V supply.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"74 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90966061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-28DOI: 10.1109/CICC.2015.7338420
Xiang Gao, E. Klumperink, B. Nauta
In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N2, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter·power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N2, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.
{"title":"Sub-sampling PLL techniques","authors":"Xiang Gao, E. Klumperink, B. Nauta","doi":"10.1109/CICC.2015.7338420","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338420","url":null,"abstract":"In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N2, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter·power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N2, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"65 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83132928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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