Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626490
Jun Feng, Shixi Chen, Jiaxu Zhang, Jiang Xu
Computing systems, from HPC and data center to automobile, aircraft, and cellphone, are integrating growing numbers of processors, accelerators, memories, and peripherals to meet the burgeoning performance requirements of new applications under tight cost, energy, thermal, space, and weight constraints. Silicon photonics technologies piggyback onto developed silicon fabrication processes to provide viable and cost-effective solutions. A large number of silicon photonics devices and circuits have been demonstrated in CMOS-compatible fabrication processes. Silicon photonics technologies open up both new opportunities and new challenges to applications, architectures, design techniques, and design automation tools for hybrid photonicselectronics information systems. In the way of reaching perfect computing systems with silicon photonics, this paper tries to address three fundamental problems, including how computing systems could benefit from silicon photonics technologies, what technologies are required, and what the major challenges are.
{"title":"Rejuvenate Post-Moore’s Law Computing with Photonics-Electronics Hybrid Systems","authors":"Jun Feng, Shixi Chen, Jiaxu Zhang, Jiang Xu","doi":"10.1109/ICICDT51558.2021.9626490","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626490","url":null,"abstract":"Computing systems, from HPC and data center to automobile, aircraft, and cellphone, are integrating growing numbers of processors, accelerators, memories, and peripherals to meet the burgeoning performance requirements of new applications under tight cost, energy, thermal, space, and weight constraints. Silicon photonics technologies piggyback onto developed silicon fabrication processes to provide viable and cost-effective solutions. A large number of silicon photonics devices and circuits have been demonstrated in CMOS-compatible fabrication processes. Silicon photonics technologies open up both new opportunities and new challenges to applications, architectures, design techniques, and design automation tools for hybrid photonicselectronics information systems. In the way of reaching perfect computing systems with silicon photonics, this paper tries to address three fundamental problems, including how computing systems could benefit from silicon photonics technologies, what technologies are required, and what the major challenges are.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89529584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626467
Hongming Ma, Yan Wang
In this paper, a new fast recovery diode concept realizing low reverse recovery time, high dynamic ruggedness and good trade-off between dynamic and static characteristics is proposed. Controlled injection of backside holes (CIBH) structure is implemented at the cathode of merged PIN/Schottky (MPS) diode, which can reduce the cathode injection efficiency during on-state and suppress the fast extraction of carriers during reverse recovery process. Through Sentaurus TCAD simulation, the proposed structure achieved a reverse recovery time of 36ns and a reverse recovery peak current density of 325.2A/cm2 at the reverse voltage of 200V and the forward current density of 100A/cm2, which is improved by 42.9% and 35.7% compared with the MPS diode. Moreover, in oscillation test, the oscillation time and voltage amplitude are optimized by 50% and 37.3% respectively compared with MPS diode.
{"title":"Si MPS with CIBH Structure for Fast Recovery Applications","authors":"Hongming Ma, Yan Wang","doi":"10.1109/ICICDT51558.2021.9626467","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626467","url":null,"abstract":"In this paper, a new fast recovery diode concept realizing low reverse recovery time, high dynamic ruggedness and good trade-off between dynamic and static characteristics is proposed. Controlled injection of backside holes (CIBH) structure is implemented at the cathode of merged PIN/Schottky (MPS) diode, which can reduce the cathode injection efficiency during on-state and suppress the fast extraction of carriers during reverse recovery process. Through Sentaurus TCAD simulation, the proposed structure achieved a reverse recovery time of 36ns and a reverse recovery peak current density of 325.2A/cm2 at the reverse voltage of 200V and the forward current density of 100A/cm2, which is improved by 42.9% and 35.7% compared with the MPS diode. Moreover, in oscillation test, the oscillation time and voltage amplitude are optimized by 50% and 37.3% respectively compared with MPS diode.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"8 2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78271738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626399
Hongming Ma, Yan Wang
A N-type silicon carbide (SiC) gate turn-off thyristor (GTO) is designed and simulated with Sentaurus TCAD software, the detailed optimization process and final parameters are presented in this paper. By introducing 3-step JTE structure, a maximum breakdown voltage (BV) exceeding 15kV is achieved with 90μm drift layer, and over 13kV BV is available with an etching depth window of 0.28μm. By optimizing the P-base concentration, the maximum turn-off gain of the final structure is 6.01, and the forward voltage drop is 3.51V at 200A/cm2. The results show that this design can effectively increase the operating voltage and current of the power system while reducing dynamic loss.
{"title":"Design and Optimization of N-type SiC Gate Turn-off Thyristor with High Turn-off Gain and High Breakdown Voltage","authors":"Hongming Ma, Yan Wang","doi":"10.1109/ICICDT51558.2021.9626399","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626399","url":null,"abstract":"A N-type silicon carbide (SiC) gate turn-off thyristor (GTO) is designed and simulated with Sentaurus TCAD software, the detailed optimization process and final parameters are presented in this paper. By introducing 3-step JTE structure, a maximum breakdown voltage (BV) exceeding 15kV is achieved with 90μm drift layer, and over 13kV BV is available with an etching depth window of 0.28μm. By optimizing the P-base concentration, the maximum turn-off gain of the final structure is 6.01, and the forward voltage drop is 3.51V at 200A/cm2. The results show that this design can effectively increase the operating voltage and current of the power system while reducing dynamic loss.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74794045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626513
Ye Liang, Yuanlei Zhang, Yutao Cai, Zhaoyi Wang, Yinchao Zhao, H. Wen, Wen Liu
In this paper, D-mode MIS-HEMTs with 24 nm ALD-Al2O3 gate dielectric are studied. The electrical parameters, such as threshold voltage (Vth), drain current (Ids), on-resistant (Ron), sub-threshold swing (SS), and gate leakage current (Ileak) are investigated during the gate stress phase and recovery phase at room temperature. It is found that, during the stress phase, Vth and Ron show positive shifts while Ids show negative shifts. It is because channel electrons are trapped by the dielectric/III-nitride interface layer and by the bulk traps in the gate dielectric. However, these electrical parameter changes cannot be fully recoverable at the end of the recovery phase, followed by 30 mins thermal de-trapping. It may be caused by (1) positive gate bias induced unrecoverable defects in the dielectric layer. (2) bulk trap has a relatively large emission constant. (3) AlGaN barrier exists between the channel and dielectric/III-nitride interface layer, make the electrons hard to exchanges.
本文研究了24 nm ALD-Al2O3栅极介质的d模miss - hemt。研究了室温下栅应力阶段和恢复阶段的阈值电压(Vth)、漏极电流(Ids)、导通电阻(Ron)、亚阈值摆幅(SS)和栅漏电流(Ileak)等电学参数。结果表明，在应力阶段，Vth和Ron为正位移，而id为负位移。这是因为通道电子被介电/ iii -氮化物界面层和栅极介电中的体阱捕获。然而，这些电气参数的变化不能在回收阶段结束时完全恢复，随后是30分钟的热脱陷。它可能是由(1)正栅极偏压引起的介电层中不可恢复的缺陷引起的。(2)散装疏水阀具有较大的发射常数。(3)通道与介质/ iii -氮化物界面层之间存在AlGaN势垒，使得电子难以交换。
{"title":"Threshold Voltage Instability in D-mode AlGaN/GaN MIS-HEMTs with Al2O3 Gate Dielectric","authors":"Ye Liang, Yuanlei Zhang, Yutao Cai, Zhaoyi Wang, Yinchao Zhao, H. Wen, Wen Liu","doi":"10.1109/ICICDT51558.2021.9626513","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626513","url":null,"abstract":"In this paper, D-mode MIS-HEMTs with 24 nm ALD-Al2O3 gate dielectric are studied. The electrical parameters, such as threshold voltage (Vth), drain current (Ids), on-resistant (Ron), sub-threshold swing (SS), and gate leakage current (Ileak) are investigated during the gate stress phase and recovery phase at room temperature. It is found that, during the stress phase, Vth and Ron show positive shifts while Ids show negative shifts. It is because channel electrons are trapped by the dielectric/III-nitride interface layer and by the bulk traps in the gate dielectric. However, these electrical parameter changes cannot be fully recoverable at the end of the recovery phase, followed by 30 mins thermal de-trapping. It may be caused by (1) positive gate bias induced unrecoverable defects in the dielectric layer. (2) bulk trap has a relatively large emission constant. (3) AlGaN barrier exists between the channel and dielectric/III-nitride interface layer, make the electrons hard to exchanges.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76011090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626471
N. Khanh, T. Iizuka, K. Asada
In this paper, several shock-wave generator schemes in mm-wave frequencies integrated in Bi-CMOS/CMOS as well as CMOS-quartz packaging processes are reviewed. Shock-wave generator techniques are generally divided in voltage-mode and electric current-mode. In voltage-mode, damping RLC circuits are employed to generate mm-wave shock-waves in both parallel and serial configurations. In addition, a positive feedback shock-wave generator to spark an LC circuit and then generate a shock pulse is presented. The circuit does not need any edge-sharpener circuit or over-sized transistors and hence requires a small chip area. Current-mode shock wave generator is presented by a combination of a CMOS excitation circuit and an on-quartz transmission line resonator. Testing prototypes are fabricated, measured, and verified. These proposed shock-wave generators are suitable for transmitter design in low-cost low-power broadband sensing applications.
{"title":"Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper","authors":"N. Khanh, T. Iizuka, K. Asada","doi":"10.1109/ICICDT51558.2021.9626471","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626471","url":null,"abstract":"In this paper, several shock-wave generator schemes in mm-wave frequencies integrated in Bi-CMOS/CMOS as well as CMOS-quartz packaging processes are reviewed. Shock-wave generator techniques are generally divided in voltage-mode and electric current-mode. In voltage-mode, damping RLC circuits are employed to generate mm-wave shock-waves in both parallel and serial configurations. In addition, a positive feedback shock-wave generator to spark an LC circuit and then generate a shock pulse is presented. The circuit does not need any edge-sharpener circuit or over-sized transistors and hence requires a small chip area. Current-mode shock wave generator is presented by a combination of a CMOS excitation circuit and an on-quartz transmission line resonator. Testing prototypes are fabricated, measured, and verified. These proposed shock-wave generators are suitable for transmitter design in low-cost low-power broadband sensing applications.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77309534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626509
Rui Shao, Guangcheng Zhao, Gong Zhang, Xiao Gong
Optical neural network (ONN) utilizes light to process a mass amount of information in parallel using photonic integrated chips. It has great potential to bypass the limitation of Moore’s law and overcome the inherent bandwidth bottleneck in electronics enabled by the >10 THz wide optical telecommunications band. One of the main challenges for the realization of ONNs is how to avoid practical errors, including various device parameter errors during fabrication and the limited phase shifter control precision. Characterization of each individual chip is possible but time-consuming. To address this issue, in this paper, we propose a robust method to train a series of ONN chips with practical errors using the genetic algorithm (GA). The effect of different parameter errors on the data classification accuracy is analyzed, including the errors in phase shifters, coupling coefficient or extinction ratio, optical absorption loss, and photodetection noise. As a proof-of-concept demonstration, a simulated feedforward ONN is implemented to identify a customized dataset with four classes and four uncorrelated features. The simulation results show that our proposed method could increase the average classification accuracy from 86% to 96% for 50 erroneous ONN chips, approaching the ideal ONN accuracy of 99.69% and demonstrating the effectiveness for significant enhancement in training robustness against practical errors.
{"title":"Robust Training of Optical Neural Network with Practical Errors using Genetic Algorithm: A Case Study in Silicon-on-Insulator-Based Photonic Integrated Chips","authors":"Rui Shao, Guangcheng Zhao, Gong Zhang, Xiao Gong","doi":"10.1109/ICICDT51558.2021.9626509","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626509","url":null,"abstract":"Optical neural network (ONN) utilizes light to process a mass amount of information in parallel using photonic integrated chips. It has great potential to bypass the limitation of Moore’s law and overcome the inherent bandwidth bottleneck in electronics enabled by the >10 THz wide optical telecommunications band. One of the main challenges for the realization of ONNs is how to avoid practical errors, including various device parameter errors during fabrication and the limited phase shifter control precision. Characterization of each individual chip is possible but time-consuming. To address this issue, in this paper, we propose a robust method to train a series of ONN chips with practical errors using the genetic algorithm (GA). The effect of different parameter errors on the data classification accuracy is analyzed, including the errors in phase shifters, coupling coefficient or extinction ratio, optical absorption loss, and photodetection noise. As a proof-of-concept demonstration, a simulated feedforward ONN is implemented to identify a customized dataset with four classes and four uncorrelated features. The simulation results show that our proposed method could increase the average classification accuracy from 86% to 96% for 50 erroneous ONN chips, approaching the ideal ONN accuracy of 99.69% and demonstrating the effectiveness for significant enhancement in training robustness against practical errors.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73823963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626530
S. Yadav, P. Cardinael, M. Zhao, K. Vondkar, U. Peralagu, A. Alian, A. Khaled, S. Makovejev, E. Ekoga, D. Lederer, J. Raskin, B. Parvais, N. Collaert
GaN-on-Si HEMTs are one of the leading technology options for 5G and beyond frond-end-modules. Substrate RF losses and harmonic distortion degrade performance of both active as well as passive devices for power amplifier and switch applications. In this paper, we report on the substrate RF loss and linearity performance of GaN-on-Si technology. It is shown that coplanar waveguides on GaN-on-high resistivity (3–6 kΩ·cm) CZ-Si wafers can achieve 2nd harmonic levels ~ −85 dBm (on a 2 mm long CPW line at Pout ~15 dBm) with effective resistivity ρeff ~1 kΩ·cm. The impact of HEMT fabrication process and epitaxy on RF losses and distortion is studied and relationship between losses and distortion is discussed.
{"title":"CMOS compatible GaN-on-Si HEMT technology for RF applications: analysis of substrate losses and non-linearities","authors":"S. Yadav, P. Cardinael, M. Zhao, K. Vondkar, U. Peralagu, A. Alian, A. Khaled, S. Makovejev, E. Ekoga, D. Lederer, J. Raskin, B. Parvais, N. Collaert","doi":"10.1109/ICICDT51558.2021.9626530","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626530","url":null,"abstract":"GaN-on-Si HEMTs are one of the leading technology options for 5G and beyond frond-end-modules. Substrate RF losses and harmonic distortion degrade performance of both active as well as passive devices for power amplifier and switch applications. In this paper, we report on the substrate RF loss and linearity performance of GaN-on-Si technology. It is shown that coplanar waveguides on GaN-on-high resistivity (3–6 kΩ·cm) CZ-Si wafers can achieve 2nd harmonic levels ~ −85 dBm (on a 2 mm long CPW line at Pout ~15 dBm) with effective resistivity ρeff ~1 kΩ·cm. The impact of HEMT fabrication process and epitaxy on RF losses and distortion is studied and relationship between losses and distortion is discussed.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"71 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84134247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626487
Chao Zhang, Ding Li, Xiaodong Huang
InGaZnO is sensitive to the air moisture, which leads to the formation of metal-hydroxyl defects at the back channel and thus causes TFT stability issues. In this work, dual-gate TFT with an unisolated top gate directly contacting with IGZO is used to suppress the above stability issues because of its simple fabrication processes. On one hand, increasing the top gate region (or passivation region) is effective to block the moisture absorption; on the other hand, the post-deposition annealing facilitates the formation of an interfacial layer TiOx at the unisolated gate/IGZO back interface. It is found that this TiOx acts as acceptor-like deep-level traps and the TiOx region increases with increasing the top gate region, which is detrimental to the TFT performance and especially the sub-threshold swing and off-current.
{"title":"Effects of TiOx Interlayer on Performance of Dual-Gate InGaZnO Thin-Film Transistor","authors":"Chao Zhang, Ding Li, Xiaodong Huang","doi":"10.1109/ICICDT51558.2021.9626487","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626487","url":null,"abstract":"InGaZnO is sensitive to the air moisture, which leads to the formation of metal-hydroxyl defects at the back channel and thus causes TFT stability issues. In this work, dual-gate TFT with an unisolated top gate directly contacting with IGZO is used to suppress the above stability issues because of its simple fabrication processes. On one hand, increasing the top gate region (or passivation region) is effective to block the moisture absorption; on the other hand, the post-deposition annealing facilitates the formation of an interfacial layer TiOx at the unisolated gate/IGZO back interface. It is found that this TiOx acts as acceptor-like deep-level traps and the TiOx region increases with increasing the top gate region, which is detrimental to the TFT performance and especially the sub-threshold swing and off-current.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"124 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90567943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626397
Ying Sun, Yuchen Gu, Bing Chen, Xiao Yu, R. Cheng
In this work, we investigate the carrier ballistic transport characteristics from the perspective of self-heating effect (SHE), parasitic resistance, aging-induced traps and the cryogenic applications, for transistors with advanced structures and novel channel materials. As the SHE in the devices could be effectively eliminated by fast measurement, circuit-speed device transport characteristics could be accurately extracted. The large parasitic resistance in nanoscale transistors also affects the device transport behavior. Furthermore, for the future quantum-CMOS integration, the ballistic parameter extraction for the FinFETs was also performed to provide the relevant design parameter at the cryogenic environment.
{"title":"A Ballistic Transport Study for Advanced Transistors in Post-Moore Era: Parasitic Resistance, Self-heating and Cryogenic Analysis","authors":"Ying Sun, Yuchen Gu, Bing Chen, Xiao Yu, R. Cheng","doi":"10.1109/ICICDT51558.2021.9626397","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626397","url":null,"abstract":"In this work, we investigate the carrier ballistic transport characteristics from the perspective of self-heating effect (SHE), parasitic resistance, aging-induced traps and the cryogenic applications, for transistors with advanced structures and novel channel materials. As the SHE in the devices could be effectively eliminated by fast measurement, circuit-speed device transport characteristics could be accurately extracted. The large parasitic resistance in nanoscale transistors also affects the device transport behavior. Furthermore, for the future quantum-CMOS integration, the ballistic parameter extraction for the FinFETs was also performed to provide the relevant design parameter at the cryogenic environment.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"57 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81050015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626464
Arianna Morciano, M. Perenzoni, S. D’Amico
In this paper, a first order model of a pulsed mode SiPM-based LiDAR receiver is proposed. Starting from the description of the LiDAR receiver components, an analysis of the output signal and a model for the variable noise is presented. Considering the effects that occur with the first order model of SiPM, a model for the SNR calculation at output of the SiPM is extracted, in particular in terms of the relationship between number of photons. A dependence of SNR on the number of cells that characterize the SiPM is highlighted. At the end, a matching between the values coming from the Matlab simulations and the analytical results is shown.
{"title":"Signal-to-Noise Ratio in Pulsed Mode SiPMs for LiDAR Applications","authors":"Arianna Morciano, M. Perenzoni, S. D’Amico","doi":"10.1109/ICICDT51558.2021.9626464","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626464","url":null,"abstract":"In this paper, a first order model of a pulsed mode SiPM-based LiDAR receiver is proposed. Starting from the description of the LiDAR receiver components, an analysis of the output signal and a model for the variable noise is presented. Considering the effects that occur with the first order model of SiPM, a model for the SNR calculation at output of the SiPM is extracted, in particular in terms of the relationship between number of photons. A dependence of SNR on the number of cells that characterize the SiPM is highlighted. At the end, a matching between the values coming from the Matlab simulations and the analytical results is shown.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"30 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77134925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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