Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626497
T. Zhao, Chun Zhao, Yina Liu, Li Yang, I. Mitrovic, E. G. Lim, Cezhou Zhao
The synaptic transistors with MXenes as floating gate and titania (TiO2) as tunneling layer are prepared by a low-cost facile solution process. The devices exhibit typical synaptic behaviors of potentiation and depression by the gate voltage pulses. Moreover, through neuromorphic computing simulation, the transistors in this work show excellent recognition rate in the modified national institute of standards and technology (MNIST) database after 12,000 training states.
{"title":"Solution-processed Synaptic Transistors Utilizing MXenes as Floating Gate","authors":"T. Zhao, Chun Zhao, Yina Liu, Li Yang, I. Mitrovic, E. G. Lim, Cezhou Zhao","doi":"10.1109/ICICDT51558.2021.9626497","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626497","url":null,"abstract":"The synaptic transistors with MXenes as floating gate and titania (TiO2) as tunneling layer are prepared by a low-cost facile solution process. The devices exhibit typical synaptic behaviors of potentiation and depression by the gate voltage pulses. Moreover, through neuromorphic computing simulation, the transistors in this work show excellent recognition rate in the modified national institute of standards and technology (MNIST) database after 12,000 training states.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"5 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86707354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose and evaluate the performance of a 3D-embedded neuromorphic computation block based on indium gallium zinc oxide (α-IGZO) based nanosheet transistor and bi-layer resistive memory devices. We have fabricated bi-layer resistive random-access memory (RRAM) devices with Ta2O5 and Al2O3 layers. The device has been characterized and modeled. The compact models of RRAM and α-IGZO based embedded nanosheet structures have been used to evaluate the system level performance of 8 vertically stacked α-IGZO based nanosheet layers with RRAM for neuromorphic applications. The model considers the design space with uniform bit line (BL), select line (SL) and word line (WL) resistance. Finally, we have simulated the weighted sum operation with our proposed 8-layer stacked nanosheet based embedded memory and evaluated the performance for VGG-16 convolutional neural network (CNN) for Fashion-MNIST and CIFAR-10 data recognition, which yielded 92% and 75% accuracy respectively with drop out layers amid device variation.
{"title":"Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory","authors":"Sunanda Thunder, Parthasarathi Pal, Yeong-Her Wang, Po-Tsang Huang","doi":"10.1109/ICICDT51558.2021.9626489","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626489","url":null,"abstract":"In this paper we propose and evaluate the performance of a 3D-embedded neuromorphic computation block based on indium gallium zinc oxide (α-IGZO) based nanosheet transistor and bi-layer resistive memory devices. We have fabricated bi-layer resistive random-access memory (RRAM) devices with Ta2O5 and Al2O3 layers. The device has been characterized and modeled. The compact models of RRAM and α-IGZO based embedded nanosheet structures have been used to evaluate the system level performance of 8 vertically stacked α-IGZO based nanosheet layers with RRAM for neuromorphic applications. The model considers the design space with uniform bit line (BL), select line (SL) and word line (WL) resistance. Finally, we have simulated the weighted sum operation with our proposed 8-layer stacked nanosheet based embedded memory and evaluated the performance for VGG-16 convolutional neural network (CNN) for Fashion-MNIST and CIFAR-10 data recognition, which yielded 92% and 75% accuracy respectively with drop out layers amid device variation.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"36 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86793495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/ICICDT.2019.8790841
Jiayun Li, Huimin Du
{"title":"Tile Buffer Design for Linear-U Data Layout in Embedded GPU","authors":"Jiayun Li, Huimin Du","doi":"10.1109/ICICDT.2019.8790841","DOIUrl":"https://doi.org/10.1109/ICICDT.2019.8790841","url":null,"abstract":"","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75803943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-09DOI: 10.1109/ICICDT.2012.6232853
Chandra Nimmagadda, D. Lisk, R. Radojcic
Summary form only given. A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electroma
{"title":"3D stacking: Where the rubber meets the road","authors":"Chandra Nimmagadda, D. Lisk, R. Radojcic","doi":"10.1109/ICICDT.2012.6232853","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232853","url":null,"abstract":"Summary form only given. A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electroma","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74293547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-05-09DOI: 10.1109/ICICDT.2005.1502599
T. Hook
SOI technologies offer the highest possible performance in today's silicon spectrum, and are used for the very fastest processor requirements. In addition to the high speed achievable with this technology, there is also unusually high robustness against inline charging damage. In this paper, we review data and theories pertinent to SOI charging immunity and design rules.
{"title":"Charging damage and SOI","authors":"T. Hook","doi":"10.1109/ICICDT.2005.1502599","DOIUrl":"https://doi.org/10.1109/ICICDT.2005.1502599","url":null,"abstract":"SOI technologies offer the highest possible performance in today's silicon spectrum, and are used for the very fastest processor requirements. In addition to the high speed achievable with this technology, there is also unusually high robustness against inline charging damage. In this paper, we review data and theories pertinent to SOI charging immunity and design rules.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"24 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2005-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80039597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309949
J. Ackaert, A. Lowe, E. D. Backer, S. Boonen, T. Yao, J. V. Houdt, L. Haspeslagh
In this paper, for the first time, plasma induced damage (PID) on floating gate based non-volatile memory cells is reported. Since the cells consist of a complex combination of tunnel and gate oxides, combined with a dense frame of metal interconnect, the chance that these cells may be affected by plasma damage is evident. In order to investigate if the plasma damage affects the flash memory cells, the appropriate test structures have been designed, manufactured and measured. The test structures include structures to generate plasma damage as well as possible protective structures to prevent plasma damage.
{"title":"Plasma damage in HIMOS/spl trade/ non-volatile memories (NVM)","authors":"J. Ackaert, A. Lowe, E. D. Backer, S. Boonen, T. Yao, J. V. Houdt, L. Haspeslagh","doi":"10.1109/ICICDT.2004.1309949","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309949","url":null,"abstract":"In this paper, for the first time, plasma induced damage (PID) on floating gate based non-volatile memory cells is reported. Since the cells consist of a complex combination of tunnel and gate oxides, combined with a dense frame of metal interconnect, the chance that these cells may be affected by plasma damage is evident. In order to investigate if the plasma damage affects the flash memory cells, the appropriate test structures have been designed, manufactured and measured. The test structures include structures to generate plasma damage as well as possible protective structures to prevent plasma damage.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"15 3 1","pages":"223-226"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77489417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309963
M. Wang, T. Hou, K. Mai, P. Lim, L. Yao, Y. Jin, S. Chen, M. Liang, Wen-Fa Wu, S.-C. Ou, Mao-chieh Chen, Tiao-Yuan Huang
A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in detail. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N/sub 2/ plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current: and high driving current. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO/sub 2/.
{"title":"Electrical performance improvement in SiO/sub 2//HfSiO high-k gate stack for advanced low power device application","authors":"M. Wang, T. Hou, K. Mai, P. Lim, L. Yao, Y. Jin, S. Chen, M. Liang, Wen-Fa Wu, S.-C. Ou, Mao-chieh Chen, Tiao-Yuan Huang","doi":"10.1109/ICICDT.2004.1309963","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309963","url":null,"abstract":"A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in detail. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N/sub 2/ plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current: and high driving current. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO/sub 2/.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"203 0 1","pages":"283-286"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80531133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309944
Sandeep Oswal, Fernando A. Mujica, S. Prasad, R. Srinivasa, B. Sharma, A. Raychoudhary, H. Khasnis, Anmol Sharma, R. Sriram, B. Vijayvardhan, R. Menon, R. Gireesh, Nilesh A. Ahuja, M. Gambhir, Mangesh Sadafale
This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 /spl mu/m CMOS process.
{"title":"Analog front-end and power management integration on a 0.13 /spl mu/m CMOS ADSL SoC","authors":"Sandeep Oswal, Fernando A. Mujica, S. Prasad, R. Srinivasa, B. Sharma, A. Raychoudhary, H. Khasnis, Anmol Sharma, R. Sriram, B. Vijayvardhan, R. Menon, R. Gireesh, Nilesh A. Ahuja, M. Gambhir, Mangesh Sadafale","doi":"10.1109/ICICDT.2004.1309944","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309944","url":null,"abstract":"This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 /spl mu/m CMOS process.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"108 1","pages":"193-198"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75938474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309951
M. Lisiansky, Y. Roizin, M. Gutman, S. Keysar, A. Ben-Guigui, M. Berreby
In-process ultraviolet (UV) stimulated charging of ONO (oxide-nitride-oxide) stack is observed in fieldless microFlash (NROM) memory arrays. This problem is solved by introducing a UV blocking layer into the D1 dielectric. In this paper we discuss an alternative approach to the solution of charging problem. A micropartitioning technique is described that allows to screen out the operations responsible for ONO charging and corresponding equipment.
{"title":"ONO charging at different stages of microFlash/sup /spl reg// process flow","authors":"M. Lisiansky, Y. Roizin, M. Gutman, S. Keysar, A. Ben-Guigui, M. Berreby","doi":"10.1109/ICICDT.2004.1309951","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309951","url":null,"abstract":"In-process ultraviolet (UV) stimulated charging of ONO (oxide-nitride-oxide) stack is observed in fieldless microFlash (NROM) memory arrays. This problem is solved by introducing a UV blocking layer into the D1 dielectric. In this paper we discuss an alternative approach to the solution of charging problem. A micropartitioning technique is described that allows to screen out the operations responsible for ONO charging and corresponding equipment.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"65 1","pages":"231-235"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88399276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309959
M. T. Currie
Strained Si is emerging as a technology vital to the continued progression of transistor performance laid out in the International Technology Roadmap for Semiconductors. Strained Si fundamentals are reviewed, as is the structure of optimized strained Si substrates. Substrate fabrication guidelines that emphasize material quality and economic processing are discussed. The impact of the substrate structure on strained Si device performance and integration is described. Strained-Si-on-Insulator, an advanced structure derived from strained Si substrates, is also introduced.
{"title":"Strained silicon: engineered substrates and device integration","authors":"M. T. Currie","doi":"10.1109/ICICDT.2004.1309959","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309959","url":null,"abstract":"Strained Si is emerging as a technology vital to the continued progression of transistor performance laid out in the International Technology Roadmap for Semiconductors. Strained Si fundamentals are reviewed, as is the structure of optimized strained Si substrates. Substrate fabrication guidelines that emphasize material quality and economic processing are discussed. The impact of the substrate structure on strained Si device performance and integration is described. Strained-Si-on-Insulator, an advanced structure derived from strained Si substrates, is also introduced.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"70 1","pages":"261-268"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76960465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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