Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626398
Yuyi Liu, B. Gao
In order to improve accuracy and robustness of RRAM based computation-in-memory chip, device-circuit-algorithm co-optimization with consideration of underlying device and array nonidealities should outperform the individual optimization of device or algorithm. In this work, we provide a device-circuit-algorithm simulation framework and propose the corresponding design guidelines. The simulation framework supports both inference and on-chip training, and a physics-based device model for analog RRAM is embedded to the framework to benchmark the CIM system. Nonideal effects and reliability issues of analog RRAM device are fully considered. Besides, array IR-drop and peripheral circuit are also modeled. Based on the evaluation results, optimization guidelines to suppress the impact of device nonidealities, reliability degradation and array IR-drop are proposed. This work provides a useful end-to-end co-design tool for developing large-scale computation-in-memory systems.
{"title":"System and Technology Co-optimization for RRAM based Computation-in-memory Chip","authors":"Yuyi Liu, B. Gao","doi":"10.1109/ICICDT51558.2021.9626398","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626398","url":null,"abstract":"In order to improve accuracy and robustness of RRAM based computation-in-memory chip, device-circuit-algorithm co-optimization with consideration of underlying device and array nonidealities should outperform the individual optimization of device or algorithm. In this work, we provide a device-circuit-algorithm simulation framework and propose the corresponding design guidelines. The simulation framework supports both inference and on-chip training, and a physics-based device model for analog RRAM is embedded to the framework to benchmark the CIM system. Nonideal effects and reliability issues of analog RRAM device are fully considered. Besides, array IR-drop and peripheral circuit are also modeled. Based on the evaluation results, optimization guidelines to suppress the impact of device nonidealities, reliability degradation and array IR-drop are proposed. This work provides a useful end-to-end co-design tool for developing large-scale computation-in-memory systems.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"58 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75075085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626483
Qihan Liu, C. Zhao, Y. Liu, I. Mitrovic, Wangying Xu, Li Yang, Z. Wang, W. Wei, Y. Wu, X. Yu
In this study, we describe combustion-processed high-quality Li-AlOx thin films and their implementation in In-2O3 synaptic transistors by a low temperatures (300 °C) water-based method. The resulting synaptic transistors presented a superior electrical performance at a low operating voltage of 3 V, with a positive threshold voltage of 0.5 V, a subthreshold swing of 0.21 V/decade, an On/Off ratio of 1.5×105, and a mobility value of 87 cm2 V−1 s−1. Counterclockwise hysteresis was observed in the transfer curve and the synaptic transistor was employed to perform synaptic emulation. Long-term and short-term synaptic depression and potentiation behavior were emulated.
{"title":"Water-induced Combustion-processed Metal-oxide Synaptic Transistor","authors":"Qihan Liu, C. Zhao, Y. Liu, I. Mitrovic, Wangying Xu, Li Yang, Z. Wang, W. Wei, Y. Wu, X. Yu","doi":"10.1109/ICICDT51558.2021.9626483","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626483","url":null,"abstract":"In this study, we describe combustion-processed high-quality Li-AlO<inf>x</inf> thin films and their implementation in In-<inf>2</inf>O<inf>3</inf> synaptic transistors by a low temperatures (300 °C) water-based method. The resulting synaptic transistors presented a superior electrical performance at a low operating voltage of 3 V, with a positive threshold voltage of 0.5 V, a subthreshold swing of 0.21 V/decade, an On/Off ratio of 1.5×10<sup>5</sup>, and a mobility value of 87 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>. Counterclockwise hysteresis was observed in the transfer curve and the synaptic transistor was employed to perform synaptic emulation. Long-term and short-term synaptic depression and potentiation behavior were emulated.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79001940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626536
Hua Fan, Yunan Wang, Xinjie Wu
This paper proposes a SAR ADC front-end calibration technique based on sorting and recombination of capacitor arrays to mitigate the impact of capacitor mismatch on the performance of high-precision SAR ADCs. This method performs proper and effective sorting and reconstruction of the unit capacitors in the capacitor array before the SAR ADC performs data conversion. In addition, an achievable digital bubble sorting module is proposed to be used in this sorting scheme, which overcomes the limitation that the analog bubble sorting module cannot be applied to high-precision SAR ADC due to the complexity of the analog bubble sorting module. For the C-DAC using N unit capacitors, a digital bubble sorting circuit is used instead of an analog bubble sorting circuit, which can reduce the number of digital-to-analog connection signal lines from N2 to N. A 1 MS/s 8-bit SAR ADC is designed based on XFAB 0.18 μm process to verify this method. The results show that before and after calibration, SNDR is increased by 3.6 dB, SFDR is increased by 11.9 dB, and ENOB can reach 7.9. The method is simple and reliable, and is suitable for various SAR ADCs based on charge redistribution structures.
{"title":"A Realizable Digital Bubble Sorting SAR ADC Calibration Technology","authors":"Hua Fan, Yunan Wang, Xinjie Wu","doi":"10.1109/ICICDT51558.2021.9626536","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626536","url":null,"abstract":"This paper proposes a SAR ADC front-end calibration technique based on sorting and recombination of capacitor arrays to mitigate the impact of capacitor mismatch on the performance of high-precision SAR ADCs. This method performs proper and effective sorting and reconstruction of the unit capacitors in the capacitor array before the SAR ADC performs data conversion. In addition, an achievable digital bubble sorting module is proposed to be used in this sorting scheme, which overcomes the limitation that the analog bubble sorting module cannot be applied to high-precision SAR ADC due to the complexity of the analog bubble sorting module. For the C-DAC using N unit capacitors, a digital bubble sorting circuit is used instead of an analog bubble sorting circuit, which can reduce the number of digital-to-analog connection signal lines from N2 to N. A 1 MS/s 8-bit SAR ADC is designed based on XFAB 0.18 μm process to verify this method. The results show that before and after calibration, SNDR is increased by 3.6 dB, SFDR is increased by 11.9 dB, and ENOB can reach 7.9. The method is simple and reliable, and is suitable for various SAR ADCs based on charge redistribution structures.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90660400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626531
Aniket Gupta, Nitanshu Chauhan, Om. Prakash, H. Amrouch
This work investigates, the impact of different variability sources 14nm FinFET transistors compared to their counterpart Negative Capacitance FinFETs transistors. We focus on NC-FinFETs that are constructed in a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, unlike existing state of the art, which employs Metal–Ferroelectric–Metal-Insulator–Semiconductor (MFMIS) structure in its variability analysis. Our investigation confirms that the existing conclusion, in which NC-FinFETs exhibit a higher immunity against variation, still holds even in MFIS structure. We study the impact that each of (1) random dopant fluctuation, (2) work-function variation, (3) HfO2 dielectric surface roughness, (4) interfacial layer surface roughness, and (5) ferroelectric variation has individually and jointly on the threshold voltage, sub-threshold swing, ON current and OFF current of NC-nFinFETs and NC-pFinFETs in comparison to their counterpart (baseline) FinFET devices.
{"title":"Variability Effects in FinFET Transistors and Emerging NC-FinFET","authors":"Aniket Gupta, Nitanshu Chauhan, Om. Prakash, H. Amrouch","doi":"10.1109/ICICDT51558.2021.9626531","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626531","url":null,"abstract":"This work investigates, the impact of different variability sources 14nm FinFET transistors compared to their counterpart Negative Capacitance FinFETs transistors. We focus on NC-FinFETs that are constructed in a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, unlike existing state of the art, which employs Metal–Ferroelectric–Metal-Insulator–Semiconductor (MFMIS) structure in its variability analysis. Our investigation confirms that the existing conclusion, in which NC-FinFETs exhibit a higher immunity against variation, still holds even in MFIS structure. We study the impact that each of (1) random dopant fluctuation, (2) work-function variation, (3) HfO2 dielectric surface roughness, (4) interfacial layer surface roughness, and (5) ferroelectric variation has individually and jointly on the threshold voltage, sub-threshold swing, ON current and OFF current of NC-nFinFETs and NC-pFinFETs in comparison to their counterpart (baseline) FinFET devices.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78537089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626499
Zhigang Ji, Jianfu Zhang
Future secure communication relies on the true Random number Generator (TRNG), of which the random source is of most importance for offering high entropy. The random telegraph noise (RTN) in nano-scaled devices show excellent randomness, however, RTN-based TRNG suffer from relatively large area and low speed. Here we introduce our recently-proposed solutions to tackle these two issues. Then we performed systematic analysis based on Monte Carlo simulation to understand the impact of design parameters on its practical performance, shedding light on the practical circuit design.
{"title":"Understanding Generated RTN as an Entropy Source for True Random Number Generators","authors":"Zhigang Ji, Jianfu Zhang","doi":"10.1109/ICICDT51558.2021.9626499","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626499","url":null,"abstract":"Future secure communication relies on the true Random number Generator (TRNG), of which the random source is of most importance for offering high entropy. The random telegraph noise (RTN) in nano-scaled devices show excellent randomness, however, RTN-based TRNG suffer from relatively large area and low speed. Here we introduce our recently-proposed solutions to tackle these two issues. Then we performed systematic analysis based on Monte Carlo simulation to understand the impact of design parameters on its practical performance, shedding light on the practical circuit design.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79936243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626492
S. Kolodinski, H. Eisenreich, S. Lehmann, J. Müller
In this contribution we present two cases of specialized variants for 22FDXTM technology in which detailed Design and Technology co-development is needed. (1) The e-NVM-variant perpendicular Spin Transfer Torque needed development of characterization techniques for the characterization of magnetic properties and STT-current and at the same time a demonstrator was developed that makes effective use of the Back-Biasing for leakage reduction. (2) Furthermore, the mmWave derivative requires characterization of functionality up to 100 GHz and far beyond, while at the same time showcases on 5G auto-radar and imaging radar could be started.
{"title":"IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology","authors":"S. Kolodinski, H. Eisenreich, S. Lehmann, J. Müller","doi":"10.1109/ICICDT51558.2021.9626492","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626492","url":null,"abstract":"In this contribution we present two cases of specialized variants for 22FDXTM technology in which detailed Design and Technology co-development is needed. (1) The e-NVM-variant perpendicular Spin Transfer Torque needed development of characterization techniques for the characterization of magnetic properties and STT-current and at the same time a demonstrator was developed that makes effective use of the Back-Biasing for leakage reduction. (2) Furthermore, the mmWave derivative requires characterization of functionality up to 100 GHz and far beyond, while at the same time showcases on 5G auto-radar and imaging radar could be started.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84125508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626529
Lingxi Xia, YungC . Liang
By profiling the AlGaN layer, the sensitivity of the AlGaN/GaN high-electron-mobility magnetoresistive sensor device can be much enhanced. The previous work on fin-shaped magnetoresistive devices had demonstrated the effect on transitioning the AlGaN profile. In this study, the design is based on a staircase-shaped profile for the sensor, which leads to a unique 2DEG distribution in the transition region. Such a design yields a more stable and higher sensitivity in the measurement of magnetic field in micro-Tesla level.
{"title":"High-sensitivity AlGaN/GaN magnetoresistive sensor device by profiling the AlGaN layer","authors":"Lingxi Xia, YungC . Liang","doi":"10.1109/ICICDT51558.2021.9626529","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626529","url":null,"abstract":"By profiling the AlGaN layer, the sensitivity of the AlGaN/GaN high-electron-mobility magnetoresistive sensor device can be much enhanced. The previous work on fin-shaped magnetoresistive devices had demonstrated the effect on transitioning the AlGaN profile. In this study, the design is based on a staircase-shaped profile for the sensor, which leads to a unique 2DEG distribution in the transition region. Such a design yields a more stable and higher sensitivity in the measurement of magnetic field in micro-Tesla level.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"43 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83872729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626538
Shenjian Zhang, S. Lam
A compact and chip-area efficient transmission line design is proposed for monolithic millimeter-wave integrated circuits. Performance improvement is achieved by the use of multi-layered air-gaps compatible to CMOS fabrication. Based on a 65-nm CMOS process, the on-chip transmission line occupies less than 17 μm in width and 8 μm in height while active devices and circuits can still be fabricated with interconnect routing right beneath the shielded structure of the transmission line. The semi-enclosed structure allows the tuning of the characteristic impedance. 3D electromagnetic simulations give results of 1.8 dB/mm insertion loss and a reflection coefficient of −28 dB at 60 GHz, for a 50-ohm matched design. The multi-layered air-gap design allows the current density more uniformly distributed in the signal-carrying conductor compared with a counterpart design without air-gaps.
{"title":"A Multi-Layered Air-Gap Transmission Line Design for CMOS-Compatible Millimeter-Wave ICs","authors":"Shenjian Zhang, S. Lam","doi":"10.1109/ICICDT51558.2021.9626538","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626538","url":null,"abstract":"A compact and chip-area efficient transmission line design is proposed for monolithic millimeter-wave integrated circuits. Performance improvement is achieved by the use of multi-layered air-gaps compatible to CMOS fabrication. Based on a 65-nm CMOS process, the on-chip transmission line occupies less than 17 μm in width and 8 μm in height while active devices and circuits can still be fabricated with interconnect routing right beneath the shielded structure of the transmission line. The semi-enclosed structure allows the tuning of the characteristic impedance. 3D electromagnetic simulations give results of 1.8 dB/mm insertion loss and a reflection coefficient of −28 dB at 60 GHz, for a 50-ohm matched design. The multi-layered air-gap design allows the current density more uniformly distributed in the signal-carrying conductor compared with a counterpart design without air-gaps.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"15 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75212283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626539
Zhikai Wang, Wenfei Hu, Ziyu Gu, Wenyuan Zhang, S.-D. Yin, Ruitao Wang, Jian Zhang, Yan Wang
Carbon nanotube field-effect transistor (CNT-FET), as a kind of efficient device, is expected to be the mainstream product of complementary metal–oxide–semi-conductor (CMOS) integrated circuits (ICs). The simulation based on SPICE model plays a significant role before ICs been fabricated. However, most of the previous circuits and simulations are based on only P-type CNT model. In this paper, we build N-type and P-type CNT model by denominator numerator fit (DNFIT) technique, perform successfully large-scale (>1000) CNT CMOS ICs simulation on CADENCE for the first time. The simulation results show that large scale CNT CMOS ICs can achieve correct logic performance.
{"title":"Large-scale Integrated Circuits Simulation Based on CNT-FET Model","authors":"Zhikai Wang, Wenfei Hu, Ziyu Gu, Wenyuan Zhang, S.-D. Yin, Ruitao Wang, Jian Zhang, Yan Wang","doi":"10.1109/ICICDT51558.2021.9626539","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626539","url":null,"abstract":"Carbon nanotube field-effect transistor (CNT-FET), as a kind of efficient device, is expected to be the mainstream product of complementary metal–oxide–semi-conductor (CMOS) integrated circuits (ICs). The simulation based on SPICE model plays a significant role before ICs been fabricated. However, most of the previous circuits and simulations are based on only P-type CNT model. In this paper, we build N-type and P-type CNT model by denominator numerator fit (DNFIT) technique, perform successfully large-scale (>1000) CNT CMOS ICs simulation on CADENCE for the first time. The simulation results show that large scale CNT CMOS ICs can achieve correct logic performance.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87224111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-15DOI: 10.1109/ICICDT51558.2021.9626494
Chin-Hao Chang, Meng-Hsiu Wu, Meng-Hsien Tsai, Chiao-Yi Huang, C. Chao
Random Telegraph Noise (RTN) is a type of electronic noise that occurs in semiconductors and ultra-thin gate oxide films. RTN data acquisition and analysis require multiple measurements of millions of devices which is time consuming. This paper presents the design of a real-time RTN analysis system which achieved 17x speed boost with same accuracy by real-time processing noise data through DDR3 memory access. The designed system reduces the per wafer RTN analysis time from 5.5 hours to 0.33 hour.
{"title":"A 50K devices/sec Real-Time RTN Analysis System for Technology Benchmarking","authors":"Chin-Hao Chang, Meng-Hsiu Wu, Meng-Hsien Tsai, Chiao-Yi Huang, C. Chao","doi":"10.1109/ICICDT51558.2021.9626494","DOIUrl":"https://doi.org/10.1109/ICICDT51558.2021.9626494","url":null,"abstract":"Random Telegraph Noise (RTN) is a type of electronic noise that occurs in semiconductors and ultra-thin gate oxide films. RTN data acquisition and analysis require multiple measurements of millions of devices which is time consuming. This paper presents the design of a real-time RTN analysis system which achieved 17x speed boost with same accuracy by real-time processing noise data through DDR3 memory access. The designed system reduces the per wafer RTN analysis time from 5.5 hours to 0.33 hour.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90302863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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