Pub Date : 2025-11-14DOI: 10.1109/LMWT.2025.3630277
Ting-Li Hsu;Amelie Hagelauer;Valentyn Solomko
In this work, a closed-loop radio frequency (RF) frontend impedance tuning system with high-voltage impedance tuning switches monolithically integrated with an RF reflectometer is presented. An RF application-specific integrated circuit (ASIC) integrating a low-power scalar RF reflectometer and two RF tuning switches is designed and manufactured in ${90}{,}text{nm}$ RF SOI CMOS switch technology. A hardware prototype closed-loop tuning system is built with the designed ASIC along with a commercial impedance tuning IC, aiming for tuning at operating frequencies between 690 and ${900}{,}text {MHz}$ . The circuit can process signals with power greater than ${18}{,}text {dBm}$ , while the RF voltage handling capability reaches ${63}{,}text {V}$ with the linearity of $text {IIP}_{{3}}={84}{,}text {dBm}$ in the signal path. The designed ASIC consumes ${46}{,}{{mu }text {W}}$ and ${184}{,}{{mu }text {W}}$ in idle and conversion mode, respectively.
{"title":"A Closed-Loop Impedance Tuner With Integrated Reflectometer and High-Voltage Tuning Switches","authors":"Ting-Li Hsu;Amelie Hagelauer;Valentyn Solomko","doi":"10.1109/LMWT.2025.3630277","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3630277","url":null,"abstract":"In this work, a closed-loop radio frequency (RF) frontend impedance tuning system with high-voltage impedance tuning switches monolithically integrated with an RF reflectometer is presented. An RF application-specific integrated circuit (ASIC) integrating a low-power scalar RF reflectometer and two RF tuning switches is designed and manufactured in <inline-formula> <tex-math>${90}{,}text{nm}$ </tex-math></inline-formula> RF SOI CMOS switch technology. A hardware prototype closed-loop tuning system is built with the designed ASIC along with a commercial impedance tuning IC, aiming for tuning at operating frequencies between 690 and <inline-formula> <tex-math>${900}{,}text {MHz}$ </tex-math></inline-formula>. The circuit can process signals with power greater than <inline-formula> <tex-math>${18}{,}text {dBm}$ </tex-math></inline-formula>, while the RF voltage handling capability reaches <inline-formula> <tex-math>${63}{,}text {V}$ </tex-math></inline-formula> with the linearity of <inline-formula> <tex-math>$text {IIP}_{{3}}={84}{,}text {dBm}$ </tex-math></inline-formula> in the signal path. The designed ASIC consumes <inline-formula> <tex-math>${46}{,}{{mu }text {W}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${184}{,}{{mu }text {W}}$ </tex-math></inline-formula> in idle and conversion mode, respectively.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2117-2120"},"PeriodicalIF":3.4,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248891","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In wireless communications, accurate frequency estimation is essential to support reliable demodulation, channel management, and spectrum surveillance. At terahertz frequencies, the higher carrier values and narrow channel spacing demand much finer frequency estimation, which requires high-resolution frequency discrimination. Conventional grating-based approaches are bulky and limited in resolution, making them unsuitable for compact terahertz systems. In this letter, we present a 3D-printed pseudo-random dielectric metasurface that enables subgigahertz frequency discrimination in the 220–330-GHz band through spatially diverse near-field patterns. The design leverages frequency-dependent scattering to create unique intensity distributions captured by a terahertz camera. We demonstrate that these spatial signatures can be used for frequency discrimination by training a convolutional neural network (CNN) to identify the frequency from a single image. To substantiate the reliability of the metasurface response, we employ multiple beam configurations with varying incidence angles in our experimental setup. The results demonstrate high classification accuracy over the operational range, thus corroborating the metasurface as a viable passive frequency analyzer for terahertz communications.
{"title":"3D-Printed Frequency-Diverse Metasurface for Camera-Based Terahertz Frequency Analyzer","authors":"Sakib Quader;Mariam Abdullah;Estrid He;Christophe Fumeaux;Withawat Withayachumnankul","doi":"10.1109/LMWT.2025.3628705","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3628705","url":null,"abstract":"In wireless communications, accurate frequency estimation is essential to support reliable demodulation, channel management, and spectrum surveillance. At terahertz frequencies, the higher carrier values and narrow channel spacing demand much finer frequency estimation, which requires high-resolution frequency discrimination. Conventional grating-based approaches are bulky and limited in resolution, making them unsuitable for compact terahertz systems. In this letter, we present a 3D-printed pseudo-random dielectric metasurface that enables subgigahertz frequency discrimination in the 220–330-GHz band through spatially diverse near-field patterns. The design leverages frequency-dependent scattering to create unique intensity distributions captured by a terahertz camera. We demonstrate that these spatial signatures can be used for frequency discrimination by training a convolutional neural network (CNN) to identify the frequency from a single image. To substantiate the reliability of the metasurface response, we employ multiple beam configurations with varying incidence angles in our experimental setup. The results demonstrate high classification accuracy over the operational range, thus corroborating the metasurface as a viable passive frequency analyzer for terahertz communications.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2105-2108"},"PeriodicalIF":3.4,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1109/LMWT.2025.3629107
Uichan Park;Taeyeong Yoon;Jungsuek Oh
This letter presents a compact and highly accurate active bidirectional phase shifter (ABPS) with reduced root-mean-square (rms) errors in 28-nm CMOS. The proposed ABPS integrates a transformer-based hybrid coupler (THC) for I/Q signal generation and combining, a bidirectional amplification core, and a Marchand balun-based rat-race coupler (MRRC) for precise signal subtraction and division. A three-stack single Gilbert cell (GC) architecture, arranged in an anti-parallel configuration, enables both amplitude scaling and 180° phase inversion within a compact footprint. An optimized novel electromagnetic (EM) structure is implemented to achieve high port-to-port isolation, ensuring precise phase and magnitude control. The proposed ABPS supports a 6-bit phase shift operation across a full 360° range and demonstrates rms gain and phase errors of 0.36 dB and 2.1°, respectively, in both forward and backward directions. The proposed ABPS was fabricated in a compact area of $1.08times 0.42$ mm2, consuming 16.2 mW.
{"title":"A Compact Active Bidirectional Phase Shifter Employing a Highly Isolated Single Gilbert Cell","authors":"Uichan Park;Taeyeong Yoon;Jungsuek Oh","doi":"10.1109/LMWT.2025.3629107","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3629107","url":null,"abstract":"This letter presents a compact and highly accurate active bidirectional phase shifter (ABPS) with reduced root-mean-square (rms) errors in 28-nm CMOS. The proposed ABPS integrates a transformer-based hybrid coupler (THC) for I/Q signal generation and combining, a bidirectional amplification core, and a Marchand balun-based rat-race coupler (MRRC) for precise signal subtraction and division. A three-stack single Gilbert cell (GC) architecture, arranged in an anti-parallel configuration, enables both amplitude scaling and 180° phase inversion within a compact footprint. An optimized novel electromagnetic (EM) structure is implemented to achieve high port-to-port isolation, ensuring precise phase and magnitude control. The proposed ABPS supports a 6-bit phase shift operation across a full 360° range and demonstrates rms gain and phase errors of 0.36 dB and 2.1°, respectively, in both forward and backward directions. The proposed ABPS was fabricated in a compact area of <inline-formula> <tex-math>$1.08times 0.42$ </tex-math></inline-formula> mm<sup>2</sup>, consuming 16.2 mW.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2109-2112"},"PeriodicalIF":3.4,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter proposes an impedance estimation method for the floating electrode multilayered ceramic capacitors (FE MLCCs) based on multiconductor transmission line (MTL) theory. The impedance of FE MLCC is a key factor in the design and optimization of electronic circuits because it directly influences system performance. However, impedance extraction through measurement or full-wave simulation is both time-consuming and computationally intensive. Therefore, it is necessary to predict the impedance of FE MLCC rapidly and efficiently. In the proposed method, the FE MLCC is divided into two subblocks, and the impedance of each subblock can be derived analytically based on the MTL theory, while considering both vertical and lateral inductive coupling among the electrodes. The proposed method was verified by comparing it with simulation results, showing maximum errors of 4.85% and 10.74% for self-resonant frequency (SRF) and equivalent series inductance, respectively. In addition, the proposed method achieves up to 3112 times faster computation compared with full-wave simulation.
{"title":"A Method for Estimating Impedance of Floating Electrode Multilayered Ceramic Capacitor","authors":"Sanguk Lee;Jaewon Rhee;Seunghun Ryu;Seonghi Lee;Hyunwoo Kim;Hongseok Kim;Seungyoung Ahn","doi":"10.1109/LMWT.2025.3627178","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3627178","url":null,"abstract":"This letter proposes an impedance estimation method for the floating electrode multilayered ceramic capacitors (FE MLCCs) based on multiconductor transmission line (MTL) theory. The impedance of FE MLCC is a key factor in the design and optimization of electronic circuits because it directly influences system performance. However, impedance extraction through measurement or full-wave simulation is both time-consuming and computationally intensive. Therefore, it is necessary to predict the impedance of FE MLCC rapidly and efficiently. In the proposed method, the FE MLCC is divided into two subblocks, and the impedance of each subblock can be derived analytically based on the MTL theory, while considering both vertical and lateral inductive coupling among the electrodes. The proposed method was verified by comparing it with simulation results, showing maximum errors of 4.85% and 10.74% for self-resonant frequency (SRF) and equivalent series inductance, respectively. In addition, the proposed method achieves up to 3112 times faster computation compared with full-wave simulation.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2125-2128"},"PeriodicalIF":3.4,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1109/LMWT.2025.3624929
{"title":"IEEE Microwave and Wireless Technology Letters Information for Authors","authors":"","doi":"10.1109/LMWT.2025.3624929","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3624929","url":null,"abstract":"","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 11","pages":"C3-C3"},"PeriodicalIF":3.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11234902","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a three-stage 6–18-GHz 25-W gallium nitride (GaN) reactively matched power amplifier (RMPA). A horizontally opposed transistor (HOT) layout is proposed to mitigate the thermal coupling. Thermal simulations reveal that in the HOT layout, the junction temperature can remain at significantly reduced levels compared to that in the conventional layout. Furthermore, a direct drain biasing/combining (DDBC) topology tailored for the HOT layout is employed to the output matching network (OMN), which facilitates broadband matching and simultaneously enhances circuital symmetry and simplicity. Continuous-wave (CW) mode measurement results in 6–18 GHz show that the presented RMPA can realize an average saturated output power (${P} _{mathbf {SAT}}$ ) and power added efficiency (PAE) of 25 W and 26%, respectively, achieving a high power density (${P} _{mathbf {DEN}}$ ) of 2.524.50 W/mm${}^{mathbf {2}}$ . The maximum degradations of ${P} _{mathbf {SAT}}$ and PAE at $+ 85~^{circ }$ C are 0.7 dB and 3.9%, respectively.
{"title":"Thermal-Coupling-Mitigated 6–18-GHz 25-W GaN Power Amplifier Using Horizontally Opposed Transistor Layout","authors":"Xiangdong Wang;Shouren Chen;Jie Gu;Yang Liu;Mo Li;Jian Zhang","doi":"10.1109/LMWT.2025.3627330","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3627330","url":null,"abstract":"This letter presents a three-stage 6–18-GHz 25-W gallium nitride (GaN) reactively matched power amplifier (RMPA). A horizontally opposed transistor (HOT) layout is proposed to mitigate the thermal coupling. Thermal simulations reveal that in the HOT layout, the junction temperature can remain at significantly reduced levels compared to that in the conventional layout. Furthermore, a direct drain biasing/combining (DDBC) topology tailored for the HOT layout is employed to the output matching network (OMN), which facilitates broadband matching and simultaneously enhances circuital symmetry and simplicity. Continuous-wave (CW) mode measurement results in 6–18 GHz show that the presented RMPA can realize an average saturated output power (<inline-formula> <tex-math>${P} _{mathbf {SAT}}$ </tex-math></inline-formula>) and power added efficiency (PAE) of 25 W and 26%, respectively, achieving a high power density (<inline-formula> <tex-math>${P} _{mathbf {DEN}}$ </tex-math></inline-formula>) of 2.524.50 W/mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula>. The maximum degradations of <inline-formula> <tex-math>${P} _{mathbf {SAT}}$ </tex-math></inline-formula> and PAE at <inline-formula> <tex-math>$+ 85~^{circ }$ </tex-math></inline-formula>C are 0.7 dB and 3.9%, respectively.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"289-292"},"PeriodicalIF":3.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/LMWT.2025.3625604
Chenghao Wu;Yingmei Chen;Fengming Zuo;En Zhu
This letter presents a 40-GBaud PAM-4 transimpedance amplifier (TIA) integrated with a fully on-chip self-adaptive gain–bandwidth consistency (SA-GBC) loop, fabricated in a 22-nm CMOS process. In contrast to prior solutions that rely on external reference clocks and digital calibration, the proposed design introduces a compact analog feedback loop that continuously regulates the supply voltage of inverter-based gain stages. This approach compensates for bandwidth variations caused by gain changes without requiring any off-chip control or digital interface, significantly reducing the application-level complexity. When the transimpedance is 70 dB$Omega $ , the TIA achieves a −3-dB bandwidth of 33 GHz, a differential output swing of $300~mathbf {mV_{text {ppd}}}$ , and an input-referred noise of 15.4 pA/$mathbf {sqrt {text{Hz}}}$ . The TIA consumes 153 mW and the active area is $0.15~mathbf {mm^{2}}$ . Electrical measurements demonstrate operation up to 40-GBaud PAM-4 signaling. Compared with the state-of-the-art designs, this work uniquely enables automatic analog gain–bandwidth tracking without digital control, offering a compact and scalable solution for the next-generation optical receivers.
{"title":"A 40-GBaud PAM-4 TIA With a Self-Adaptive Gain–Bandwidth Consistency Loop in 22-nm CMOS","authors":"Chenghao Wu;Yingmei Chen;Fengming Zuo;En Zhu","doi":"10.1109/LMWT.2025.3625604","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3625604","url":null,"abstract":"This letter presents a 40-GBaud PAM-4 transimpedance amplifier (TIA) integrated with a fully on-chip self-adaptive gain–bandwidth consistency (SA-GBC) loop, fabricated in a 22-nm CMOS process. In contrast to prior solutions that rely on external reference clocks and digital calibration, the proposed design introduces a compact analog feedback loop that continuously regulates the supply voltage of inverter-based gain stages. This approach compensates for bandwidth variations caused by gain changes without requiring any off-chip control or digital interface, significantly reducing the application-level complexity. When the transimpedance is 70 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, the TIA achieves a −3-dB bandwidth of 33 GHz, a differential output swing of <inline-formula> <tex-math>$300~mathbf {mV_{text {ppd}}}$ </tex-math></inline-formula>, and an input-referred noise of 15.4 pA/<inline-formula> <tex-math>$mathbf {sqrt {text{Hz}}}$ </tex-math></inline-formula>. The TIA consumes 153 mW and the active area is <inline-formula> <tex-math>$0.15~mathbf {mm^{2}}$ </tex-math></inline-formula>. Electrical measurements demonstrate operation up to 40-GBaud PAM-4 signaling. Compared with the state-of-the-art designs, this work uniquely enables automatic analog gain–bandwidth tracking without digital control, offering a compact and scalable solution for the next-generation optical receivers.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"277-280"},"PeriodicalIF":3.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/LMWT.2025.3627788
Jeng-Han Tsai;Jia-Hui Huang
This article presents a Ku-/K-band bulk CMOS low-noise amplifier (LNA) for satellite communication RF front end. A power-constrained simultaneous noise and input matching (PCSNIM) technique is adopted for the first common-source (CS) stage to minimize the noise figure (NF) while maintaining low dc power and good input return loss. The second stage, using a neutralized differential CS configuration, is adopted to increase the gain and stability performance. Utilizing a current-reuse technique, the first CS stage and the second differential CS stage can be stacked and share the current from a single supply to further reduce the power consumption of the LNA. Fabricated in 90-nm CMOS technology, the LNA achieves 1.95-dB minimum NF at 18 GHz with low dc power consumption of 3.6 mW. The maximum small signal gain is 16.2 at 20.5 GHz, and the 3-dB bandwidth (BW) is 6.6 GHz from 15.9 to 22.5 GHz. To the best of our knowledge, the presented Ku-/K-band CMOS LNA has low NF, low dc power, and the highest figure of merit (FoM) among recently published Ku-/K-/Ka-band bulk CMOS LNAs.
{"title":"An 18-GHz 1.95-dB NF 3.6-mW CMOS Low-Noise Amplifier for Satellite Communication Applications","authors":"Jeng-Han Tsai;Jia-Hui Huang","doi":"10.1109/LMWT.2025.3627788","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3627788","url":null,"abstract":"This article presents a Ku-/K-band bulk CMOS low-noise amplifier (LNA) for satellite communication RF front end. A power-constrained simultaneous noise and input matching (PCSNIM) technique is adopted for the first common-source (CS) stage to minimize the noise figure (NF) while maintaining low dc power and good input return loss. The second stage, using a neutralized differential CS configuration, is adopted to increase the gain and stability performance. Utilizing a current-reuse technique, the first CS stage and the second differential CS stage can be stacked and share the current from a single supply to further reduce the power consumption of the LNA. Fabricated in 90-nm CMOS technology, the LNA achieves 1.95-dB minimum NF at 18 GHz with low dc power consumption of 3.6 mW. The maximum small signal gain is 16.2 at 20.5 GHz, and the 3-dB bandwidth (BW) is 6.6 GHz from 15.9 to 22.5 GHz. To the best of our knowledge, the presented Ku-/K-band CMOS LNA has low NF, low dc power, and the highest figure of merit (FoM) among recently published Ku-/K-/Ka-band bulk CMOS LNAs.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"257-260"},"PeriodicalIF":3.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a novel integrated bandpass filtering power amplifier (FPA) structure using a compact asymmetrical filtering coupled resonator (AFCR) matching network. Unlike traditional CMOS FPA designs that rely on transformers with LC notch filters, the proposed AFCR matching method leverages the advantage of introducing two transmission zeros (TZs) without adding additional inductors. The AFCR achieves high-$Q$ filtering with high selectivity in both the lower and upper stopbands while maintaining a compact layout footprint, thereby saving chip area and reducing insertion loss. For verification, a two-stage $K$ -band FPA is designed and fabricated in 180-nm CMOS process with a core area of 0.42 mm2. The measurement results demonstrate 50.5-/41.4-dBc stopband rejection, 19.1-dBm Psat, and 17.0% PAE at 22 GHz. For single-carrier 100-MHz 64-QAM signals without digital predistortion (DPD), the measured Pavg of 13.5 dBm and ACLR of −30.0 dBc at 22 GHz are achieved at an EVM level of −25.2 dB.
{"title":"A K-Band CMOS High-Selectivity Power Amplifier With Compact Asymmetrical Filtering Coupled Resonator Network","authors":"Zhuoyin Chen;Yongle Wu;Xiaopan Chen;Moushu Yang;Shuchen Zhen;Xinyu Zhang;Weimin Wang;Quan Xue","doi":"10.1109/LMWT.2025.3627790","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3627790","url":null,"abstract":"This letter presents a novel integrated bandpass filtering power amplifier (FPA) structure using a compact asymmetrical filtering coupled resonator (AFCR) matching network. Unlike traditional CMOS FPA designs that rely on transformers with LC notch filters, the proposed AFCR matching method leverages the advantage of introducing two transmission zeros (TZs) without adding additional inductors. The AFCR achieves high-<inline-formula> <tex-math>$Q$ </tex-math></inline-formula> filtering with high selectivity in both the lower and upper stopbands while maintaining a compact layout footprint, thereby saving chip area and reducing insertion loss. For verification, a two-stage <inline-formula> <tex-math>$K$ </tex-math></inline-formula>-band FPA is designed and fabricated in 180-nm CMOS process with a core area of 0.42 mm<sup>2</sup>. The measurement results demonstrate 50.5-/41.4-dBc stopband rejection, 19.1-dBm P<sub>sat</sub>, and 17.0% PAE at 22 GHz. For single-carrier 100-MHz 64-QAM signals without digital predistortion (DPD), the measured P<sub>avg</sub> of 13.5 dBm and ACLR of −30.0 dBc at 22 GHz are achieved at an EVM level of −25.2 dB.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"261-264"},"PeriodicalIF":3.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/LMWT.2025.3625179
Xiangdong Wang;Mo Li;Heng Xie;Yang Liu;Jian Zhang
This letter presents a compact 6–18-GHz 6-bit GaAs digital phase shifter (DPS) for broadband large-scale phased array systems. A novel switchable reflection-type (SRT) topology featuring a simplified configuration is proposed to realize a broadband low-loss 180°-bit phase shifting cell (PSC). Furthermore, a reactive phase equalization network (PEN) is adopted to effectively reduce the phase error of 180°-bit PSC. To prove the feasibility of the proposed techniques, a DPS embedded with spiral quadrature couplers (SQCs) is designed, fabricated, and measured. The die area of the presented DPS is merely 2.55 mm2 ($1.7times 1.5$ mm). The DPS exhibits a low insertion loss (IL) of 6.38.8 dB. Root-mean-square magnitude and phase errors are 0.350.72 dB and 0.84°–2.1° for six main states, respectively. Compared with previously reported GaAs DPSs, this work exhibits superb figure-of-merits (FOMs) in the smallest die size.
{"title":"A Compact Broadband 6-bit Digital Phase Shifter Using Novel Switchable Reflection-Type Topology","authors":"Xiangdong Wang;Mo Li;Heng Xie;Yang Liu;Jian Zhang","doi":"10.1109/LMWT.2025.3625179","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3625179","url":null,"abstract":"This letter presents a compact 6–18-GHz 6-bit GaAs digital phase shifter (DPS) for broadband large-scale phased array systems. A novel switchable reflection-type (SRT) topology featuring a simplified configuration is proposed to realize a broadband low-loss 180°-bit phase shifting cell (PSC). Furthermore, a reactive phase equalization network (PEN) is adopted to effectively reduce the phase error of 180°-bit PSC. To prove the feasibility of the proposed techniques, a DPS embedded with spiral quadrature couplers (SQCs) is designed, fabricated, and measured. The die area of the presented DPS is merely 2.55 mm<sup>2</sup> (<inline-formula> <tex-math>$1.7times 1.5$ </tex-math></inline-formula> mm). The DPS exhibits a low insertion loss (IL) of 6.38.8 dB. Root-mean-square magnitude and phase errors are 0.350.72 dB and 0.84°–2.1° for six main states, respectively. Compared with previously reported GaAs DPSs, this work exhibits superb figure-of-merits (FOMs) in the smallest die size.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"309-312"},"PeriodicalIF":3.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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