This letter presents a novel design method for wideband low-noise amplifiers (LNAs), which decouples the realization procedure of input noise matching, input impedance matching, and gain flatness. The input matching network is designed to realize wideband noise matching. Then, the degeneration inductor and T-type interstage matching network with magnetic coupling are employed to meet the required range of the interstage impedance mismatch level to achieve wide input impedance bandwidth. The gain bandwidth is enhanced by designing the impedance mismatch related to output matching network, without affecting the input matching. For demonstration, a three-stage E-/W-band LNA has been implemented using a 0.13-$mu $ m SiGe BiCMOS technology. The LNA achieves a peak gain of 24.1 dB with a 3-dB gain bandwidth of 53 GHz, less than −10-dB $vert S_{11} vert $ bandwidth of 50 GHz, and a low noise figure (NF) ranging from 3.8 to 6.9 dB across the W-band, while consuming power of 23 mW.
{"title":"A 57–110-GHz LNA With Novel Bandwidth Enhancement Technique in 130-nm SiGe BiCMOS","authors":"Zhan Chen;Chun-Xia Zhou;Guoxiao Cheng;Wei Kang;Wen Wu;Zhou Shu;Yongxin Guo","doi":"10.1109/LMWT.2025.3627232","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3627232","url":null,"abstract":"This letter presents a novel design method for wideband low-noise amplifiers (LNAs), which decouples the realization procedure of input noise matching, input impedance matching, and gain flatness. The input matching network is designed to realize wideband noise matching. Then, the degeneration inductor and T-type interstage matching network with magnetic coupling are employed to meet the required range of the interstage impedance mismatch level to achieve wide input impedance bandwidth. The gain bandwidth is enhanced by designing the impedance mismatch related to output matching network, without affecting the input matching. For demonstration, a three-stage E-/W-band LNA has been implemented using a 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe BiCMOS technology. The LNA achieves a peak gain of 24.1 dB with a 3-dB gain bandwidth of 53 GHz, less than −10-dB <inline-formula> <tex-math>$vert S_{11} vert $ </tex-math></inline-formula> bandwidth of 50 GHz, and a low noise figure (NF) ranging from 3.8 to 6.9 dB across the W-band, while consuming power of 23 mW.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2113-2116"},"PeriodicalIF":3.4,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1109/LMWT.2025.3624146
Areeba Ahsan;M. Jaleel Akhtar
This work presents a fast, optimization-based synthesis approach to design compact broadband matching networks (MNs) using continuously varying impedance lines (CVILs). The impedance profile of the CVIL is modeled using a truncated Fourier series, whose coefficients are directly optimized to minimize impedance mismatch over the desired bandwidth. Unlike conventional stepped or discrete matching approaches, the proposed method yields a smooth impedance transition that mitigates abrupt discontinuities and associated parasitic effects. Practical fabrication constraints and substrate losses are directly incorporated into the optimization, thereby enabling electromagnetic (EM)-accurate designs from inception without requiring postlayout tuning. The applicability of the proposed scheme is validated through the design, fabrication, and testing of a 0.5–3.0 GHz Class-AB amplifier, which achieves $11.1~pm ~0.2$ dB gain, 52%–62% power-added efficiency (PAE), and an output power of $23.1~pm ~0.2$ dBm across the band. These results demonstrate that the proposed CVIL-based technique offers an efficient and versatile alternative for broadband and multiband RF amplifier design.
{"title":"Synthesis of Broadband RF Amplifier Matching Networks Using Continuously Varying Impedance Lines","authors":"Areeba Ahsan;M. Jaleel Akhtar","doi":"10.1109/LMWT.2025.3624146","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3624146","url":null,"abstract":"This work presents a fast, optimization-based synthesis approach to design compact broadband matching networks (MNs) using continuously varying impedance lines (CVILs). The impedance profile of the CVIL is modeled using a truncated Fourier series, whose coefficients are directly optimized to minimize impedance mismatch over the desired bandwidth. Unlike conventional stepped or discrete matching approaches, the proposed method yields a smooth impedance transition that mitigates abrupt discontinuities and associated parasitic effects. Practical fabrication constraints and substrate losses are directly incorporated into the optimization, thereby enabling electromagnetic (EM)-accurate designs from inception without requiring postlayout tuning. The applicability of the proposed scheme is validated through the design, fabrication, and testing of a 0.5–3.0 GHz Class-AB amplifier, which achieves <inline-formula> <tex-math>$11.1~pm ~0.2$ </tex-math></inline-formula> dB gain, 52%–62% power-added efficiency (PAE), and an output power of <inline-formula> <tex-math>$23.1~pm ~0.2$ </tex-math></inline-formula> dBm across the band. These results demonstrate that the proposed CVIL-based technique offers an efficient and versatile alternative for broadband and multiband RF amplifier design.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"273-276"},"PeriodicalIF":3.4,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes a low-noise monolithically integrated 80-Gbps PAM4 optical receiver using multidrive noise cancellation technique. The proposed receiver integrates a multidrive noise-canceling transimpedance stage (MDNC-TIS), a CML-based differential postamplifier, auxiliary analog loops, and a PD on a single chip. The proposed MDNC-TIS comprises a shunt-feedback transimpedance stage (SF-TIS) followed by a multidrive common-source (MD-CS) stage, which reduces transimpedance amplifier (TIA) noise through noise cancellation mechanism. Additionally, the MDNC-TIS demonstrates a gain enhancement which effectively mitigates the noise impact on postamplifier stages. The optical receiver is implemented in a 45-nm CMOS SOI-photonic process. Measurement results show that the realized TIA achieves 64.5 dB$Omega $ transimpedance gain and 28.5-GHz bandwidth with 9.4-pA/$surd $ Hz input-referred noise current density. The opto-electrical time-domain measurement results indicate that the implemented optical receiver chip achieves sensitivity of −9.64 dBm for 80 Gbps PAM4 signal at 2.4E–4 bit error rate (BER) with 0.9 A/W responsivity of PD.
{"title":"A 9.4-pA/√Hz Monolithically Integrated Optical Receiver Using Multidrive Noise Cancellation Technique in 45-nm CMOS SOI-Photonic Process","authors":"Jian Li;Xiaojun Bi;Changyu Hu;Jinxuan Jin;Zhao Bo;Jun Liu;Qichao Ding;Qinfen Xu","doi":"10.1109/LMWT.2025.3624303","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3624303","url":null,"abstract":"This article proposes a low-noise monolithically integrated 80-Gbps PAM4 optical receiver using multidrive noise cancellation technique. The proposed receiver integrates a multidrive noise-canceling transimpedance stage (MDNC-TIS), a CML-based differential postamplifier, auxiliary analog loops, and a PD on a single chip. The proposed MDNC-TIS comprises a shunt-feedback transimpedance stage (SF-TIS) followed by a multidrive common-source (MD-CS) stage, which reduces transimpedance amplifier (TIA) noise through noise cancellation mechanism. Additionally, the MDNC-TIS demonstrates a gain enhancement which effectively mitigates the noise impact on postamplifier stages. The optical receiver is implemented in a 45-nm CMOS SOI-photonic process. Measurement results show that the realized TIA achieves 64.5 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> transimpedance gain and 28.5-GHz bandwidth with 9.4-pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz input-referred noise current density. The opto-electrical time-domain measurement results indicate that the implemented optical receiver chip achieves sensitivity of −9.64 dBm for 80 Gbps PAM4 signal at 2.4E–4 bit error rate (BER) with 0.9 A/W responsivity of PD.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"285-288"},"PeriodicalIF":3.4,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents an interlaboratory comparison of multiline thru-reflect-line (mTRL) on-wafer calibrations on a commercial high-resistivity silicon (HRSi) substrate at D-band frequencies (110–170 GHz). Two national metrology institutes (KRISS and PTB) measured identical calibration structures using the same probe types and techniques, enabling an in-depth analysis of spatial measurement variation and reproducibility between laboratories. Overall, the results demonstrate high consistency with repeatable measurements achieved by different operators and over multiple months, showing negligible drift and affirming the stability of the calibration process. These findings demonstrate that, when best practices are followed, on-wafer calibrations on HRSi substrates can be reliably transferred between laboratories, with residual differences being attributable to known parasitic effects and boundary-condition influences.
{"title":"Interlaboratory Comparison of Commercial High-Resistivity Silicon Calibration Substrate at D-Band","authors":"Hyunji Koo;Gia Ngoc Phung;Uwe Arz;Chihyun Cho;Jae-Yong Kwon","doi":"10.1109/LMWT.2025.3625538","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3625538","url":null,"abstract":"This article presents an interlaboratory comparison of multiline thru-reflect-line (mTRL) on-wafer calibrations on a commercial high-resistivity silicon (HRSi) substrate at D-band frequencies (110–170 GHz). Two national metrology institutes (KRISS and PTB) measured identical calibration structures using the same probe types and techniques, enabling an in-depth analysis of spatial measurement variation and reproducibility between laboratories. Overall, the results demonstrate high consistency with repeatable measurements achieved by different operators and over multiple months, showing negligible drift and affirming the stability of the calibration process. These findings demonstrate that, when best practices are followed, on-wafer calibrations on HRSi substrates can be reliably transferred between laboratories, with residual differences being attributable to known parasitic effects and boundary-condition influences.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 12","pages":"2129-2132"},"PeriodicalIF":3.4,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224371","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145766215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1109/LMWT.2025.3624700
Bo Shao;Yang Li;Kunzhe Zhang;Renpin Huang;Junchao Yao;Tao Liu;Haoyuan Sun;Zhangcheng Liu;Zhiwei Chen;Jie You;Xiao Wang;Jinping Ao
This letter presents a thorough analysis of the extended continuous Class-B/J mode theory, incorporating a second-harmonic input component. By establishing the relationship between the input and output waveforms, the relationships between output power, drain efficiency (DE), and the input nonlinearity factor can be derived. Compared with conventional continuous Class-B/J mode, an impedance design space enabling concurrent input/output control is obtained, providing guidance for the design of broadband high-efficiency power amplifiers (PAs). To validate the proposed theory, a broadband PA operating from 1.5 to 2.55 GHz is designed and fabricated. Measurement results demonstrate a DE of 69.2%–79.5%, an output power of 39.3–42.5 dBm, and a power gain of 9.0–14.3 dB across the design bandwidth, demonstrating its effectiveness.
{"title":"Design of Extended Continuous Class B/J Wideband High-Efficiency Power Amplifier With Input and Output Waveform Engineering","authors":"Bo Shao;Yang Li;Kunzhe Zhang;Renpin Huang;Junchao Yao;Tao Liu;Haoyuan Sun;Zhangcheng Liu;Zhiwei Chen;Jie You;Xiao Wang;Jinping Ao","doi":"10.1109/LMWT.2025.3624700","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3624700","url":null,"abstract":"This letter presents a thorough analysis of the extended continuous Class-B/J mode theory, incorporating a second-harmonic input component. By establishing the relationship between the input and output waveforms, the relationships between output power, drain efficiency (DE), and the input nonlinearity factor can be derived. Compared with conventional continuous Class-B/J mode, an impedance design space enabling concurrent input/output control is obtained, providing guidance for the design of broadband high-efficiency power amplifiers (PAs). To validate the proposed theory, a broadband PA operating from 1.5 to 2.55 GHz is designed and fabricated. Measurement results demonstrate a DE of 69.2%–79.5%, an output power of 39.3–42.5 dBm, and a power gain of 9.0–14.3 dB across the design bandwidth, demonstrating its effectiveness.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"269-272"},"PeriodicalIF":3.4,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents the RF design and experimental validation of a codesigned wideband filtering amplifier that simultaneously achieves flat in-band gain, high reverse isolation, and low noise figure (NF). The proposed architecture incorporates a wideband unilateral frequency-selective gain stage (UFGS) featuring resistive transmission-line (TL) feedback to suppress its reverse transmission while maintaining high gain and low NF. The UFGS is codesigned with coupled-line sections and open-circuited stubs to enable wideband filtering characteristics and multiple transmission zeros (TZs) for enhanced selectivity and out-of-band rejection. A step-by-step practical design procedure is also developed following conventional coupled-resonator design principles. For experimental validation purposes, a filtering amplifier prototype was manufactured and tested at 2.13 GHz, demonstrating a 3-dB fractional bandwidth (FBW) of 72% and a flat-gain bandwidth (FGBW) of 66%, along with a wide upper stopband spanning 3.1–5.5 GHz. Additionally, it achieves 15-dB peak gain, 55-dB directivity, 1.9-dB NF, 4.2-dBm output 1-dB compression point, and 16-dBm output third-order intercept point at the center frequency.
{"title":"Codesigned Wideband Filtering Amplifier With High Reverse Isolation Using Unilateral Frequency-Selective Gain Stage","authors":"Kexin Li;Photos Vryonides;Symeon Nikolaou;Dimitra Psychogiou","doi":"10.1109/LMWT.2025.3625432","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3625432","url":null,"abstract":"This letter presents the RF design and experimental validation of a codesigned wideband filtering amplifier that simultaneously achieves flat in-band gain, high reverse isolation, and low noise figure (NF). The proposed architecture incorporates a wideband unilateral frequency-selective gain stage (UFGS) featuring resistive transmission-line (TL) feedback to suppress its reverse transmission while maintaining high gain and low NF. The UFGS is codesigned with coupled-line sections and open-circuited stubs to enable wideband filtering characteristics and multiple transmission zeros (TZs) for enhanced selectivity and out-of-band rejection. A step-by-step practical design procedure is also developed following conventional coupled-resonator design principles. For experimental validation purposes, a filtering amplifier prototype was manufactured and tested at 2.13 GHz, demonstrating a 3-dB fractional bandwidth (FBW) of 72% and a flat-gain bandwidth (FGBW) of 66%, along with a wide upper stopband spanning 3.1–5.5 GHz. Additionally, it achieves 15-dB peak gain, 55-dB directivity, 1.9-dB NF, 4.2-dBm output 1-dB compression point, and 16-dBm output third-order intercept point at the center frequency.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"249-252"},"PeriodicalIF":3.4,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223056","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a novel broadband high-efficiency continuous inverse class-F (CCF–1) mode monolithic microwave integrated circuit (MMIC) power amplifier (PA) based on the drain current waveform amplitude scaling factor $lambda $ . To minimize the current clipping and efficiency reduction caused by the reactive extension parameter [$1-gamma $ sin($theta $ )] in CCF–1 when $vert gamma vert gt 0.5$ , a modified maximum efficiency admittance boundary can be determined at $vert gamma vert gt 0.5$ through theoretical analysis of the impact of $lambda $ on CCF–1 performance. A load-pull simulation is carried out to verify this theoretical result. Furthermore, a GaN-on-Si MMIC PA operating over 1.6−3 GHz is designed and fabricated based on proposed method. The measurement results show a drain efficiency (DE) of 52%−69% and an output power (Pout) of 34.8−36.6 dBm. When tested with a 100 MHz 64-quadrature amplitude modulation (QAM) signal at 2.4 GHz with an average Pout (Pavg) of 30 dBm, the PA achieves an adjacent channel power (ACPR), ratio (ACPR) of −35.3 dBc with a 32.6% average DE (DEavg) without using digital predistortion (DPD).
本文提出了一种基于漏极电流波形幅度比例因子$lambda $的新型宽带高效连续反f类（CCF-1）模式单片微波集成电路（MMIC）功率放大器（PA）。为了最大限度地减少$vert gamma vert gt 0.5$时CCF-1中反应性扩展参数[$1-gamma $ sin($theta $)]造成的电流剪切和效率降低，可以通过理论分析$lambda $对CCF-1性能的影响，在$vert gamma vert gt 0.5$处确定修正后的最大效率导纳边界。通过负载-拉力仿真验证了这一理论结果。在此基础上，设计并制作了工作频率为1.6−3 GHz的GaN-on-Si MMIC放大器。测量结果表明，漏极效率（DE）为52%−69% and an output power (Pout) of 34.8−36.6 dBm. When tested with a 100 MHz 64-quadrature amplitude modulation (QAM) signal at 2.4 GHz with an average Pout (Pavg) of 30 dBm, the PA achieves an adjacent channel power (ACPR), ratio (ACPR) of −35.3 dBc with a 32.6% average DE (DEavg) without using digital predistortion (DPD).
{"title":"A High-Efficiency Fully Integrated GaN-on-Si Power Amplifier Using Drain Current Scaling Factor","authors":"Chupeng Yi;Xin Liu;Lang Tong;Ziyue Zhao;Ting Feng;Dawei Zhang;Jiejie Zhu;Yang Lu;Xiaohua Ma;Yue Hao","doi":"10.1109/LMWT.2025.3625224","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3625224","url":null,"abstract":"This letter presents a novel broadband high-efficiency continuous inverse class-F (CCF<sup>–1</sup>) mode monolithic microwave integrated circuit (MMIC) power amplifier (PA) based on the drain current waveform amplitude scaling factor <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>. To minimize the current clipping and efficiency reduction caused by the reactive extension parameter [<inline-formula> <tex-math>$1-gamma $ </tex-math></inline-formula> sin(<inline-formula> <tex-math>$theta $ </tex-math></inline-formula>)] in CCF<sup>–1</sup> when <inline-formula> <tex-math>$vert gamma vert gt 0.5$ </tex-math></inline-formula>, a modified maximum efficiency admittance boundary can be determined at <inline-formula> <tex-math>$vert gamma vert gt 0.5$ </tex-math></inline-formula> through theoretical analysis of the impact of <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula> on CCF<sup>–1</sup> performance. A load-pull simulation is carried out to verify this theoretical result. Furthermore, a GaN-on-Si MMIC PA operating over 1.6−3 GHz is designed and fabricated based on proposed method. The measurement results show a drain efficiency (DE) of 52%−69% and an output power (Pout) of 34.8−36.6 dBm. When tested with a 100 MHz 64-quadrature amplitude modulation (QAM) signal at 2.4 GHz with an average Pout (P<sub>avg</sub>) of 30 dBm, the PA achieves an adjacent channel power (ACPR), ratio (ACPR) of −35.3 dBc with a 32.6% average DE (DE<sub>avg</sub>) without using digital predistortion (DPD).","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"297-300"},"PeriodicalIF":3.4,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1109/LMWT.2025.3623400
Eunsu Mo;Wonseob Lee;Euijin Oh;Subin Lim;Seunghun Wang;Hui-Dong Lee;Bonghyuk Park;Seungchan Lee;Jinseok Park
This letter presents a Ku-band power combining amplifier (PCA) using the 65-nm CMOS process. Because of the large size of the pi-network used in Wilkinson combiners, a transformer (TF)-based series combining method was employed to achieve a more compact design, reducing insertion loss and maximizing the power amplifier (PA)’s performance. A parallel combining topology enables a symmetric TF design, whereas a series combining topology inherently results in an asymmetric structure, leading to unavoidable phase and gain imbalance between two signals. To mitigate this issue, we propose an asymmetric in-phase TF-based power combiner that minimizes phase imbalance between two PAs and to improve output power and efficiency. The designed PA demonstrates a saturation output power ($P_{mathrm {sat}}$ ) of 26.3 dBm, peak power-added efficiency (PAE) of 30.3%, and P1dB of 25 dBm at 16 GHz. Also, the phase imbalance between the two power stages to the output was improved from 15° to 2°. The proposed PA delivers a linear output power of 19.5 dBm under a 5G NR FR2 100-MHz 64-QAM signal, demonstrating its suitability for high-linearity applications.
本文介绍了一种采用65纳米CMOS工艺的ku波段功率组合放大器（PCA）。由于Wilkinson合成器中使用的pi网络规模较大，因此采用基于变压器（TF）的串联合成器实现更紧凑的设计，减少插入损耗，最大限度地提高功率放大器（PA）的性能。并联组合拓扑可以实现对称的TF设计，而串联组合拓扑本质上导致不对称结构，导致两个信号之间不可避免的相位和增益不平衡。为了缓解这一问题，我们提出了一种基于非对称同相tf的功率合成器，该合成器可以最大限度地减少两个pa之间的相位不平衡，并提高输出功率和效率。所设计的放大器在16 GHz时的饱和输出功率为26.3 dBm，峰值功率附加效率（PAE）为30.3%，P1dB为25 dBm。同时，两个功率级之间的相位不平衡从15°改善到2°。该放大器在5G NR FR2 100-MHz 64-QAM信号下提供19.5 dBm的线性输出功率，证明其适用于高线性应用。
{"title":"A Ku-Band CMOS Two-Way In-Phase Power Combining Amplifier With 26.3-dBm Psat and 1.1° AM–PM Distortion","authors":"Eunsu Mo;Wonseob Lee;Euijin Oh;Subin Lim;Seunghun Wang;Hui-Dong Lee;Bonghyuk Park;Seungchan Lee;Jinseok Park","doi":"10.1109/LMWT.2025.3623400","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3623400","url":null,"abstract":"This letter presents a Ku-band power combining amplifier (PCA) using the 65-nm CMOS process. Because of the large size of the pi-network used in Wilkinson combiners, a transformer (TF)-based series combining method was employed to achieve a more compact design, reducing insertion loss and maximizing the power amplifier (PA)’s performance. A parallel combining topology enables a symmetric TF design, whereas a series combining topology inherently results in an asymmetric structure, leading to unavoidable phase and gain imbalance between two signals. To mitigate this issue, we propose an asymmetric in-phase TF-based power combiner that minimizes phase imbalance between two PAs and to improve output power and efficiency. The designed PA demonstrates a saturation output power (<inline-formula> <tex-math>$P_{mathrm {sat}}$ </tex-math></inline-formula>) of 26.3 dBm, peak power-added efficiency (PAE) of 30.3%, and <italic>P</i><sub>1dB</sub> of 25 dBm at 16 GHz. Also, the phase imbalance between the two power stages to the output was improved from 15° to 2°. The proposed PA delivers a linear output power of 19.5 dBm under a 5G NR FR2 100-MHz 64-QAM signal, demonstrating its suitability for high-linearity applications.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"265-268"},"PeriodicalIF":3.4,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/LMWT.2025.3623604
Peiyi Yu;Yongqiang Wang;Jianquan Hu;Kaixue Ma
This letter presents the first demonstration of a high-efficiency Class-F power amplifier (PA) implemented on a metal-integrated suspended line (MISL) platform. To mitigate the detrimental effects of parasitic elements inherent in the transistor, a compensation network designed from the device’s parasitic model is integrated. This approach enables precise harmonic impedance control at the intrinsic current source plane, thereby enhancing design flexibility and improving PA performance. Experimental results show that the proposed MISL-based Class-F PA achieves a peak power gain of 11.7 dB and a peak drain efficiency (DE) of 79% within the 3.2–3.4-GHz band. These results highlight the potential of MISL technology for PA applications, offering the advantages of low loss, good heat dissipation, and self-packaging.
{"title":"A High-Efficiency Class-F PA Utilizing Parasitic Compensation Based on Metal-Integrated Suspended Line (MISL) Platform","authors":"Peiyi Yu;Yongqiang Wang;Jianquan Hu;Kaixue Ma","doi":"10.1109/LMWT.2025.3623604","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3623604","url":null,"abstract":"This letter presents the first demonstration of a high-efficiency Class-F power amplifier (PA) implemented on a metal-integrated suspended line (MISL) platform. To mitigate the detrimental effects of parasitic elements inherent in the transistor, a compensation network designed from the device’s parasitic model is integrated. This approach enables precise harmonic impedance control at the intrinsic current source plane, thereby enhancing design flexibility and improving PA performance. Experimental results show that the proposed MISL-based Class-F PA achieves a peak power gain of 11.7 dB and a peak drain efficiency (DE) of 79% within the 3.2–3.4-GHz band. These results highlight the potential of MISL technology for PA applications, offering the advantages of low loss, good heat dissipation, and self-packaging.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"293-296"},"PeriodicalIF":3.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, we propose a third-order parity-time symmetric wireless power transfer (PTS-WPT) system with constant current (CC) and constant voltage (CV) output capabilities. The proposed system eliminates the need for bilateral communication and additional dc–dc converter control and is capable of providing stable charging services for a wider battery load range at a constant operating frequency, while increasing the transfer distance. To validate the proposed PTS-WPT system, we built an experimental prototype with an output specification of 2 A/24 V, and the measured results show that the system can stably maintain CC and CV outputs over a transmission distance range of 26–34 cm and a battery equivalent resistance range of 6–$30~Omega $ .
{"title":"A Third-Order Parity-Time Symmetric Wireless Charging System With CC and CV Output","authors":"Xujian Shu;Wenzhen He;Jingjing Yang;Bo Zhang;Yanwei Jiang","doi":"10.1109/LMWT.2025.3624243","DOIUrl":"https://doi.org/10.1109/LMWT.2025.3624243","url":null,"abstract":"In this letter, we propose a third-order parity-time symmetric wireless power transfer (PTS-WPT) system with constant current (CC) and constant voltage (CV) output capabilities. The proposed system eliminates the need for bilateral communication and additional dc–dc converter control and is capable of providing stable charging services for a wider battery load range at a constant operating frequency, while increasing the transfer distance. To validate the proposed PTS-WPT system, we built an experimental prototype with an output specification of 2 A/24 V, and the measured results show that the system can stably maintain CC and CV outputs over a transmission distance range of 26–34 cm and a battery equivalent resistance range of 6–<inline-formula> <tex-math>$30~Omega $ </tex-math></inline-formula>.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"36 2","pages":"281-284"},"PeriodicalIF":3.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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