Pub Date : 2024-06-24DOI: 10.1109/LMWT.2024.3414598
Yijing Wang;Xinbo He;Bin Wei
This letter presents a parallel frequency-domain finite-difference (FDFD) algorithm based on multi-graphic processing unit (GPU) applied to electromagnetic scattering computations to enhance the computational efficiency of the algorithm. The proposed algorithm parallelizes the solution of large-scale sparse matrices, distributing threads to the matrix-vector and vector-vector multiplication operations within decomposed sub-matrices to reduce the computational time. Moreover, we configure the OpenMP to optimize communication transfer between multiple GPUs, thereby improving computational efficiency. The simulation results show that compared with the conventional FDFD method, the proposed algorithm can enhance computational efficiency while ensuring accuracy.
{"title":"A New Parallel Frequency-Domain Finite-Difference Algorithm Using Multi-GPU","authors":"Yijing Wang;Xinbo He;Bin Wei","doi":"10.1109/LMWT.2024.3414598","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3414598","url":null,"abstract":"This letter presents a parallel frequency-domain finite-difference (FDFD) algorithm based on multi-graphic processing unit (GPU) applied to electromagnetic scattering computations to enhance the computational efficiency of the algorithm. The proposed algorithm parallelizes the solution of large-scale sparse matrices, distributing threads to the matrix-vector and vector-vector multiplication operations within decomposed sub-matrices to reduce the computational time. Moreover, we configure the OpenMP to optimize communication transfer between multiple GPUs, thereby improving computational efficiency. The simulation results show that compared with the conventional FDFD method, the proposed algorithm can enhance computational efficiency while ensuring accuracy.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"971-974"},"PeriodicalIF":0.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A millimeter-wave CMOS active vector-sum phase shifter (VSPS) with a phase resolution of 5.625° using a two-stage transformer-based resistor and inductor (RL) polyphase filter (PPF) for generating wideband in-phase/quadrature (I/Q) signals is proposed. Theoretical analysis demonstrates that the inductors in RL PPF can resonate with the capacitive loads to boost the passive voltage gain and alleviate the issue of high loss in the traditional RC PPF. Furthermore, the RL PPF provides a larger bandwidth and a better tolerance to process variations. An active VSPS prototype incorporating the proposed RL PPF is implemented in 65-nm CMOS process. The measured results of the phase shifter show a maximum insertion gain of −2.28 dB with a maximum power consumption of 20.52 mW. The measured root-mean-square (rms) phase error and gain error over the 360° phase shifting range are 0.71°–2.95° and 0.67–0.76 dB, respectively, from 20 to 30 GHz (FBW =40%). The core size is 0.238 mm2.
{"title":"A Wideband CMOS Active Phase Shifter Using a Transformer-Based RL Polyphase Filter","authors":"Taotao Xu;Ke Long;Haoshen Zhu;Cao Wan;Shuai Deng;Pei Qin;Wenquan Che;Quan Xue","doi":"10.1109/LMWT.2024.3413861","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3413861","url":null,"abstract":"A millimeter-wave CMOS active vector-sum phase shifter (VSPS) with a phase resolution of 5.625° using a two-stage transformer-based resistor and inductor (RL) polyphase filter (PPF) for generating wideband in-phase/quadrature (I/Q) signals is proposed. Theoretical analysis demonstrates that the inductors in RL PPF can resonate with the capacitive loads to boost the passive voltage gain and alleviate the issue of high loss in the traditional RC PPF. Furthermore, the RL PPF provides a larger bandwidth and a better tolerance to process variations. An active VSPS prototype incorporating the proposed RL PPF is implemented in 65-nm CMOS process. The measured results of the phase shifter show a maximum insertion gain of −2.28 dB with a maximum power consumption of 20.52 mW. The measured root-mean-square (rms) phase error and gain error over the 360° phase shifting range are 0.71°–2.95° and 0.67–0.76 dB, respectively, from 20 to 30 GHz (FBW =40%). The core size is 0.238 mm2.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"1015-1018"},"PeriodicalIF":0.0,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/LMWT.2024.3403950
Van-Son Trinh;Jeong-Moon Song;Jung-Dong Park
We present a D-band eight-way power amplifier (PA), which achieves the saturated output power ( $P_{mathrm {sat}}$ ) of 16.5 dBm in 40-nm bulk CMOS. The proposed D-band PA consists of four push-pull PA units with three stages, whose active device sizes are gradually tapered from the output to the input optimal power efficiency. A cascaded transformer-transformer (balun) structure was employed at the output of the PA unit to avoid self-resonance with an improved balun performance at the D-band. The power combiner/splitter is comprised of microstrip transmission lines (MSTLs) to combine the power of the four PA units in the current domain. The fabricated prototype has a chip size of 0.72 mm2 with a core size of 0.46-mm2 excluding pads. The measured PA achieved a power gain of 14.5 dB with the 3-dB gain bandwidth of 18 GHz (121–139 GHz), a peak PAE of 7.2%, and a saturated output power ( $P_{mathrm {sat}}$ ) of 16.5 dBm, which demonstrates the highest output power among the recently reported D-band PAs in bulk CMOS.
我们提出了一种 D 波段八路功率放大器 (PA)，它能在 40-nm 块状 CMOS 中实现 16.5 dBm 的饱和输出功率（$P_{mathrm {sat}}$）。拟议的 D 波段功率放大器由四个推挽式功率放大器单元组成，共分三级，其有源器件尺寸从输出到输入逐渐减小，以达到最佳功率效率。功率放大器单元的输出端采用了级联变压器-变压器（平衡器）结构，以避免自谐振，从而提高 D 波段的平衡器性能。功率合路器/分路器由微带传输线（MSTL）组成，用于在电流域组合四个功率放大器单元的功率。制作的原型芯片尺寸为 0.72 平方毫米，核心尺寸为 0.46 平方毫米（不包括焊盘）。所测量的功率放大器在 18 GHz（121-139 GHz）的 3-dB 增益带宽下实现了 14.5 dB 的功率增益，峰值 PAE 为 7.2%，饱和输出功率（$P_{mathrm {sat}}$ ）为 16.5 dBm，在最近报道的采用体 CMOS 的 D 波段功率放大器中输出功率最高。
{"title":"A 16.5-dBm D-Band Eight-Way Power Amplifier Utilizing Cascaded Transformers in 40-nm Bulk CMOS","authors":"Van-Son Trinh;Jeong-Moon Song;Jung-Dong Park","doi":"10.1109/LMWT.2024.3403950","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3403950","url":null,"abstract":"We present a D-band eight-way power amplifier (PA), which achieves the saturated output power (\u0000<inline-formula> <tex-math>$P_{mathrm {sat}}$ </tex-math></inline-formula>\u0000) of 16.5 dBm in 40-nm bulk CMOS. The proposed D-band PA consists of four push-pull PA units with three stages, whose active device sizes are gradually tapered from the output to the input optimal power efficiency. A cascaded transformer-transformer (balun) structure was employed at the output of the PA unit to avoid self-resonance with an improved balun performance at the D-band. The power combiner/splitter is comprised of microstrip transmission lines (MSTLs) to combine the power of the four PA units in the current domain. The fabricated prototype has a chip size of 0.72 mm2 with a core size of 0.46-mm2 excluding pads. The measured PA achieved a power gain of 14.5 dB with the 3-dB gain bandwidth of 18 GHz (121–139 GHz), a peak PAE of 7.2%, and a saturated output power (\u0000<inline-formula> <tex-math>$P_{mathrm {sat}}$ </tex-math></inline-formula>\u0000) of 16.5 dBm, which demonstrates the highest output power among the recently reported D-band PAs in bulk CMOS.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"1019-1022"},"PeriodicalIF":0.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a tunable Nolen matrix with small phase tuning range phase shifters and simple control is presented. The proposed circuit topology is constructed from $3times 3$ Nolen matrix embedded with three tunable phase shifters with small tuning range of 0°–120°. For each input port excitation in this proposed network, a continuous 120° tunable progressive phase difference is obtained at the output ports, and the full 360° tunable phase progression is achieved by exciting all three input ports. Most importantly, all tuning range relaxed phase shifters are controlled simultaneously by only two-channel dc voltages to achieve full progressive phase tuning range, which can simplify the control method of beam steering. Compared to the conventional feeding matrix, the proposed design achieves a flexible progressive phase, compact size, easy control, and low power consumption. The theoretical analysis is carried out for the proposed circuit topology, and the closed-form equations are derived to minimize the phase shifter’s tuning range and reduce the control complexity. To verify the proposed design concept, a prototype tunable Nolen matrix operating at 5.8 GHz is designed and tested, and the experimental results agree well with simulation and theoretical analysis.
{"title":"Tunable 3 × 3 Nolen Matrix Network for Power-Saving Phased Array","authors":"Hanxiang Zhang;Han Ren;Powei Liu;Hao Yan;Bayaner Arigong","doi":"10.1109/LMWT.2024.3413721","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3413721","url":null,"abstract":"In this article, a tunable Nolen matrix with small phase tuning range phase shifters and simple control is presented. The proposed circuit topology is constructed from \u0000<inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula>\u0000 Nolen matrix embedded with three tunable phase shifters with small tuning range of 0°–120°. For each input port excitation in this proposed network, a continuous 120° tunable progressive phase difference is obtained at the output ports, and the full 360° tunable phase progression is achieved by exciting all three input ports. Most importantly, all tuning range relaxed phase shifters are controlled simultaneously by only two-channel dc voltages to achieve full progressive phase tuning range, which can simplify the control method of beam steering. Compared to the conventional feeding matrix, the proposed design achieves a flexible progressive phase, compact size, easy control, and low power consumption. The theoretical analysis is carried out for the proposed circuit topology, and the closed-form equations are derived to minimize the phase shifter’s tuning range and reduce the control complexity. To verify the proposed design concept, a prototype tunable Nolen matrix operating at 5.8 GHz is designed and tested, and the experimental results agree well with simulation and theoretical analysis.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"995-998"},"PeriodicalIF":0.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter introduces an ultrawideband directional coupler with ground-signal-ground (GSG) interfaces that can be seamlessly integrated with the monolithic microwave integrated circuit (MMIC) mixers within a compact 67-GHz vector network analyzer (VNA) system. The coupler is fabricated through metal copper additive manufacturing process. To mitigate the impact of the polymer strips on the coupler’s raw directivity, the coupled lines were designed with a special impedance function, which effectively increases the average spacing between them, so the parasitic couplings from the polymer can be reduced. Additionally, enhancements to the polymer fabrication process now allow for the supporting strips to be meshed, further enhancing the directivity of the coupler. The fabricated coupler shows good performance in the operating frequency of 0.38–67 GHz, and the simulation results are in good agreement with the measured results: coupling of $13.5~pm ~0.17$ dB, insertion loss <3>13 dB, and directivity of >12 dB (>15 dB at 1.72–67 GHz).
{"title":"A 0.38–67-GHz Directional Coupler With GSG Interface for Compact VNA System","authors":"Tingting Sun;Ming Guo;Zhen Wang;Guanghua Shi;Hongjun Li;Qian Yang;Anxue Zhang;Cheng Guo","doi":"10.1109/LMWT.2024.3413154","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3413154","url":null,"abstract":"This letter introduces an ultrawideband directional coupler with ground-signal-ground (GSG) interfaces that can be seamlessly integrated with the monolithic microwave integrated circuit (MMIC) mixers within a compact 67-GHz vector network analyzer (VNA) system. The coupler is fabricated through metal copper additive manufacturing process. To mitigate the impact of the polymer strips on the coupler’s raw directivity, the coupled lines were designed with a special impedance function, which effectively increases the average spacing between them, so the parasitic couplings from the polymer can be reduced. Additionally, enhancements to the polymer fabrication process now allow for the supporting strips to be meshed, further enhancing the directivity of the coupler. The fabricated coupler shows good performance in the operating frequency of 0.38–67 GHz, and the simulation results are in good agreement with the measured results: coupling of \u0000<inline-formula> <tex-math>$13.5~pm ~0.17$ </tex-math></inline-formula>\u0000 dB, insertion loss <3>13 dB, and directivity of >12 dB (>15 dB at 1.72–67 GHz).","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"991-994"},"PeriodicalIF":0.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/LMWT.2024.3412922
Saurabh Shukla;Soumava Mukherjee
This letter presents substrate integrated coaxial line technology (SICL)-based low phase noise (PN) reflection oscillator at 15 GHz. The proposed oscillator circuit is realized using SICL-based high-Q-factor resonator. The SICL resonator operates at 15 GHz, where the terminating impedance of the resonator is controlled by the appropriate selection of inset dimensions. Moreover, the proposed circuit satisfies the Kurokawa’s condition between the SICL resonator and the source terminal of active device with adjusting the length of short-circuited stub at the gate terminal in the SICL environment. Due to the high-Q factor of the SICL-based resonator, the prototype of the proposed oscillator achieved a low PN of −110 dBc/Hz at 100 kHz and −133 dBc/Hz at 1 MHz with an RF output power of 12 dBm.
{"title":"A Low-Cost Reflection Oscillator Using Substrate Integrated Coaxial Line Technology","authors":"Saurabh Shukla;Soumava Mukherjee","doi":"10.1109/LMWT.2024.3412922","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3412922","url":null,"abstract":"This letter presents substrate integrated coaxial line technology (SICL)-based low phase noise (PN) reflection oscillator at 15 GHz. The proposed oscillator circuit is realized using SICL-based high-Q-factor resonator. The SICL resonator operates at 15 GHz, where the terminating impedance of the resonator is controlled by the appropriate selection of inset dimensions. Moreover, the proposed circuit satisfies the Kurokawa’s condition between the SICL resonator and the source terminal of active device with adjusting the length of short-circuited stub at the gate terminal in the SICL environment. Due to the high-Q factor of the SICL-based resonator, the prototype of the proposed oscillator achieved a low PN of −110 dBc/Hz at 100 kHz and −133 dBc/Hz at 1 MHz with an RF output power of 12 dBm.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"1035-1038"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a power amplifier (PA) with excellent power-added efficiency (PAE) for millimeter-wave (mm-wave) applications. The high efficiency is achieved by leveraging a local backside etching (LBE) process to enhance the quality factor (Q) of the output matching network. The PA was fabricated in a mature SiGe BiCMOS technology featuring heterojunction bipolar transistors (HBTs) having an $ {f}_{T} / {f}_{max } $ of 250/340 GHz. While the measured peak PAE is 56% at 24 and 25 GHz, the PA provides 16 dB of peak gain and a 3-dB bandwidth of 19 GHz ranging from 13.5 to 32.5 GHz, which makes the circuit well suited for multiple purposes, such as sensors, radars, 5G, and satellite communications. The maximum PAE exceeds 40% from 22 to 28 GHz, with a peak saturated power ( $ {P}_{text {sat}} $ ) of 16.5 dBm at 25 GHz. To the best of authors’ knowledge, this PA achieves the highest PAE reported to date for silicon-based mm-wave amplifiers.
{"title":"56% PAE mm-Wave SiGe BiCMOS Power Amplifier Employing Local Backside Etching","authors":"Aniello Franzese;Batuhan Sutbas;Raqibul Hasan;Andrea Malignaggi;Thomas Mausolf;Nebojsa Maletic;Muh-Dey Wei;Han Zhou;Christian Fager;Corrado Carta;Renato Negra","doi":"10.1109/LMWT.2024.3409149","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3409149","url":null,"abstract":"This letter presents a power amplifier (PA) with excellent power-added efficiency (PAE) for millimeter-wave (mm-wave) applications. The high efficiency is achieved by leveraging a local backside etching (LBE) process to enhance the quality factor (Q) of the output matching network. The PA was fabricated in a mature SiGe BiCMOS technology featuring heterojunction bipolar transistors (HBTs) having an \u0000<inline-formula> <tex-math>$ {f}_{T} / {f}_{max } $ </tex-math></inline-formula>\u0000 of 250/340 GHz. While the measured peak PAE is 56% at 24 and 25 GHz, the PA provides 16 dB of peak gain and a 3-dB bandwidth of 19 GHz ranging from 13.5 to 32.5 GHz, which makes the circuit well suited for multiple purposes, such as sensors, radars, 5G, and satellite communications. The maximum PAE exceeds 40% from 22 to 28 GHz, with a peak saturated power (\u0000<inline-formula> <tex-math>$ {P}_{text {sat}} $ </tex-math></inline-formula>\u0000) of 16.5 dBm at 25 GHz. To the best of authors’ knowledge, this PA achieves the highest PAE reported to date for silicon-based mm-wave amplifiers.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"1023-1026"},"PeriodicalIF":0.0,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-13DOI: 10.1109/LMWT.2024.3408457
Jiawei Wang;Minyu Mao;Ru Xiang;Huifu Wang;Haoyu Lian
A memory-efficient variant of the precise-integration time-domain (PITD) method is proposed for multiscale electromagnetic simulations involving geometry details in only one or two dimensions. In the classic PITD method, the dense matrix exponential of the time-stepping operator arising from the finite difference discretization needs explicit evaluation and storage, leading to prohibitive memory costs. In the proposed method, the precise integration (PI) method is used to efficiently compute the sparse matrix exponential of a diagonal operator to obtain a transformation of the original ordinary differential equation (ODE) system, which has a relaxed stability criterion and can be integrated by any explicit time integration scheme. It is demonstrated by numerical experiments that the proposed method can exclude the stiffness due to directional geometry details and outperforms the classic finite-difference time-domain (FDTD) method in multiscale analysis.
{"title":"A Memory-Efficient PITD Method for Multiscale Electromagnetic Simulations","authors":"Jiawei Wang;Minyu Mao;Ru Xiang;Huifu Wang;Haoyu Lian","doi":"10.1109/LMWT.2024.3408457","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3408457","url":null,"abstract":"A memory-efficient variant of the precise-integration time-domain (PITD) method is proposed for multiscale electromagnetic simulations involving geometry details in only one or two dimensions. In the classic PITD method, the dense matrix exponential of the time-stepping operator arising from the finite difference discretization needs explicit evaluation and storage, leading to prohibitive memory costs. In the proposed method, the precise integration (PI) method is used to efficiently compute the sparse matrix exponential of a diagonal operator to obtain a transformation of the original ordinary differential equation (ODE) system, which has a relaxed stability criterion and can be integrated by any explicit time integration scheme. It is demonstrated by numerical experiments that the proposed method can exclude the stiffness due to directional geometry details and outperforms the classic finite-difference time-domain (FDTD) method in multiscale analysis.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"967-970"},"PeriodicalIF":0.0,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-13DOI: 10.1109/LMWT.2024.3410669
Xiangyu Meng;Gaoyuan Zhao;Baoyong Chi
This letter proposes an ultracompact attenuator structure consisting mainly of nMOS transistors. The attenuator utilizes the parasitic capacitance of nMOS transistors for phase compensation to reduce the root-mean-square (rms) phase error. The common centroid layout scheme is used to mitigate the impact of process gradients on transistor performance. The proposed attenuator structure, designed and fabricated using a 65-nm CMOS process, features a compact core area of 0.0043 mm2. The fabricated attenuator exhibits a 31.5-dB attenuation range, featuring a 0.5-dB resolution and an insertion loss ranging from 4.3 to 6.4 dB from dc to 20 GHz. The amplitude rms error is within 0.297 dB, and the phase rms error is within 3.21°.
{"title":"An Ultracompact DC–20-GHz nMOS-Based CMOS Attenuator","authors":"Xiangyu Meng;Gaoyuan Zhao;Baoyong Chi","doi":"10.1109/LMWT.2024.3410669","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3410669","url":null,"abstract":"This letter proposes an ultracompact attenuator structure consisting mainly of nMOS transistors. The attenuator utilizes the parasitic capacitance of nMOS transistors for phase compensation to reduce the root-mean-square (rms) phase error. The common centroid layout scheme is used to mitigate the impact of process gradients on transistor performance. The proposed attenuator structure, designed and fabricated using a 65-nm CMOS process, features a compact core area of 0.0043 mm2. The fabricated attenuator exhibits a 31.5-dB attenuation range, featuring a 0.5-dB resolution and an insertion loss ranging from 4.3 to 6.4 dB from dc to 20 GHz. The amplitude rms error is within 0.297 dB, and the phase rms error is within 3.21°.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"1011-1014"},"PeriodicalIF":0.0,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-13DOI: 10.1109/LMWT.2024.3400834
Faisal Amin;Yun Liu;Yongjiu Zhao;Lingyun Liu
A novel approach for the implementation of single-unit multibit phase shifters (SUMBPSs) using binary multibit susceptance blocks (MBSBs) is presented. A single 50- $Omega $ main transmission line (MTL) is symmetrically loaded with three binary MBSBs, each comprising M parallel open-circuited stubs and p-i-n diodes. The linear relationship between loaded susceptance and phase shift is established by leveraging the linearity of susceptances curves w.r.t. length of the MTL. The use of single MTL allows the realization of SUMBPSs in a compact, single-unit structure with lower insertion loss (IL), whereas the linear susceptance curves enable the application of the principle of superposition, achieving the required $2^{M}$ phase states with only $3times M$ stubs and switches, representing a significant reduction compared with other contemporary solutions. For validation, a 3-bit SUMBPS is developed, and measurement results are given.
{"title":"Single-Unit Multibit Phase Shifters Using Binary Multibit Susceptance Blocks","authors":"Faisal Amin;Yun Liu;Yongjiu Zhao;Lingyun Liu","doi":"10.1109/LMWT.2024.3400834","DOIUrl":"https://doi.org/10.1109/LMWT.2024.3400834","url":null,"abstract":"A novel approach for the implementation of single-unit multibit phase shifters (SUMBPSs) using binary multibit susceptance blocks (MBSBs) is presented. A single 50-\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 main transmission line (MTL) is symmetrically loaded with three binary MBSBs, each comprising M parallel open-circuited stubs and p-i-n diodes. The linear relationship between loaded susceptance and phase shift is established by leveraging the linearity of susceptances curves w.r.t. length of the MTL. The use of single MTL allows the realization of SUMBPSs in a compact, single-unit structure with lower insertion loss (IL), whereas the linear susceptance curves enable the application of the principle of superposition, achieving the required \u0000<inline-formula> <tex-math>$2^{M}$ </tex-math></inline-formula>\u0000 phase states with only \u0000<inline-formula> <tex-math>$3times M$ </tex-math></inline-formula>\u0000 stubs and switches, representing a significant reduction compared with other contemporary solutions. For validation, a 3-bit SUMBPS is developed, and measurement results are given.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 8","pages":"999-1002"},"PeriodicalIF":0.0,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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