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Wideband Input Impedance-Invariant Active Phase Shifter Using Miller Capacitor Cancellation for 5G Communication 利用米勒电容消除的宽带输入阻抗不变有源移相器用于 5G 通信
N/A ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-19 DOI: 10.1109/LMWT.2024.3411602
Yongjun Kwon;Songcheol Hong
A wideband input impedance-invariant active phase shifter for millimeter-wave 5G communication is proposed and implemented in a 28-nm CMOS process. It consists of an IQ generator, a Gilbert cell-based vector summer, and a digital-to-analog converter (DAC). Input impedance variations of the vector summer according to the states of the phase shifter, which give rise to IQ mismatches, are substantially suppressed in a wide bandwidth. This is effectively achieved by introducing cross-coupled neutralization capacitors to cancel out the Miller capacitors ( $C_{text {gd}}$ ) of the input transistors of the vector summing circuit. The implemented phase shifter shows a maximum gain of 0.613 dB at 24.9 GHz and 3-dB bandwidths of 21.7–28.6 GHz (27.4%). The root mean square (rms) phase and gain errors are measured to be less than 1.5° and 0.25 dB, respectively, for 6-bit 360° phase and 4-bit 10-dB gain controls. The core area and power consumption are $0.47~text {mm}^{2}$ and 14.4 mW, respectively.
本文提出了一种用于毫米波 5G 通信的宽带输入阻抗不变有源移相器,并在 28 纳米 CMOS 工艺中实现。它由一个 IQ 发生器、一个基于 Gilbert 单元的矢量夏和一个数模转换器 (DAC) 组成。根据移相器的状态,矢量夏的输入阻抗会发生变化,从而导致 IQ 失配,而这种变化在宽带宽内得到了大幅抑制。这是通过引入交叉耦合中和电容器来抵消矢量相加电路输入晶体管的米勒电容器($C_{text {gd}}$)而有效实现的。实现的移相器在 24.9 GHz 时的最大增益为 0.613 dB,3-dB 带宽为 21.7-28.6 GHz (27.4%)。对于 6 位 360° 相位和 4 位 10 dB 增益控制,测量得出的均方根相位和增益误差分别小于 1.5° 和 0.25 dB。内核面积和功耗分别为 0.47~text {mm}^{2}$ 和 14.4 mW。
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引用次数: 0
Demonstrating Broadside-Coupled Coplanar Waveguide Interconnects to 325 GHz 展示宽边耦合共面波导互连器件,频率达 325 千兆赫
0 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-15 DOI: 10.1109/LMWT.2024.3440831
Nicholas R. Jungwirth;Meagan C. Papac;Bryan T. Bosworth;Aaron M. Hagerstrom;Eric J. Marksz;Jerome Cheron;Kassiopeia Smith;Angela C. Stelson;Ari Feldman;Dylan F. Williams;Christian J. Long;Nathan D. Orloff
We demonstrate three different broadside-coupled coplanar waveguides (CPWs) to 325 GHz that do not require bump bonds, wire bonds, or direct metal-to-metal bonding. Our design approach used a multimoded distributed theory rather than the conventional $lambda /4 $ approximation. The different interconnects had insertion losses better than 0.7 dB at 63, 93, and 120 GHz.
我们展示了三种不同的宽边耦合共面波导(CPW),其频率可达 325 GHz,无需凸点键合、线键合或直接金属对金属键合。我们的设计方法采用了多编码分布理论,而不是传统的$lambda /4 $近似。不同互连器件在 63、93 和 120 GHz 时的插入损耗均优于 0.7 dB。
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引用次数: 0
A Wideband High-Efficiency Continuous-Mode Class-GF−1 Power Amplifier With Second Harmonic Suppression 具有二次谐波抑制功能的宽带高效连续模式-GF-1 类功率放大器
0 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-14 DOI: 10.1109/LMWT.2024.3438550
Huawei Wu;Qiang Liu;Wang Liu;Guangxing Du;Guolin Li;Dong Cheng
This letter presents a wideband high-efficiency continuous-mode class-GF−1 (CCGF−1) power amplifier (PA) with harmonic suppression. An accurate impedance design space (IDS) in the load terminal is provided, considering the influence caused by the input second harmonic voltage. Moreover, the PA design focuses on the output matching network (MN) for suppressing the second harmonic component, which increases drain efficiency (DE). Meanwhile, the proposed CCGF−1 PA achieves close to one octave bandwidth (BW), because the design relaxes the relationship between input fundamental and second harmonic voltage for the first time. To verify the proposed methodology, a prototype is designed and fabricated by using a 10-W gallium nitride (GaN) device. The simulated and measured results show that the CCGF−1 PA achieves the DE of 64.3%–82.7%, the gain of 11.5–15.9 dB, and the output power of 38.2–42.4 dBm over the frequency range from 1.1 to 2 GHz. Compared with existing typical continuous-mode PAs, the design exhibits higher efficiency and wider BW.
本文介绍了一种具有谐波抑制功能的宽带高效连续模式-GF-1(CCGF-1)功率放大器(PA)。考虑到输入二次谐波电压的影响,提供了负载终端的精确阻抗设计空间(IDS)。此外,功率放大器的设计重点是抑制二次谐波分量的输出匹配网络(MN),从而提高漏极效率(DE)。同时,由于设计首次放宽了输入基波和二次谐波电压之间的关系,因此所提出的 CCGF-1 功率放大器实现了接近一个倍频程的带宽(BW)。为了验证所提出的方法,我们使用一个 10 瓦的氮化镓(GaN)器件设计并制造了一个原型。模拟和测量结果表明,CCGF-1 功率放大器在 1.1 至 2 GHz 频率范围内实现了 64.3% 至 82.7% 的 DE 值、11.5 至 15.9 dB 的增益和 38.2 至 42.4 dBm 的输出功率。与现有的典型连续模式功率放大器相比,该设计具有更高的效率和更宽的 BW。
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引用次数: 0
A 1.5–2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of −138 dBc/Hz at 1-MHz Offset Frequency 1.5-2.56 GHz TDC 辅助快速锁定宽带分数 N CPPLL,1 MHz 偏移频率时相位噪声为 -138 dBc/Hz
N/A ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-14 DOI: 10.1109/LMWT.2024.3427384
Ruiyong Xiang;Yixing Lu;Xiao Luo;Sifan Wang;Bodong Zhang;Shengpeng Shu;Haigang Feng
This letter presents a low phase noise wideband fractional-N fast-locking charge pump phase-locked loop (CPPLL) with a time-to-digital converter (TDC) calibrated by a frequency-locked loop (FLL). The proposed TDC loop is activated to adjust the PLL’s loop bandwidth (LBW) and accelerate the locking process. After the PLL locks, the TDC loop is automatically turned off, which does not require additional power and not affect the phase noise. Fabricated in the 65-nm CMOS process with an active area of 1.25 mm2, the proposed PLL achieves a phase noise of −138.55 dBc/Hz at 1-MHz offset from a 1.85-GHz carrier. It draws 54.2-mW power with a 50-MHz reference frequency from a 3.3-V power supply, leading to a −237.7-dB FoMr.
本文提出了一种低相位噪声宽带分数 N 快速锁定电荷泵锁相环 (CPPLL),它带有一个由锁频环 (FLL) 校准的时间数字转换器 (TDC)。建议的 TDC 环路被激活,以调整 PLL 的环路带宽 (LBW) 并加速锁定过程。PLL 锁定后,TDC 环路自动关闭,无需额外电源,也不会影响相位噪声。拟议的 PLL 采用 65 纳米 CMOS 工艺制造,有效面积为 1.25 平方毫米,在 1.85 千兆赫载波偏移 1 千兆赫时,相位噪声为 -138.55 dBc/Hz。它的功耗为 54.2-mW,参考频率为 50-MHz,电源电压为 3.3-V,因此 FoMr 为 -237.7-dB。
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引用次数: 0
Quarter-Dual-Mode SIW and Microstrip Line Resonator Stabled Feedback Oscillator 四分之一双模 SIW 和微带线谐振器固定反馈振荡器
0 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-14 DOI: 10.1109/LMWT.2024.3439733
Xian-Long Yang;Xiao-Wei Zhu;Dong-Yi Huang
In this letter, a low-phase noise feedback oscillator based on a quarter-dual-mode (QDM) substrate-integrated waveguide (SIW) and microstrip line is proposed. By combining a QDM SIW resonator with a microstrip line, a third-order transmission response can be achieved without increasing the occupied area. Two transmission zeros (TZs) are generated at the upper passband to increase the group delay peak and an additional TZ at $2f_{0}$ to suppress the second harmonic signal. The compact feedback-type oscillator using QDM SIW is designed, fabricated, and measured for the first time, which a circuit size is just about 930 mm2. The experimental results exhibit an output power of 0.22 dBm with a phase noise of −134.66 dBc/Hz at a 1-MHz frequency offset from the oscillation frequency. The oscillation frequency is 10.1 GHz and the corresponding suppression of the second harmonic signal is more than 52 dBc.
本文提出了一种基于四分之一双模(QDM)基底集成波导(SIW)和微带线的低相位噪声反馈振荡器。通过将 QDM SIW 谐振器与微带线相结合,可以在不增加占用面积的情况下实现三阶传输响应。在上通带产生两个传输零点 (TZ),以增加群延迟峰值,并在 2f_{0}$ 处产生一个额外的 TZ,以抑制二次谐波信号。我们首次设计、制造并测量了使用 QDM SIW 的紧凑型反馈型振荡器,其电路尺寸仅为 930 平方毫米。实验结果表明,在振荡频率偏移 1-MHz 时,输出功率为 0.22 dBm,相位噪声为 -134.66 dBc/Hz。振荡频率为 10.1 GHz,相应的二次谐波信号抑制超过 52 dBc。
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引用次数: 0
A Novel Digital Predistortion Coefficients Prediction Technique for Dynamic PA Nonlinearities Using Artificial Neural Networks 利用人工神经网络预测动态功率放大器非线性的新型数字预失真系数技术
N/A ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-12 DOI: 10.1109/LMWT.2024.3433484
Yufeng Zhang;Qingyue Chen;Kun Gao;Xin Liu;Wenhua Chen;Haigang Feng;Zhenghe Feng;Fadhel M. Ghannouchi
This article presents a novel artificial neural network (ANN)-based digital predistortion (DPD) coefficients prediction (ANN-DPDCP) technique for dynamic nonlinearities induced by varying input power levels of power amplifiers (PAs). Conventional DPD techniques face challenges in mitigating dynamic nonlinearities efficiently. By modeling and predicting variations of conventional Volterra-based DPD coefficients using ANNs, the ANN-DPDCP technique rapidly provides appropriate DPD coefficients based on the target input power level. Benefiting from its concise training dataset and fitting capability, the ANN-DPDCP technique requires limited storage resources and derives DPD coefficients at arbitrary input power levels with negligible delay and comparable linearization performance. Experiments on a Ka-band PA driven by 100- and 400-MHz signals with a 12-dBm input power range illustrate storage resource reductions of 99.54% for 400 MHz and 99.81% for 100 MHz.
本文介绍了一种基于人工神经网络(ANN)的新型数字预失真(DPD)系数预测(ANN-DPDCP)技术,用于处理功率放大器(PA)输入功率水平变化引起的动态非线性问题。传统的 DPD 技术在有效缓解动态非线性方面面临挑战。ANN-DPDCP 技术通过使用 ANN 对基于 Volterra 的传统 DPD 系数的变化进行建模和预测,可根据目标输入功率电平快速提供适当的 DPD 系数。得益于其简洁的训练数据集和拟合能力,ANN-DPDCP 技术只需有限的存储资源,就能在任意输入功率水平下推导出 DPD 系数,且延迟可忽略不计,线性化性能相当。在一个由 100 和 400 MHz 信号驱动、输入功率范围为 12 dBm 的 Ka 波段功率放大器上进行的实验表明,400 MHz 和 100 MHz 的存储资源分别减少了 99.54% 和 99.81%。
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引用次数: 0
A Monolithic Differential Bridged T-Coil 单片差分桥接 T 型线圈
0 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-12 DOI: 10.1109/LMWT.2024.3436613
Giovanni Scarlato;John R. Long
Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and $7~{pm }~2$ ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and $12~{pm }~2$ -ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is $2.43times $ (MFA) and $2.2times $ (MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of $224 times 215~{mu {text {m}}^{2}}$ .
介绍了适用于宽带和高速集成电路的两极和三极全差分桥式 T 型线圈。对为最大平坦振幅(MFA)和包络延迟(MFED)响应而设计的 T 型线圈原型进行了鉴定。两极 MFA 设计的测量跨导带宽和群延迟分别为 43.2 GHz 和 $7~{pm }~2$ ps,跨越 45 GHz。三极 MFED 设计的带宽为 23 GHz,群延迟为 12~{pm }~2$ -ps,频率范围为 30 GHz。与各自的非尖峰 R-C 电路相比,带宽扩展比(BWER)分别为 2.43 倍(MFA)和 2.2 倍(MFED)。T 线圈原型采用 22 纳米 FD-SOI CMOS 技术,芯片面积为 224 times 215~{mu {text {m}}^{2}}$ 。
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引用次数: 0
IEEE Microwave and Wireless Technology Letters Information for Authors 电气和电子工程师学会《微波与无线技术通讯》作者须知
N/A ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-08 DOI: 10.1109/LMWT.2024.3426192
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引用次数: 0
Calibration Techniques for Concurrent Dual-Band Multiport Receivers 并行双频多端口接收器的校准技术
0 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-08 DOI: 10.1109/LMWT.2024.3436529
Ronghao Chen;Mengting Tu;Pedro Cheong;Wai-Wa Choi
This letter introduces a novel calibration scheme designed for concurrent dual-band receivers based on a multiport interferometer aimed at resolving mismatches introduced by circuitry imperfections and distortion resulting from mutual interference. With mathematical deviations, we have demonstrated how these nonidealities degrade the performance of the receiver. In addition, we have shown that our proposed scheme has an affirmative impact on the mismatches and mutual interference between different input signals. With numerical investigations, the effectiveness of the proposed structure is validated, and a minimum of 36.2% and 66.7% improvement in error vector magnitude (EVM) is recorded compared with the reported literature under 0.2 and 2 Gb/s, respectively. In addition, a 15.6-dB improvement in the isolation between the dual-band signals is achieved.
这封信介绍了一种新的校准方案,该方案专为基于多端口干涉仪的并行双频接收器设计,旨在解决电路缺陷和相互干扰造成的失真所带来的不匹配问题。通过数学偏差,我们证明了这些非理想性是如何降低接收器性能的。此外,我们还证明了我们提出的方案对不同输入信号之间的失配和相互干扰有积极影响。通过数值研究,我们验证了所提结构的有效性,在 0.2 和 2 Gb/s 条件下,与文献报道相比,误差矢量幅度(EVM)分别至少提高了 36.2% 和 66.7%。此外,双频信号之间的隔离度也提高了 15.6 分贝。
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引用次数: 0
IEEE Microwave and Wireless Technology Letters publication 电气和电子工程师学会《微波与无线技术通讯》出版物
N/A ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-08-08 DOI: 10.1109/LMWT.2024.3426194
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引用次数: 0
期刊
IEEE microwave and wireless technology letters
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