Pub Date : 2019-01-01DOI: 10.1109/ICCAD46983.2019.9037972
Dyhia Kais, H. Denoun, Mohamed Lamine Hamida, A. Fekik, N. Benamrouche
{"title":"Comparative Study of PI and Fuzzy logic controllers for three-phases parallel multi-cell converter","authors":"Dyhia Kais, H. Denoun, Mohamed Lamine Hamida, A. Fekik, N. Benamrouche","doi":"10.1109/ICCAD46983.2019.9037972","DOIUrl":"https://doi.org/10.1109/ICCAD46983.2019.9037972","url":null,"abstract":"","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76263561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-01DOI: 10.1109/CADIAG.2018.8751436
Fouad Toufik, M. Bahaj
{"title":"Extracting OCL Integrity Constraints from Object Relational Database","authors":"Fouad Toufik, M. Bahaj","doi":"10.1109/CADIAG.2018.8751436","DOIUrl":"https://doi.org/10.1109/CADIAG.2018.8751436","url":null,"abstract":"","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79520112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICCAD.2017.8203750
K. Svore
In 1981, Richard Feynman proposed a device called a “quantum computer” to take advantage of the laws of quantum physics to achieve computational speed-ups over classical methods. Quantum computing promises to revolutionize how and what we compute. Over the course of three decades, quantum algorithms have been developed that offer fast solutions to problems in a variety of fields including number theory, optimization, chemistry, physics, and materials science. Quantum devices have also significantly advanced such that components of a scalable quantum computer have been demonstrated; the promise of implementing quantum algorithms is in our near future. I will attempt to explain some of the mysteries of this disruptive, revolutionary computational paradigm and how it will transform our digital age.
{"title":"Keynote addresses: Quantum computing: Revolutionizing computation through quantum mechanics","authors":"K. Svore","doi":"10.1109/ICCAD.2017.8203750","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203750","url":null,"abstract":"In 1981, Richard Feynman proposed a device called a “quantum computer” to take advantage of the laws of quantum physics to achieve computational speed-ups over classical methods. Quantum computing promises to revolutionize how and what we compute. Over the course of three decades, quantum algorithms have been developed that offer fast solutions to problems in a variety of fields including number theory, optimization, chemistry, physics, and materials science. Quantum devices have also significantly advanced such that components of a scalable quantum computer have been demonstrated; the promise of implementing quantum algorithms is in our near future. I will attempt to explain some of the mysteries of this disruptive, revolutionary computational paradigm and how it will transform our digital age.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77097807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Needle biopsy is a method to extract the cells from the patient’s body with a needle for tissue pathological examination. Many factors affect the cutting process of soft tissue, including the geometry of the biopsy needle, the mechanical properties of the soft tissue, the parameters of the puncture process and the interaction between them. This paper conducted orthogonal experiment of main cutting parameters based on single plane puncture biopsy needle, and obtained the cutting force curve of single plane puncture biopsy needle by studying the influence of the inclination angle, diameter and velocity of the single plane puncture biopsy needle on the puncture force of the biopsy needle. Stage analysis of the cutting process of biopsy needle puncture was made to determine the main influencing factors of puncture force during the cutting process, which provides a certain theoretical support for the design of new type of puncture biopsy needle and the operation of puncture biopsy.
{"title":"Cutting performance orthogonal test of single plane puncture biopsy needle based on puncture force","authors":"Yingqiang Xu, Qinhe Zhang, Guowei Liu","doi":"10.1063/1.4981581","DOIUrl":"https://doi.org/10.1063/1.4981581","url":null,"abstract":"Needle biopsy is a method to extract the cells from the patient’s body with a needle for tissue pathological examination. Many factors affect the cutting process of soft tissue, including the geometry of the biopsy needle, the mechanical properties of the soft tissue, the parameters of the puncture process and the interaction between them. This paper conducted orthogonal experiment of main cutting parameters based on single plane puncture biopsy needle, and obtained the cutting force curve of single plane puncture biopsy needle by studying the influence of the inclination angle, diameter and velocity of the single plane puncture biopsy needle on the puncture force of the biopsy needle. Stage analysis of the cutting process of biopsy needle puncture was made to determine the main influencing factors of puncture force during the cutting process, which provides a certain theoretical support for the design of new type of puncture biopsy needle and the operation of puncture biopsy.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91397672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-01-01DOI: 10.1109/CADIAG.2017.8075706
I. Mahmoud, H. Rehaoulia
{"title":"Nonlinear modelling improvement approach for linear actuator","authors":"I. Mahmoud, H. Rehaoulia","doi":"10.1109/CADIAG.2017.8075706","DOIUrl":"https://doi.org/10.1109/CADIAG.2017.8075706","url":null,"abstract":"","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82550674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICCAD.2014.7001411
Jin Hu, D. Sinha, Igor Keller
To protect against modeling limitations in considering design and electrical complexities, as well as variability, early and late signal propagation times in static timing analysis are often made pessimistic by addition of extra guard bands. However, these forced early-late splits introduce excessive and undesired pessimism. To this end, common path pessimism removal (CPPR) eliminates guaranteed redundant pessimism during timing analysis. This session aims to highlight the importance of CPPR during timing analysis, as well as explore novel methods for fast CPPR from the top performers of the TAU 2014 timing contest.
{"title":"TAU 2014 contest on removing common path pessimism during timing analysis","authors":"Jin Hu, D. Sinha, Igor Keller","doi":"10.1109/ICCAD.2014.7001411","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001411","url":null,"abstract":"To protect against modeling limitations in considering design and electrical complexities, as well as variability, early and late signal propagation times in static timing analysis are often made pessimistic by addition of extra guard bands. However, these forced early-late splits introduce excessive and undesired pessimism. To this end, common path pessimism removal (CPPR) eliminates guaranteed redundant pessimism during timing analysis. This session aims to highlight the importance of CPPR during timing analysis, as well as explore novel methods for fast CPPR from the top performers of the TAU 2014 timing contest.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80245907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.
{"title":"FPGA Simulation Engine for Customized Construction of Neural Microcircuits.","authors":"Hugh T Blair, Jason Cong, Di Wu","doi":"10.1109/FCCM.2013.22","DOIUrl":"https://doi.org/10.1109/FCCM.2013.22","url":null,"abstract":"<p><p>In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform <i>oscillatory path integration</i>, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.</p>","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/FCCM.2013.22","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"32970807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105292
G. Sigl
The design of security controllers, or more generally of microcontroller platforms implementing measures against hardware attacks, is still a very tedious handwork. Standardized and broadly available design tools as well as the necessary knowledge are rarely available and make secure hardware design a black art, known only within specialized companies building smart cards or Pay TV chips, for example. Secure hardware is, however, of increasing importance in many future embedded systems connected to cyber physical systems. Secure elements, i.e. special security chips or cores on a system on chip, are needed everywhere to protect these systems against physical attacks. Within this talk, the speaker will give some insight in the design flow of two security controller platforms and the special challenges encountered there. After summarizing the main attack scenarios for security hardware, a selection of countermeasures will be presented. These countermeasures have to be implemented and verified during various phases in the design flow. Some self-made tools and scripts have been used to achieve the result of a highly secure implementation, but there is a huge opportunity to accelerate implementation and verification steps. Furthermore, the knowledge about security could be captured inside tools and relieve designers of the task of becoming hardware security experts. The talk should motivate researchers in the EDA world to participate in the development of a new state-of-the-art design flow for secure hardware.
{"title":"Keynote address: Design of secure systems - Where are the EDA tools?","authors":"G. Sigl","doi":"10.1109/ICCAD.2011.6105292","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105292","url":null,"abstract":"The design of security controllers, or more generally of microcontroller platforms implementing measures against hardware attacks, is still a very tedious handwork. Standardized and broadly available design tools as well as the necessary knowledge are rarely available and make secure hardware design a black art, known only within specialized companies building smart cards or Pay TV chips, for example. Secure hardware is, however, of increasing importance in many future embedded systems connected to cyber physical systems. Secure elements, i.e. special security chips or cores on a system on chip, are needed everywhere to protect these systems against physical attacks. Within this talk, the speaker will give some insight in the design flow of two security controller platforms and the special challenges encountered there. After summarizing the main attack scenarios for security hardware, a selection of countermeasures will be presented. These countermeasures have to be implemented and verified during various phases in the design flow. Some self-made tools and scripts have been used to achieve the result of a highly secure implementation, but there is a huge opportunity to accelerate implementation and verification steps. Furthermore, the knowledge about security could be captured inside tools and relieve designers of the task of becoming hardware security experts. The talk should motivate researchers in the EDA world to participate in the development of a new state-of-the-art design flow for secure hardware.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89667235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-10DOI: 10.1109/ICCAD.2008.4681532
M. L. Jepsen
We take displays for granted in devices like our laptops, television, cell phones, and cars -to name a few places. The TFT LCD processes in use now are as mature as CMOS was 20 years ago, which is when we started seeing ASIC companies doing fabless chip design and investing heavily in CAD. Today, the display, as I believe I showed while working on the OLPC, is really just an ASIC! Why focus on the display? The display is the most expensive and power hungry component in your laptops, it can now be "taped out" just like an ASIC using standard TFT LCD fabs, and -in the limit- the laptop or the cell phone will become just a display in which the electronics are integrated into. I believe that we are about to see a revolution in display design, with gradual subsumption of more and more of the CPU and motherboard electronics, to further drive down cost and power consumption.
{"title":"CAD for displays!","authors":"M. L. Jepsen","doi":"10.1109/ICCAD.2008.4681532","DOIUrl":"https://doi.org/10.1109/ICCAD.2008.4681532","url":null,"abstract":"We take displays for granted in devices like our laptops, television, cell phones, and cars -to name a few places. The TFT LCD processes in use now are as mature as CMOS was 20 years ago, which is when we started seeing ASIC companies doing fabless chip design and investing heavily in CAD. Today, the display, as I believe I showed while working on the OLPC, is really just an ASIC!\u0000 Why focus on the display? The display is the most expensive and power hungry component in your laptops, it can now be \"taped out\" just like an ASIC using standard TFT LCD fabs, and -in the limit- the laptop or the cell phone will become just a display in which the electronics are integrated into. I believe that we are about to see a revolution in display design, with gradual subsumption of more and more of the CPU and motherboard electronics, to further drive down cost and power consumption.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80648827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-10DOI: 10.1109/ICCAD.2008.4681537
D. Pan, S. Renwick, Vivek Singh, Judy Huckabay
The semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. On one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. On the other hand, next generation lithography, in particular, extreme ultra violet lithography (EUVL) is projected by ITRS as the main contender for technology nodes at or below 22nm, though significant challenges still exist from both technology and economy aspects. This tutorial will cover key nanolithography and CAD challenges with possible solutions for 32nm/22nm (and beyond?), from the underlying hardware/equipment perspectives (for double patterning, EUV, and so on), to the computational lithography aspects (extreme RET, inverse lithography, pixelated mask, etc.), and to the key EDA issues on nanolithofriendly layouts (e.g., double patterning compliance layout, and so on).
{"title":"Nanolithography and CAD challenges for 32nm/22nm and beyond","authors":"D. Pan, S. Renwick, Vivek Singh, Judy Huckabay","doi":"10.1109/ICCAD.2008.4681537","DOIUrl":"https://doi.org/10.1109/ICCAD.2008.4681537","url":null,"abstract":"The semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. On one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. On the other hand, next generation lithography, in particular, extreme ultra violet lithography (EUVL) is projected by ITRS as the main contender for technology nodes at or below 22nm, though significant challenges still exist from both technology and economy aspects. This tutorial will cover key nanolithography and CAD challenges with possible solutions for 32nm/22nm (and beyond?), from the underlying hardware/equipment perspectives (for double patterning, EUV, and so on), to the computational lithography aspects (extreme RET, inverse lithography, pixelated mask, etc.), and to the key EDA issues on nanolithofriendly layouts (e.g., double patterning compliance layout, and so on).","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76000533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：