We propose a novel layer assignment approach for the k-layer Constrained Via Minimization (CVM) problem. We transform the problem into a constrained k-way graph partitioning one. Practical issues such as pin-out constraint, over-the-cell constraint, and overlapping between wire segments of the same net, have all been taken into consideration. We propose a modified simulated annealing program for the problem. A set of large routing results generated by a commercial three-layer router has been used to test the effectiveness of the program. Up to 70% reduction of vias has been observed. Assuming an additional fourth layer is available, more reduction is achieved. This work is the first to demonstrate the feasibility of via minimization for practical sized multi layer layout. It is also applicable to future design with more layers.
{"title":"A graph-partitioning-based approach for multi-layer constrained via minimization","authors":"Yih-Chih Chou, Y. Lin","doi":"10.1145/288548.289065","DOIUrl":"https://doi.org/10.1145/288548.289065","url":null,"abstract":"We propose a novel layer assignment approach for the k-layer Constrained Via Minimization (CVM) problem. We transform the problem into a constrained k-way graph partitioning one. Practical issues such as pin-out constraint, over-the-cell constraint, and overlapping between wire segments of the same net, have all been taken into consideration. We propose a modified simulated annealing program for the problem. A set of large routing results generated by a commercial three-layer router has been used to test the effectiveness of the program. Up to 70% reduction of vias has been observed. Assuming an additional fourth layer is available, more reduction is achieved. This work is the first to demonstrate the feasibility of via minimization for practical sized multi layer layout. It is also applicable to future design with more layers.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74176570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-01DOI: 10.1109/ICCAD.1998.743050
A. Hirata, H. Onodera, K. Tamaru
{"title":"Proposal of a timing model for CMOS logic gates driving a CRC load","authors":"A. Hirata, H. Onodera, K. Tamaru","doi":"10.1109/ICCAD.1998.743050","DOIUrl":"https://doi.org/10.1109/ICCAD.1998.743050","url":null,"abstract":"","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74504258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643584
Jiing-Yuan Lin, W. Shen, Jing-Yang Jou
To characterize a macrocell, a general method is to store the power consumption of all possible transition events at primary inputs in the lookup tables. Though this approach is very accurate, the lookup tables could be huge for the macrocells with many inputs. In this paper, we present a new power modeling method which takes advantage of the structure information of macrocells and selects minimum number of primary inputs or internal nodes in a macrocell as state variables to build a state transition graph (STG). Those state variables can completely model the transitions of all internal nodes and the primary outputs. By carefully deleting some state variables, we further introduce an incomplete power modeling technique which can simplify the STG without losing much accuracy. In addition, we exploit the property of the compatible patterns of a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy and can reduce the size of the lookup table significantly comparing to the general approach.
{"title":"A power modeling and characterization method for macrocells using structure information","authors":"Jiing-Yuan Lin, W. Shen, Jing-Yang Jou","doi":"10.1109/ICCAD.1997.643584","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643584","url":null,"abstract":"To characterize a macrocell, a general method is to store the power consumption of all possible transition events at primary inputs in the lookup tables. Though this approach is very accurate, the lookup tables could be huge for the macrocells with many inputs. In this paper, we present a new power modeling method which takes advantage of the structure information of macrocells and selects minimum number of primary inputs or internal nodes in a macrocell as state variables to build a state transition graph (STG). Those state variables can completely model the transitions of all internal nodes and the primary outputs. By carefully deleting some state variables, we further introduce an incomplete power modeling technique which can simplify the STG without losing much accuracy. In addition, we exploit the property of the compatible patterns of a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy and can reduce the size of the lookup table significantly comparing to the general approach.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83358685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-12-01DOI: 10.1109/ICCAD.1996.569916
C. Su, Yue-Tsang Chen, S. Jou, Y. Ting
In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.
{"title":"Metrology for analog module testing using analog testability bus","authors":"C. Su, Yue-Tsang Chen, S. Jou, Y. Ting","doi":"10.1109/ICCAD.1996.569916","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569916","url":null,"abstract":"In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78484361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569828
Jiing-Yuan Lin, W. Shen, Jing-Yang Jou
In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in [1]. We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rate, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.
{"title":"A power modeling and characterization method for the CMOS standard cell library","authors":"Jiing-Yuan Lin, W. Shen, Jing-Yang Jou","doi":"10.1109/ICCAD.1996.569828","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569828","url":null,"abstract":"In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in [1]. We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rate, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75936576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the primary Department of Commerce bureau to assist with post-natural disaster economic recovery, EDA received two distinct disaster supplemental appropriations totaling $500 million in Fiscal Year 2008. The appropriations are to be used for disaster relief, long-term recovery and restoration of infrastructure in areas covered by a declaration of major disaster under the Robert T. Stafford Disaster Relief and Emergency Assistance Act.
{"title":"Intranets and EDA: impact, application, and technology","authors":"D. Ku, J. Rowson","doi":"10.1145/244522.244883","DOIUrl":"https://doi.org/10.1145/244522.244883","url":null,"abstract":"As the primary Department of Commerce bureau to assist with post-natural disaster economic recovery, EDA received two distinct disaster supplemental appropriations totaling $500 million in Fiscal Year 2008. The appropriations are to be used for disaster relief, long-term recovery and restoration of infrastructure in areas covered by a declaration of major disaster under the Robert T. Stafford Disaster Relief and Emergency Assistance Act.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72997234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629772
J. Grodstein, E. Lehman, H. Harkness, H. Touati, B. Grundmann
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming and extends them to retime pipelined circuits. If the circuit to be mapped has a tree structure, our algorithm generates an optimal solution compatible with that structure. The algorithm takes into account gate delays and capacitive loads as latches are moved across the logic. It also supports latches with embedded logic: i.e., cells that combine a D latch with a combinational gate at little extra cost in latch delay.
{"title":"Optimal Latch Mapping And Retiming Within A Tree","authors":"J. Grodstein, E. Lehman, H. Harkness, H. Touati, B. Grundmann","doi":"10.1109/ICCAD.1994.629772","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629772","url":null,"abstract":"We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming and extends them to retime pipelined circuits. If the circuit to be mapped has a tree structure, our algorithm generates an optimal solution compatible with that structure. The algorithm takes into account gate delays and capacitive loads as latches are moved across the logic. It also supports latches with embedded logic: i.e., cells that combine a D latch with a combinational gate at little extra cost in latch delay.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74440456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629876
P. Siegel, G. Micheli
We describe methods for decomposing gates within a speed-independent asynchronous design. The decomposition step is an essential part of the library binding process, and is used both to increase the granularity of the design for higher quality mapping and to ensure that the design can be implemented. We present algorithms for simple hazard-free gate decomposition, and show results which indicate that we can decompose most of the gates in our benchmark set by this simple method. We then extend these algorithms to work for those cases in which no simple decomposition exists.
{"title":"Decomposition Methods For Library Binding Of Speed-independent Asynchronous Designs","authors":"P. Siegel, G. Micheli","doi":"10.1109/ICCAD.1994.629876","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629876","url":null,"abstract":"We describe methods for decomposing gates within a speed-independent asynchronous design. The decomposition step is an essential part of the library binding process, and is used both to increase the granularity of the design for higher quality mapping and to ensure that the design can be implemented. We present algorithms for simple hazard-free gate decomposition, and show results which indicate that we can decompose most of the gates in our benchmark set by this simple method. We then extend these algorithms to work for those cases in which no simple decomposition exists.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79249779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629729
Massoud Pedram, J. Rabaey
Description: In recent years, the desirability of portable operation of all types of electronic systems has become evident. One of the primary objectives in the design of portable systems is power reduction needed to minimize the size and weight allocated to batteries. Another driver of the progress in low power design is the increasing need to reduce active and/or standby power consumption in all electronic systems, low to high end, analog and digital. Essential elements of a low power design environment include means of analyzing the dissipation of a proposed or an existing design, mechanisms for minimizing the power consumption when needed and techniques to explore the impact of design trade-offs on the power consumption, area and performance of a design.
{"title":"Design Solutions And Challenges For Low Power Systems","authors":"Massoud Pedram, J. Rabaey","doi":"10.1109/ICCAD.1994.629729","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629729","url":null,"abstract":"Description: In recent years, the desirability of portable operation of all types of electronic systems has become evident. One of the primary objectives in the design of portable systems is power reduction needed to minimize the size and weight allocated to batteries. Another driver of the progress in low power design is the increasing need to reduce active and/or standby power consumption in all electronic systems, low to high end, analog and digital. Essential elements of a low power design environment include means of analyzing the dissipation of a proposed or an existing design, mechanisms for minimizing the power consumption when needed and techniques to explore the impact of design trade-offs on the power consumption, area and performance of a design.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85115262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629788
Kazuhito Ito, L. Lucke, K. Parhi
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule.
{"title":"Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis","authors":"Kazuhito Ito, L. Lucke, K. Parhi","doi":"10.1109/ICCAD.1994.629788","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629788","url":null,"abstract":"In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85466939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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