This paper presents a new congestion minimization technique for standard cell global placement. The most distinct feature of this approach is that it does not follow the traditional "estimate-then-eliminate" strategy. Instead, it avoids the excessive usage of routing resources by the "local" nets so that more routing resources are available for the uncertain "global" nets. The experimental results show that our new technique, SPARSE, achieves better routability than the traditional total wire length (Bounding Box) guided placers, which had been shown to deliver the best routability results among the placers optimizing different cost functions [2]. Another feature of SPARSE is the capability of allocating white space implicitly. SPARSE exploits the well known empirical Rent's rule and is able to improve the routability even more in the presence of white space. Compared to the most recent academic routability-driven placer Dragon[8], SPARSE is able to produce solutions with equal or better routability.
{"title":"Congestion minimization during placement without estimation","authors":"Bo Hu, M. Marek-Sadowska","doi":"10.1145/774572.774681","DOIUrl":"https://doi.org/10.1145/774572.774681","url":null,"abstract":"This paper presents a new congestion minimization technique for standard cell global placement. The most distinct feature of this approach is that it does not follow the traditional \"estimate-then-eliminate\" strategy. Instead, it avoids the excessive usage of routing resources by the \"local\" nets so that more routing resources are available for the uncertain \"global\" nets. The experimental results show that our new technique, SPARSE, achieves better routability than the traditional total wire length (Bounding Box) guided placers, which had been shown to deliver the best routability results among the placers optimizing different cost functions [2]. Another feature of SPARSE is the capability of allocating white space implicitly. SPARSE exploits the well known empirical Rent's rule and is able to improve the routability even more in the presence of white space. Compared to the most recent academic routability-driven placer Dragon[8], SPARSE is able to produce solutions with equal or better routability.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78454878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-11-04DOI: 10.1109/ICCAD.2001.968687
Daler N. Rakhmatov, S. Vrudhula
Once the battery becomes fully discharged, a battery-powered portable electronic system goes off-line. Therefore, it is important to take the battery behavior into account. A system designer needs an adequate high-level model in order to make battery-aware decisions that target maximization of the system's lifetime on-line. We propose such a model: it allows a designer to predict the battery time-to-failure for a given load and provides a cost metric for lifetime optimization algorithms. Our model also allows for a tradeoff between the accuracy and the amount of computation performed. The quality of the proposed model is evaluated using a detailed low-level simulation of a lithium-ion electrochemical cell.
{"title":"An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems","authors":"Daler N. Rakhmatov, S. Vrudhula","doi":"10.1109/ICCAD.2001.968687","DOIUrl":"https://doi.org/10.1109/ICCAD.2001.968687","url":null,"abstract":"Once the battery becomes fully discharged, a battery-powered portable electronic system goes off-line. Therefore, it is important to take the battery behavior into account. A system designer needs an adequate high-level model in order to make battery-aware decisions that target maximization of the system's lifetime on-line. We propose such a model: it allows a designer to predict the battery time-to-failure for a given load and provides a cost metric for lifetime optimization algorithms. Our model also allows for a tradeoff between the accuracy and the amount of computation performed. The quality of the proposed model is evaluated using a detailed low-level simulation of a lithium-ion electrochemical cell.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76263993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-11-04DOI: 10.1109/ICCAD.2001.968723
C. Chang, M. Marek-Sadowska
Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, the search for valid alternative wires requires trial-and-error redundancy testing of a potentially large set of candidate wires. In this paper, we study the fundamental theory behind this technique and propose a new reasoning scheme which directly identifies alternative wires without performing trial-and-error tests. Experimental results show up to 15 times speedup in comparison to the best techniques in literature.
{"title":"Single-pass redundancy addition and removal","authors":"C. Chang, M. Marek-Sadowska","doi":"10.1109/ICCAD.2001.968723","DOIUrl":"https://doi.org/10.1109/ICCAD.2001.968723","url":null,"abstract":"Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, the search for valid alternative wires requires trial-and-error redundancy testing of a potentially large set of candidate wires. In this paper, we study the fundamental theory behind this technique and propose a new reasoning scheme which directly identifies alternative wires without performing trial-and-error tests. Experimental results show up to 15 times speedup in comparison to the best techniques in literature.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ICCAD.2001.968723","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72378680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-11-04DOI: 10.1109/ICCAD.2001.968609
A. Singh, G. Parthasarathy, M. Marek-Sadowska
In this paper, we utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.
{"title":"Interconnect resource-aware placement for hierarchical FPGAs","authors":"A. Singh, G. Parthasarathy, M. Marek-Sadowska","doi":"10.1109/ICCAD.2001.968609","DOIUrl":"https://doi.org/10.1109/ICCAD.2001.968609","url":null,"abstract":"In this paper, we utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88672118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-05DOI: 10.1109/ICCAD.2000.896534
A. Strojwas
Over the years, the increase in IC functionality has been achieved by a continuous drive towards smaller feature sizes. Due to the decreasing dimensions of semiconductor structures, the sensitivity to critical design and manufacturing parameters has risen dramatically. Vertical integration techniques and multi-level interconnect, which are becoming more common in modern technologies, have driven up the number of critical processing steps to several hundreds. These trends are expected to continue for the next several decades. The .13 micron technology is around the corner, as well as 300mm wafers. The increase in IC functionality has come with a skyrocketing capital spending (more than $2 billion per fabrication facility). Moreover, the product life cycles for leading edge IC's have become very short (less than 2 years).
{"title":"Design-manufacturing interface for 0.13 micron and below","authors":"A. Strojwas","doi":"10.1109/ICCAD.2000.896534","DOIUrl":"https://doi.org/10.1109/ICCAD.2000.896534","url":null,"abstract":"Over the years, the increase in IC functionality has been achieved by a continuous drive towards smaller feature sizes. Due to the decreasing dimensions of semiconductor structures, the sensitivity to critical design and manufacturing parameters has risen dramatically. Vertical integration techniques and multi-level interconnect, which are becoming more common in modern technologies, have driven up the number of critical processing steps to several hundreds. These trends are expected to continue for the next several decades. The .13 micron technology is around the corner, as well as 300mm wafers. The increase in IC functionality has come with a skyrocketing capital spending (more than $2 billion per fabrication facility). Moreover, the product life cycles for leading edge IC's have become very short (less than 2 years).","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80280464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810635
Yi-Kan Cheng, S. Kang
In this paper, we present a method to efficiently identify the onchip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in early chip design phase, for which a large number of design iterations is needed and simulation efficiency is much required.
{"title":"An efficient method for hot-spot identification in ULSI circuits","authors":"Yi-Kan Cheng, S. Kang","doi":"10.1109/ICCAD.1999.810635","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810635","url":null,"abstract":"In this paper, we present a method to efficiently identify the onchip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in early chip design phase, for which a large number of design iterations is needed and simulation efficiency is much required.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73867414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/ICCAD.1999.810719
E. M. Foster
This presentation will review system-level issues associated with integrating the major blocks of a Set-Top Box onto a single die. In addition to the challenges of merging several powerful functions into a single chip, the goal of integration is to yield a composite design that is not only more cost effective but also provides more function than the sum of discrete parts. This is accomplished through consolidated and shared memory, improved system bandwidth and efficiency, and additional inter-macro signals to facilitate improved communication.
{"title":"Design of a Set-Top Box System on a Chip","authors":"E. M. Foster","doi":"10.1109/ICCAD.1999.810719","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810719","url":null,"abstract":"This presentation will review system-level issues associated with integrating the major blocks of a Set-Top Box onto a single die. In addition to the challenges of merging several powerful functions into a single chip, the goal of integration is to yield a composite design that is not only more cost effective but also provides more function than the sum of discrete parts. This is accomplished through consolidated and shared memory, improved system bandwidth and efficiency, and additional inter-macro signals to facilitate improved communication.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74613012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate simulation of transient device thermal behavior is essential to predict CMOS VLSI circuit failures under electrical overstress (EOS). In this paper, we present an efficient transient electrothermal simulator that is built upon a SPICE-like engine. The transient device temperature is estimated by the convolution of the device power dissipation and its thermal impulse response which can be derived an analytical solution of the heat diffusion equation. New fast thermal simulation techniques are proposed including a regionwise-exponential (RWE) approximation of thermal impulse response and recursive convolution scheme. The recursive convolution provides a significant performance improvement over the numerical convolution by orders of magnitude, making it computationally feasible to simulate CMOS circuits with many devices.
{"title":"Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress","authors":"Tong Li, C. Tsai, S. Kang","doi":"10.1145/288548.288553","DOIUrl":"https://doi.org/10.1145/288548.288553","url":null,"abstract":"Accurate simulation of transient device thermal behavior is essential to predict CMOS VLSI circuit failures under electrical overstress (EOS). In this paper, we present an efficient transient electrothermal simulator that is built upon a SPICE-like engine. The transient device temperature is estimated by the convolution of the device power dissipation and its thermal impulse response which can be derived an analytical solution of the heat diffusion equation. New fast thermal simulation techniques are proposed including a regionwise-exponential (RWE) approximation of thermal impulse response and recursive convolution scheme. The recursive convolution provides a significant performance improvement over the numerical convolution by orders of magnitude, making it computationally feasible to simulate CMOS circuits with many devices.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72592649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given.This tutorial is intended to help circuit designers and CAD tools developers gain an understanding of the problems, the existing tools, and the critical CAD needs in the area of interconnect for high speed systems.
{"title":"Interconnect in high speed designs: problems, methodologies and tools","authors":"P. Restle, J. Phillips, I. Elfadel","doi":"10.1145/288548.288551","DOIUrl":"https://doi.org/10.1145/288548.288551","url":null,"abstract":"Summary form only given.This tutorial is intended to help circuit designers and CAD tools developers gain an understanding of the problems, the existing tools, and the critical CAD needs in the area of interconnect for high speed systems.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75886679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Time multiplexed FPGAs have the potential to dramatically improve logic density by time sharing logic, and have become an active research for reconfigurable computing. The partitioning problem for time multiplexed FPGAs is different from the traditional partitioning problem in that the nodes have precedence constraints among them, and the widely used iterative improvement partitioning methods such as KL B.W. Kernighan and S. Lin, 1978) are no longer applicable. All later approaches (S. Trimberger, 1998; D. Chang and M. Marek-Sadowska, 1998; 1997) used list scheduling heuristics. We present a network flow based algorithm for multi way precedence constrained partitioning, which can handle the precedence constraints while minimizing the net cut size. The experimental results on the MCNC benchmark circuits show that our algorithm outperforms list scheduling by a big margin, with an average improvement of over 50% for bipartitioning and 20% for multi way partitioning.
{"title":"Network flow based circuit partitioning for time-multiplexed FPGAs","authors":"Huiqun Liu, D. F. Wong","doi":"10.1145/288548.289077","DOIUrl":"https://doi.org/10.1145/288548.289077","url":null,"abstract":"Time multiplexed FPGAs have the potential to dramatically improve logic density by time sharing logic, and have become an active research for reconfigurable computing. The partitioning problem for time multiplexed FPGAs is different from the traditional partitioning problem in that the nodes have precedence constraints among them, and the widely used iterative improvement partitioning methods such as KL B.W. Kernighan and S. Lin, 1978) are no longer applicable. All later approaches (S. Trimberger, 1998; D. Chang and M. Marek-Sadowska, 1998; 1997) used list scheduling heuristics. We present a network flow based algorithm for multi way precedence constrained partitioning, which can handle the precedence constraints while minimizing the net cut size. The experimental results on the MCNC benchmark circuits show that our algorithm outperforms list scheduling by a big margin, with an average improvement of over 50% for bipartitioning and 20% for multi way partitioning.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89472793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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