Pub Date : 2008-11-10DOI: 10.1109/ICCAD.2008.4681538
Dan Bailey, E. Soenen, Puneet Gupta, P. Villarrubia, S. Dhong
Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.
{"title":"Challenges at 45nm and beyond","authors":"Dan Bailey, E. Soenen, Puneet Gupta, P. Villarrubia, S. Dhong","doi":"10.1109/ICCAD.2008.4681538","DOIUrl":"https://doi.org/10.1109/ICCAD.2008.4681538","url":null,"abstract":"Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79119197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-10DOI: 10.1109/ICCAD.2008.4681540
R. Aitken, J. Bautista, Wojciech Maly, J. Rabaey
Moore's law has been a foundation of modern electronics, sustained primarily by scaling. But can this continue despite the serious problems of litho, variability, device physics, and cost? This panel looks at several possibilities. Perhaps Moore's law will muddle through, as it has so far, with a combination of tools, process, and design. But even if technically possible, Moore's law is in practice driven by economics, and economics might turn against further scaling. Also, we've all seen how performance of single cores has topped out, despite scaling. Might this be a fundamental problem with planar technologies, prompting the need to go 3-D to get further performance increases? Or might CMOS itself give way to other technologies, allowing Moore's law yet another respite? Compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.
{"title":"More Moore: foolish, feasible, or fundamentally different?","authors":"R. Aitken, J. Bautista, Wojciech Maly, J. Rabaey","doi":"10.1109/ICCAD.2008.4681540","DOIUrl":"https://doi.org/10.1109/ICCAD.2008.4681540","url":null,"abstract":"Moore's law has been a foundation of modern electronics, sustained primarily by scaling. But can this continue despite the serious problems of litho, variability, device physics, and cost? This panel looks at several possibilities. Perhaps Moore's law will muddle through, as it has so far, with a combination of tools, process, and design. But even if technically possible, Moore's law is in practice driven by economics, and economics might turn against further scaling. Also, we've all seen how performance of single cores has topped out, despite scaling. Might this be a fundamental problem with planar technologies, prompting the need to go 3-D to get further performance increases? Or might CMOS itself give way to other technologies, allowing Moore's law yet another respite? Compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ICCAD.2008.4681540","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72495543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-10DOI: 10.1109/ICCAD.2008.4681539
Henry Chang, W. Walker, J. Maneatis, J. F. Croix
The design of complex mixed-signal system-on-a-chip (SOC) designer poses challenging requirements on the simulation design environment. The simulation platform has to include simulations at the behavioral, gate and transistor-level which have traditionally been done in separate environments. As the scaling trend continues, the designer needs additional accuracy and capacity, new capabilities such as efficient statistical simulation that takes into account layout dependent effects. In this panel we have representatives from the CAD and design community discussing the challenges and current solutions available to the mixed-signal simulation challenge.
{"title":"Mixed-signal simulation challenges and solutions","authors":"Henry Chang, W. Walker, J. Maneatis, J. F. Croix","doi":"10.1109/ICCAD.2008.4681539","DOIUrl":"https://doi.org/10.1109/ICCAD.2008.4681539","url":null,"abstract":"The design of complex mixed-signal system-on-a-chip (SOC) designer poses challenging requirements on the simulation design environment. The simulation platform has to include simulations at the behavioral, gate and transistor-level which have traditionally been done in separate environments. As the scaling trend continues, the designer needs additional accuracy and capacity, new capabilities such as efficient statistical simulation that takes into account layout dependent effects. In this panel we have representatives from the CAD and design community discussing the challenges and current solutions available to the mixed-signal simulation challenge.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75532291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The human brain is a network containing a hundred billion neurons, each communicating with several thousand others. As the wiring for neuronal communication draws on limited space and energy resources, evolution had to optimize their use. This principle of minimizing wiring costs, similar to that in computer design, explains many features of brain architecture, including placement and shape of many neurons. However, the shape of some neurons and their synaptic properties remained unexplained. This led us to the principle of maximization of brain's ability to store information. Combination of the two principles provides a systematic view of brain architecture, necessary to explain brain function. It would be interesting to see whether advances in understanding brain function will make impact on computer design.
{"title":"What can brain researchers learn from computer engineers and vice versa?","authors":"D. Chklovskii","doi":"10.1145/1509456.1509459","DOIUrl":"https://doi.org/10.1145/1509456.1509459","url":null,"abstract":"The human brain is a network containing a hundred billion neurons, each communicating with several thousand others. As the wiring for neuronal communication draws on limited space and energy resources, evolution had to optimize their use. This principle of minimizing wiring costs, similar to that in computer design, explains many features of brain architecture, including placement and shape of many neurons. However, the shape of some neurons and their synaptic properties remained unexplained. This led us to the principle of maximization of brain's ability to store information. Combination of the two principles provides a systematic view of brain architecture, necessary to explain brain function. It would be interesting to see whether advances in understanding brain function will make impact on computer design.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74069501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICCAD.2007.4397264
Yu Hu, Satyaki Das, S. Trimberger, Lei He
Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small set of logic functions that are able to implement a large portion of functions for given FPGA applications. Assuming that the extracted logic functions are implemented by macro-gates in PLBs, we then develop a complete synthesis flow for such heterogeneous PLBs with mixed LUTs and macro-gates. The flow includes a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming based area recovery algorithm to balance the resource utilization of macro-gates and LUTs for area-efficient packing, and a SAT-based packing. We finally evaluate the proposed heterogeneous FPGA using the newly developed flow and show that mixing LUT and macro-gates, both with 6 inputs, improves performance by 16.5% and reduces logic area by 30% compared to using merely 6-input LUTs.
{"title":"Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates","authors":"Yu Hu, Satyaki Das, S. Trimberger, Lei He","doi":"10.1109/ICCAD.2007.4397264","DOIUrl":"https://doi.org/10.1109/ICCAD.2007.4397264","url":null,"abstract":"Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small set of logic functions that are able to implement a large portion of functions for given FPGA applications. Assuming that the extracted logic functions are implemented by macro-gates in PLBs, we then develop a complete synthesis flow for such heterogeneous PLBs with mixed LUTs and macro-gates. The flow includes a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming based area recovery algorithm to balance the resource utilization of macro-gates and LUTs for area-efficient packing, and a SAT-based packing. We finally evaluate the proposed heterogeneous FPGA using the newly developed flow and show that mixing LUT and macro-gates, both with 6 inputs, improves performance by 16.5% and reduces logic area by 30% compared to using merely 6-input LUTs.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84351982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Welcome to the 2006 International Conference on Computer-Aided Design, the world's premier conference in electronic design technology! Our technical program this year is more exciting than ever, addressing several challenges posed by current and future design technologies including power, variability, reliability, yield, system design, and the impact of new devices and materials. We also offer several social events where you can meet colleagues and friends. Both professionals and researchers active in EDA, as well as practicing designers, will benefit from the knowledge provided in both regular paper sessions and embedded tutorials.
{"title":"Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design","authors":"S. Hassoun","doi":"10.1145/1233501","DOIUrl":"https://doi.org/10.1145/1233501","url":null,"abstract":"Welcome to the 2006 International Conference on Computer-Aided Design, the world's premier conference in electronic design technology! \u0000 \u0000Our technical program this year is more exciting than ever, addressing several challenges posed by current and future design technologies including power, variability, reliability, yield, system design, and the impact of new devices and materials. \u0000 \u0000We also offer several social events where you can meet colleagues and friends. Both professionals and researchers active in EDA, as well as practicing designers, will benefit from the knowledge provided in both regular paper sessions and embedded tutorials.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91397549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ICCAD.2006.320040
L. Stok
{"title":"Wednesday Keynote: Innovation in Electronic Design Automation","authors":"L. Stok","doi":"10.1109/ICCAD.2006.320040","DOIUrl":"https://doi.org/10.1109/ICCAD.2006.320040","url":null,"abstract":"","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91395549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-05-31DOI: 10.1109/ICCAD.2005.1560204
K. O. Kenneth, Kihong Kim, B. Floyd, J. Mehta, H. Yoon, Chih-Ming Hung, D. Bravo, T. Dickson, Xiaoling Guo, Ran Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, Dong-Jun Yang, J. Bohorquez, Jie Chen, Eunyoung Seok, L. Gao, A. Sugavanam, Jau-Jr Lin, S. Yu, C. Cao, M. Hwang, Y.-R. Ding, S.-H. Hwang, Hsin-Ta Wu, N. Zhang, J. Brewer
The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. Besides, on-chip interconnection, this technology can potentially be applied for implementation of true single chip radio and radar, interchip communication systems, RFID tags and others.
{"title":"The feasibility of on-chip interconnection using antennas","authors":"K. O. Kenneth, Kihong Kim, B. Floyd, J. Mehta, H. Yoon, Chih-Ming Hung, D. Bravo, T. Dickson, Xiaoling Guo, Ran Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, Dong-Jun Yang, J. Bohorquez, Jie Chen, Eunyoung Seok, L. Gao, A. Sugavanam, Jau-Jr Lin, S. Yu, C. Cao, M. Hwang, Y.-R. Ding, S.-H. Hwang, Hsin-Ta Wu, N. Zhang, J. Brewer","doi":"10.1109/ICCAD.2005.1560204","DOIUrl":"https://doi.org/10.1109/ICCAD.2005.1560204","url":null,"abstract":"The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. Besides, on-chip interconnection, this technology can potentially be applied for implementation of true single chip radio and radar, interchip communication systems, RFID tags and others.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81852390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-07DOI: 10.1109/ICCAD.2004.1382681
Arvind, R. Nikhil, Daniel L. Rosenband, Nirav H. Dave
It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.
{"title":"High-level synthesis: an essential ingredient for designing complex ASICs","authors":"Arvind, R. Nikhil, Daniel L. Rosenband, Nirav H. Dave","doi":"10.1109/ICCAD.2004.1382681","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382681","url":null,"abstract":"It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72675159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is expressed using "don't cares" and we seek the best implementation that does not violate them. However, the calculation and storing of don't care information is CPU and memory-intensive. In this paper, we give an overview of logic synthesis approaches based on techniques developed for Automatic Test Pattern Generation (ATPG). Instead of calculating and storing don't cares explicitly, ATPG-based logic synthesis techniques calculate the flexibility implicitly. Low CPU and memory usage make those techniques applicable for practical industrial circuits. Also, the basic ATPG-based logic level operations create predictable, small layout perturbations, making an ideal foundation for efficient physical synthesis. Theoretical results show that an efficient, yet simple add-a-wire-and-remove-a-wire operation covers all possible complex logic transformations.
{"title":"ATPG-based logic synthesis: an overview","authors":"C. Chang, M. Marek-Sadowska","doi":"10.1145/774572.774688","DOIUrl":"https://doi.org/10.1145/774572.774688","url":null,"abstract":"The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is expressed using \"don't cares\" and we seek the best implementation that does not violate them. However, the calculation and storing of don't care information is CPU and memory-intensive. In this paper, we give an overview of logic synthesis approaches based on techniques developed for Automatic Test Pattern Generation (ATPG). Instead of calculating and storing don't cares explicitly, ATPG-based logic synthesis techniques calculate the flexibility implicitly. Low CPU and memory usage make those techniques applicable for practical industrial circuits. Also, the basic ATPG-based logic level operations create predictable, small layout perturbations, making an ideal foundation for efficient physical synthesis. Theoretical results show that an efficient, yet simple add-a-wire-and-remove-a-wire operation covers all possible complex logic transformations.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77961419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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