It is well known that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway partitioning problem. However, little progress has been made to identify and overcome the weakness of the direct (alternatively called flat) approach. We make the first observation that the performance of iterative improvement based flat multiway partitioner K-FM (L.A. Sanchis, 1989; 1993) is not suitable for today's large scale circuits. Then, we propose a simple yet effective hill climbing method called PM (Pairwise cell Movement) that overcomes the limitation of K-FM and provides partitioners the capability to explore wider range of solution space effectively while ensuring convergence to satisfying suboptimal solutions. The main idea is to reduce the multiway partitioning problem to sets of concurrent bipartitioning problems. Starting with an initial multiway partition of the netlist, we apply 2-way FM (C. Fiduccia and R. Mattheyses, 1982) to pairs of blocks so as to improve the quality of overall multiway partitioning solution. The pairing of blocks is based on the gain of the last pass, and the Pairwise cell Movement (PM) passes continue until no further gain can be obtained. We observe that PM passes are effective in distributing clusters evenly into multiple blocks to minimize the connections across the multiway cutlines. Our iterative improvement based flat multiway partitioner K-PM/LR improves K-FM by a surprising average margin of up to 86.2% and outperforms its counterpart recursive FIM by up to 17.3% when tested on MCNC and large scale ISPD98 benchmark circuits (C.J. Alpert, 1998).
{"title":"Multiway partitioning with pairwise movement","authors":"J. Cong, S. Lim","doi":"10.1145/288548.289079","DOIUrl":"https://doi.org/10.1145/288548.289079","url":null,"abstract":"It is well known that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway partitioning problem. However, little progress has been made to identify and overcome the weakness of the direct (alternatively called flat) approach. We make the first observation that the performance of iterative improvement based flat multiway partitioner K-FM (L.A. Sanchis, 1989; 1993) is not suitable for today's large scale circuits. Then, we propose a simple yet effective hill climbing method called PM (Pairwise cell Movement) that overcomes the limitation of K-FM and provides partitioners the capability to explore wider range of solution space effectively while ensuring convergence to satisfying suboptimal solutions. The main idea is to reduce the multiway partitioning problem to sets of concurrent bipartitioning problems. Starting with an initial multiway partition of the netlist, we apply 2-way FM (C. Fiduccia and R. Mattheyses, 1982) to pairs of blocks so as to improve the quality of overall multiway partitioning solution. The pairing of blocks is based on the gain of the last pass, and the Pairwise cell Movement (PM) passes continue until no further gain can be obtained. We observe that PM passes are effective in distributing clusters evenly into multiple blocks to minimize the connections across the multiway cutlines. Our iterative improvement based flat multiway partitioner K-PM/LR improves K-FM by a surprising average margin of up to 86.2% and outperforms its counterpart recursive FIM by up to 17.3% when tested on MCNC and large scale ISPD98 benchmark circuits (C.J. Alpert, 1998).","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1145/288548.289079","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72388257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degradation when supply energy is limited, and adapting power dissipation to satisfy environmental constraints.
{"title":"Dynamic power management of electronic systems","authors":"L. Benini, A. Bogliolo, G. Micheli","doi":"10.1145/288548.289120","DOIUrl":"https://doi.org/10.1145/288548.289120","url":null,"abstract":"Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degradation when supply energy is limited, and adapting power dissipation to satisfy environmental constraints.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73338386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hoon Choi, Jong-Sun Kim, C. Yoon, I. Park, S. Hwang, C. Kyung
Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, while the previous state-of-the-art approaches generate only the single-cycle instructions or just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applied to the case that instructions are predefined. Experimental results on real applications show that Various given constraints can be met by the generated set of application specific instructions without attaching special hardware accelerators.
{"title":"Synthesis of application specific instructions for embedded DSP software","authors":"Hoon Choi, Jong-Sun Kim, C. Yoon, I. Park, S. Hwang, C. Kyung","doi":"10.1145/288548.289109","DOIUrl":"https://doi.org/10.1145/288548.289109","url":null,"abstract":"Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, while the previous state-of-the-art approaches generate only the single-cycle instructions or just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applied to the case that instructions are predefined. Experimental results on real applications show that Various given constraints can be met by the generated set of application specific instructions without attaching special hardware accelerators.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81920298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A linear optimal test generation algorithm is proposed to decompose serial test vectors into segments with one for each driver. Each driver is assigned a serial vector with two or more transitions for the detection of net and driver faults. As compared to the conventional counting and transition sequences, the reduction is up to 20% for buses and 36% for general networks.
{"title":"A linear optimal test generation algorithm for interconnect testing","authors":"C. Su","doi":"10.1145/288548.288626","DOIUrl":"https://doi.org/10.1145/288548.288626","url":null,"abstract":"A linear optimal test generation algorithm is proposed to decompose serial test vectors into segments with one for each driver. Each driver is assigned a serial vector with two or more transitions for the detection of net and driver faults. As compared to the conventional counting and transition sequences, the reduction is up to 20% for buses and 36% for general networks.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76838647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Hein, V. Nagasamy, B. Rohfleisch, C. Kozyrakis, N. Dutt, F. Catthoor
Summary form only given. The term system-on-silicon has been used to denote the integration of random logic, processor cores, SRAMs, ROMs, and analog ccimponents on the same die. But up to recently, one major component had been missing: high-density DRAMS. Today?s technologies allow the integration of such as data buffering, picture storage, and prograddata storage. In quarter-micron technology, chips with up to 128 Mbit of DRAM and 500 kgates of logic are eminently feasible. This enlarges the system design space tremendously since system architects arc no more restricted to standard commodity DRAMS. We will discuss the market for embedded DRAM applications as well as the associated challenges.
{"title":"Embedded memories in system design - from technology to systems architecture","authors":"S. Hein, V. Nagasamy, B. Rohfleisch, C. Kozyrakis, N. Dutt, F. Catthoor","doi":"10.1145/288548.288549","DOIUrl":"https://doi.org/10.1145/288548.288549","url":null,"abstract":"Summary form only given. The term system-on-silicon has been used to denote the integration of random logic, processor cores, SRAMs, ROMs, and analog ccimponents on the same die. But up to recently, one major component had been missing: high-density DRAMS. Today?s technologies allow the integration of such as data buffering, picture storage, and prograddata storage. In quarter-micron technology, chips with up to 128 Mbit of DRAM and 500 kgates of logic are eminently feasible. This enlarges the system design space tremendously since system architects arc no more restricted to standard commodity DRAMS. We will discuss the market for embedded DRAM applications as well as the associated challenges.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78626176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interface synthesis seeks to automate the process of interconnecting components. There are many levels of interconnection that must be considered including electrical, power, logic, register-transfer, device drivers, and higher software levels. This presentation will cover a vertical slice of the interfacing problem from digital logic up to coordinating communications between software components. The focus will be within an embedded systems context where the interfacing is between processors and memory and peripheral blocks as is the case in system-on-a-chip design. The structure of the tutorial will parallel the history of CAD efforts in this area. We will begin with the early work in interface specification and logic synthesis then proceed on to the problems of interconnecting hardware to processors and their software, and finish with purely software interfaces involving inter-process communication and protocols between multiple processors. At each level we will discuss specification, synthesis, and verification aspects as well as highlight the currently available tools and on-going research efforts.
{"title":"Interface synthesis: a vertical slice from digital logic to software components","authors":"G. Borriello, L. Lavagno, R. Ortega","doi":"10.1145/288548.289119","DOIUrl":"https://doi.org/10.1145/288548.289119","url":null,"abstract":"Interface synthesis seeks to automate the process of interconnecting components. There are many levels of interconnection that must be considered including electrical, power, logic, register-transfer, device drivers, and higher software levels. This presentation will cover a vertical slice of the interfacing problem from digital logic up to coordinating communications between software components. The focus will be within an embedded systems context where the interfacing is between processors and memory and peripheral blocks as is the case in system-on-a-chip design. The structure of the tutorial will parallel the history of CAD efforts in this area. We will begin with the early work in interface specification and logic synthesis then proceed on to the problems of interconnecting hardware to processors and their software, and finish with purely software interfaces involving inter-process communication and protocols between multiple processors. At each level we will discuss specification, synthesis, and verification aspects as well as highlight the currently available tools and on-going research efforts.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85510065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Y. Lin
Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not utilized effectively nor efficiently. Retiming and layout is combined for the first time in this paper. We present heuristics for two key problems: interconnection delay estimation and post-retiming incremental placement. An efficient retiming algorithm incorporating interconnection delay is also proposed. Experimental results show that on the average we can improve the circuit speed by 5.4% targeted toward a 0.52 /spl mu/m CMOS technology. Scaling down the technology to 0.1 /spl mu/m, as much as 25.6% improvement have been achieved.
{"title":"Integrating logic retiming and register placement","authors":"Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Y. Lin","doi":"10.1145/288548.288591","DOIUrl":"https://doi.org/10.1145/288548.288591","url":null,"abstract":"Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not utilized effectively nor efficiently. Retiming and layout is combined for the first time in this paper. We present heuristics for two key problems: interconnection delay estimation and post-retiming incremental placement. An efficient retiming algorithm incorporating interconnection delay is also proposed. Experimental results show that on the average we can improve the circuit speed by 5.4% targeted toward a 0.52 /spl mu/m CMOS technology. Scaling down the technology to 0.1 /spl mu/m, as much as 25.6% improvement have been achieved.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80987215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/ICCAD.1998.742799
R. Aitken, J. Cong, Randy Harr, K. Shepard, W. Wolf
Summary form only given, as follows. The SIA National Technology Roadmap and Ivloore?s Law both predict that logic chips containing one billion transistors will ship by the year 2010. This panel will explore the challenges awaiting the CAD industry as we move toward such huge chip:;. These chips will almost certainly include a variety of technologies, including logic, microprocessor cores, buses, static and dynamic memory, analog circuitry, and possibly micromechanical devices. Challenges loom at all levels of system abstraction, from artwork to architecture, and all aspects of CAD, from data management to algorithms. The panelists, whose expertise ranges from interconnect and noise through system-level synthesis, will begin by summarizing these CAD challenges and identifying key areas where contributions are needed, and then discuss promising research directions.
{"title":"How will CAD handle billion-transistor systems? (panel)","authors":"R. Aitken, J. Cong, Randy Harr, K. Shepard, W. Wolf","doi":"10.1109/ICCAD.1998.742799","DOIUrl":"https://doi.org/10.1109/ICCAD.1998.742799","url":null,"abstract":"Summary form only given, as follows. The SIA National Technology Roadmap and Ivloore?s Law both predict that logic chips containing one billion transistors will ship by the year 2010. This panel will explore the challenges awaiting the CAD industry as we move toward such huge chip:;. These chips will almost certainly include a variety of technologies, including logic, microprocessor cores, buses, static and dynamic memory, analog circuitry, and possibly micromechanical devices. Challenges loom at all levels of system abstraction, from artwork to architecture, and all aspects of CAD, from data management to algorithms. The panelists, whose expertise ranges from interconnect and noise through system-level synthesis, will begin by summarizing these CAD challenges and identifying key areas where contributions are needed, and then discuss promising research directions.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73192669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/ICCAD.1998.742797
S. Dey, J. Abraham, Y. Zorian
Description: To meet aggressive design cycle, complexity, and productivity requirements, more electronic systems than before are being specified and designed at higher levels of abstraction, involve embedded processors and other programmable components, and achieve design re-use vith hard~vareand sofivare components. k order not to compromise the productivity gains obtained by component-based systems, verification and test should be addressed early in the design cycle. This tutorird addresses the challenges, proposed methodologies, and current industrird practices in verification and test of components and component-based systems at higher levels of abstraction.
{"title":"High-level design validation and test","authors":"S. Dey, J. Abraham, Y. Zorian","doi":"10.1109/ICCAD.1998.742797","DOIUrl":"https://doi.org/10.1109/ICCAD.1998.742797","url":null,"abstract":"Description: To meet aggressive design cycle, complexity, and productivity requirements, more electronic systems than before are being specified and designed at higher levels of abstraction, involve embedded processors and other programmable components, and achieve design re-use vith hard~vareand sofivare components. k order not to compromise the productivity gains obtained by component-based systems, verification and test should be addressed early in the design cycle. This tutorird addresses the challenges, proposed methodologies, and current industrird practices in verification and test of components and component-based systems at higher levels of abstraction.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76799801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin overhead and are not supported by boundary scan. We present a novel method to allow a single input line to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, we show that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCAS'85 combinational circuits and 10 largest ISCAS'89 sequential circuits, respectively.
{"title":"Using a single input to support multiple scan chains","authors":"Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang","doi":"10.1145/288548.288563","DOIUrl":"https://doi.org/10.1145/288548.288563","url":null,"abstract":"Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin overhead and are not supported by boundary scan. We present a novel method to allow a single input line to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, we show that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCAS'85 combinational circuits and 10 largest ISCAS'89 sequential circuits, respectively.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77393131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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