Pub Date : 2008-05-18DOI: 10.1109/ISCAS.2008.4542064
D. Bruckmann
Digital signal processing in continuous-time can result in a number of advantages compared to classical sampled data systems, while the inherent advantages of digital implementations with respect to programmability and noise immunity are retained. It turned out however that a critical point of these systems is the implementation of the continuous- time delays, requiring a considerably larger chip area than the delays in sampled data systems. Thus structures with a minimum number of delay elements seem to be advantageous. In this contribution the implementation of continuous-time wave digital filters (WDFs) is considered. This filter type is well- known for its superior properties with respect to stability and sensitivity. Furthermore, by selecting a proper reference structure, WDFs can be implemented with a minimum number of delay elements for a given filter specification thus making them very attractive for continuous-time implementations. Due to the proposed concept a number of advantages are obtained and a very efficient realization in VLSI-technology becomes feasible.
{"title":"Design and realization of continuous-time wave digital filters","authors":"D. Bruckmann","doi":"10.1109/ISCAS.2008.4542064","DOIUrl":"https://doi.org/10.1109/ISCAS.2008.4542064","url":null,"abstract":"Digital signal processing in continuous-time can result in a number of advantages compared to classical sampled data systems, while the inherent advantages of digital implementations with respect to programmability and noise immunity are retained. It turned out however that a critical point of these systems is the implementation of the continuous- time delays, requiring a considerably larger chip area than the delays in sampled data systems. Thus structures with a minimum number of delay elements seem to be advantageous. In this contribution the implementation of continuous-time wave digital filters (WDFs) is considered. This filter type is well- known for its superior properties with respect to stability and sensitivity. Furthermore, by selecting a proper reference structure, WDFs can be implemented with a minimum number of delay elements for a given filter specification thus making them very attractive for continuous-time implementations. Due to the proposed concept a number of advantages are obtained and a very efficient realization in VLSI-technology becomes feasible.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"23 1","pages":"2901-2904"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88196300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-27DOI: 10.1109/ISCAS.2007.378109
T. Kumar, K. D. Rao
This paper presents a robust multiuser detector for combating multiple access interference and impulsive noise in direct-sequence code-division multiple-access (DS-CDMA) communication systems. A new M-estimator is proposed for robustifying the detector. The lower bounds for the explosion and implosion breakdown points of the proposed estimator are derived. For appropriate tuning constants, it is shown that the breakdown points attain the maximum possible value. The approach is also corroborated with simulation results to evaluate the performance of the proposed robust multiuser detector in comparison with the linear decorrelating detector, Huber and Hampel M-estimator based detectors. Simulation results show that, in highly impulsive noise, the proposed detector with the proposed M-estimator with significant performance gain outperforms the linear decorrelating detector, Huber and Hampel M-estimator based detectors in both synchronous and asynchronous non-Gaussian channels.
{"title":"Breakdown Point Analysis of a New M-Estimator for Robust Multiuser Detection in Non-Gaussian Channels","authors":"T. Kumar, K. D. Rao","doi":"10.1109/ISCAS.2007.378109","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378109","url":null,"abstract":"This paper presents a robust multiuser detector for combating multiple access interference and impulsive noise in direct-sequence code-division multiple-access (DS-CDMA) communication systems. A new M-estimator is proposed for robustifying the detector. The lower bounds for the explosion and implosion breakdown points of the proposed estimator are derived. For appropriate tuning constants, it is shown that the breakdown points attain the maximum possible value. The approach is also corroborated with simulation results to evaluate the performance of the proposed robust multiuser detector in comparison with the linear decorrelating detector, Huber and Hampel M-estimator based detectors. Simulation results show that, in highly impulsive noise, the proposed detector with the proposed M-estimator with significant performance gain outperforms the linear decorrelating detector, Huber and Hampel M-estimator based detectors in both synchronous and asynchronous non-Gaussian channels.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"77 1","pages":"3191-3194"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83879229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-27DOI: 10.1109/ISCAS.2007.378171
X. Redondo, J. Pallares, F. Serra-Graells
This paper presents a new low-voltage MOS-only circuit technique to implement oversampling ΣΔ modulators in purely digital CMOS technologies. The basis of the proposed design strategy is a combination of log domain processing and the MOSFET operating in subthreshold. In this sense, compact circuit implementations are given for all the required basic building blocks, such as compressors, integrators, quantizers and DACs. Finally, experimental results are presented for a complete 4th-order 64-oversampling 1-bit ΣΔ modulator integrated using a standard 0.35μm 1-polySi 3-metal digital CMOS technology.
{"title":"A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator","authors":"X. Redondo, J. Pallares, F. Serra-Graells","doi":"10.1109/ISCAS.2007.378171","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378171","url":null,"abstract":"This paper presents a new low-voltage MOS-only circuit technique to implement oversampling ΣΔ modulators in purely digital CMOS technologies. The basis of the proposed design strategy is a combination of log domain processing and the MOSFET operating in subthreshold. In this sense, compact circuit implementations are given for all the required basic building blocks, such as compressors, integrators, quantizers and DACs. Finally, experimental results are presented for a complete 4th-order 64-oversampling 1-bit ΣΔ modulator integrated using a standard 0.35μm 1-polySi 3-metal digital CMOS technology.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"71 1","pages":"17-20"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78745576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-27DOI: 10.1109/ISCAS.2007.377901
M. D. Federico, P. Julián, Tomaso Poggi, M. Storace
In this paper we present a mixed-signal integrated circuit in a standard CMOS 0.5 µm technology implementing a piecewise-linear (PWL) function with three inputs, where each input can be either analog or coded with 8 bits. The output of the circuit is a digital word with 8-bit precision, representing the value of the PWL function at the three-dimensional input. The circuit accesses also a 4 kB external memory, which is addressed with a 12-bit word. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW.
{"title":"A Simplicial PWL Integrated Circuit Realization","authors":"M. D. Federico, P. Julián, Tomaso Poggi, M. Storace","doi":"10.1109/ISCAS.2007.377901","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377901","url":null,"abstract":"In this paper we present a mixed-signal integrated circuit in a standard CMOS 0.5 µm technology implementing a piecewise-linear (PWL) function with three inputs, where each input can be either analog or coded with 8 bits. The output of the circuit is a digital word with 8-bit precision, representing the value of the PWL function at the three-dimensional input. The circuit accesses also a 4 kB external memory, which is addressed with a 12-bit word. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"110 1","pages":"685-688"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73031934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-27DOI: 10.1109/ISCAS.2007.378583
B. Sedighi, M. S. Bakhtiar
In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply.
{"title":"An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS","authors":"B. Sedighi, M. S. Bakhtiar","doi":"10.1109/ISCAS.2007.378583","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378583","url":null,"abstract":"In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"47 1","pages":"1481-1484"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74149901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-01-01DOI: 10.1109/ISCAS.2007.378501
R. Lehto, T. Saramäki, O. Vainio
{"title":"Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse Response","authors":"R. Lehto, T. Saramäki, O. Vainio","doi":"10.1109/ISCAS.2007.378501","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378501","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"300 1","pages":"2052-2055"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76438874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-01-01DOI: 10.1109/ISCAS.2007.378800
Ümit Güz, Hakan Gürkan, B. Yarman
{"title":"A Novel Fast Algorithm for Speech and Audio Coding","authors":"Ümit Güz, Hakan Gürkan, B. Yarman","doi":"10.1109/ISCAS.2007.378800","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378800","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"36 1","pages":"4020-4023"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77061350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-01-01DOI: 10.1109/ISCAS.2006.1692971
Ümit Güz, Hakan Gürkan, B. Yarman
In this paper, the method of speech modeling which is called SYMPES is introduced and it is compared with the commercially available methods. It is shown that for the same compression ratio or better, SYMPES yields considerably better hearing quality over the coders such as G.726 at 16 Kbps and voice excited LPC-10E of 2.4Kbps.
{"title":"A new speech modeling method: SYMPES","authors":"Ümit Güz, Hakan Gürkan, B. Yarman","doi":"10.1109/ISCAS.2006.1692971","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692971","url":null,"abstract":"In this paper, the method of speech modeling which is called SYMPES is introduced and it is compared with the commercially available methods. It is shown that for the same compression ratio or better, SYMPES yields considerably better hearing quality over the coders such as G.726 at 16 Kbps and voice excited LPC-10E of 2.4Kbps.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"11 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2006-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87688780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-05-23DOI: 10.1109/ISCAS.2005.1464890
H. Liu, W. Goh, L. Siek
This paper presents a three-stage 1.8-V 10-GHz ring oscillator, implemented using the 0.18-/spl mu/m digital CMOS technology. The circuit utilizes the feedforward technique at the delay cells and positive feedback provided by a cross-coupled nMOS pair in each delay cell to boost the operation speed of the oscillator. The output frequency ranges from 10.1 to 8.4 GHz with control voltages of 0 to 1.5 V. The simulated result of the phase noise is -99.9 dBc/Hz at 1-MHz offset from the center frequency of 9.2 GHz. The circuit draws 35 mA and 22 mA from the 1.8-V supply when running at the highest and lowest frequencies, respectively.
{"title":"A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers","authors":"H. Liu, W. Goh, L. Siek","doi":"10.1109/ISCAS.2005.1464890","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464890","url":null,"abstract":"This paper presents a three-stage 1.8-V 10-GHz ring oscillator, implemented using the 0.18-/spl mu/m digital CMOS technology. The circuit utilizes the feedforward technique at the delay cells and positive feedback provided by a cross-coupled nMOS pair in each delay cell to boost the operation speed of the oscillator. The output frequency ranges from 10.1 to 8.4 GHz with control voltages of 0 to 1.5 V. The simulated result of the phase noise is -99.9 dBc/Hz at 1-MHz offset from the center frequency of 9.2 GHz. The circuit draws 35 mA and 22 mA from the 1.8-V supply when running at the highest and lowest frequencies, respectively.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"22 1","pages":"1525-1528"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88328924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-05-23DOI: 10.1109/ISCAS.2005.1464595
M. Kamuf, John B. Anderson, V. Öwall
Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.
{"title":"Area and power efficient trellis computational blocks in 0.13µm CMOS","authors":"M. Kamuf, John B. Anderson, V. Öwall","doi":"10.1109/ISCAS.2005.1464595","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464595","url":null,"abstract":"Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13/spl mu/m CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"74 7 1","pages":"344-347"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77845398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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