Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.692906
S. Norsworthy
{"title":"Optimal Nonrecursive Noise Shaping Filters for Oversampling Data Converters Part 2: Applications","authors":"S. Norsworthy","doi":"10.1109/iscas.1993.692906","DOIUrl":"https://doi.org/10.1109/iscas.1993.692906","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"9 1","pages":"1357-1360"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82447098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.692762
M. Milanese, N. Elia
{"title":"Worst-case l1 system identification using perturbed ARMA models","authors":"M. Milanese, N. Elia","doi":"10.1109/iscas.1993.692762","DOIUrl":"https://doi.org/10.1109/iscas.1993.692762","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"93 1","pages":"786-789"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76638854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.692940
R. Hossain, L. Wronski, A. Albicki
{"title":"Double Edge Triggered Devices: Speed and Power Considerations","authors":"R. Hossain, L. Wronski, A. Albicki","doi":"10.1109/iscas.1993.692940","DOIUrl":"https://doi.org/10.1109/iscas.1993.692940","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"22 1","pages":"1491-1494"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86827973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.693006
L. Wang, I. Hartimo
{"title":"Systolic Array for 2-D Circular Convolution Using the Chinese Remainder Theorem","authors":"L. Wang, I. Hartimo","doi":"10.1109/iscas.1993.693006","DOIUrl":"https://doi.org/10.1109/iscas.1993.693006","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"27 1","pages":"1746-1749"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81748131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.692893
Qiuting Huang
{"title":"Linear-phase Filters Configured as a Combination of Sigma-delta Modulator, SC Transversal Filter and a Low-Q Biquad","authors":"Qiuting Huang","doi":"10.1109/iscas.1993.692893","DOIUrl":"https://doi.org/10.1109/iscas.1993.692893","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"24 1","pages":"1306-1309"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91223875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-01DOI: 10.1109/iscas.1993.692905
S. Norsworthy
{"title":"Optimal Nonrecursive Noise Shaping Filters for Oversampling Data Converters Part 1: Theory","authors":"S. Norsworthy","doi":"10.1109/iscas.1993.692905","DOIUrl":"https://doi.org/10.1109/iscas.1993.692905","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"100 1","pages":"1353-1356"},"PeriodicalIF":0.0,"publicationDate":"1993-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79322061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A highly linear four-quadrant analogue BiCMOS multiplier is presented. It operates with ±1.5V supplies and with 2V peak to peak input and output signal wings. It is based on the use of crosscoupled, voltage biased differential pairs. Experimental results of a CMOS test chip are presented that confirm the proposed structure.
{"title":"Highly Linear Four Quadrant Analog BiCMOS Multiplier for ± 1.5 V Supply Operation","authors":"J. Ramírez-Angulo","doi":"10.1049/EL:19921137","DOIUrl":"https://doi.org/10.1049/EL:19921137","url":null,"abstract":"A highly linear four-quadrant analogue BiCMOS multiplier is presented. It operates with ±1.5V supplies and with 2V peak to peak input and output signal wings. It is based on the use of crosscoupled, voltage biased differential pairs. Experimental results of a CMOS test chip are presented that confirm the proposed structure.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"16 1","pages":"1467-1470"},"PeriodicalIF":0.0,"publicationDate":"1992-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73998763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-01DOI: 10.1109/ISCAS.1990.112524
E. Vittoz
The potentialities of CMOS analog VLSI for the implementation of neural systems are demonstrated. It is shown how the various modes of operation of the transistor can be exploited to build very efficient neurons on a very small area with very low power consumption. The connectivity problem can be alleviated by selecting appropriate architectures. Various methods for implementing analog synaptic memories are discussed, and examples of working chips are given.<>
{"title":"Analog VLSI implementation of neural networks","authors":"E. Vittoz","doi":"10.1109/ISCAS.1990.112524","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112524","url":null,"abstract":"The potentialities of CMOS analog VLSI for the implementation of neural systems are demonstrated. It is shown how the various modes of operation of the transistor can be exploited to build very efficient neurons on a very small area with very low power consumption. The connectivity problem can be alleviated by selecting appropriate architectures. Various methods for implementing analog synaptic memories are discussed, and examples of working chips are given.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"79 1","pages":"2524-2527 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74082877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-01DOI: 10.1109/ISCAS.1990.112709
T. Ritoniemi, T. Karema, H. Tenhunen
A method for designing stable 1-b high-order (>or=3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizer's gain in the modulator at the present clock period determines the modulator's stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64.<>
{"title":"Design of stable high order 1-bit sigma-delta modulators","authors":"T. Ritoniemi, T. Karema, H. Tenhunen","doi":"10.1109/ISCAS.1990.112709","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112709","url":null,"abstract":"A method for designing stable 1-b high-order (>or=3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizer's gain in the modulator at the present clock period determines the modulator's stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"45 1","pages":"3267-3270 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75657425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-01DOI: 10.1109/ISCAS.1990.112180
S. Kung
The regular principal components (PC) analysis of stochastic processes is extended to the so-called constrained principal components (CPC) problem. The CPC analysis involves extracting representative components which contain the most information about the original processes, The CPC solution has to be extracted from a given constraint subspace. Therefore, the CPC solution may be adopted to best recover the original signal and simultaneously avoid the undesirably noisy or redundant components. A technique for finding optimal CPC solutions via an orthogonal learning network (OLN) is proposed. The underlying numerical analysis for the theoretical proof of the convergency of OLN is discussed. The same numerical analysis provides a useful estimate of optimal learning rates leading to very fast convergence speed. Simulation and application examples are provided.<>
{"title":"Constrained principal component analysis via an orthogonal learning network","authors":"S. Kung","doi":"10.1109/ISCAS.1990.112180","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112180","url":null,"abstract":"The regular principal components (PC) analysis of stochastic processes is extended to the so-called constrained principal components (CPC) problem. The CPC analysis involves extracting representative components which contain the most information about the original processes, The CPC solution has to be extracted from a given constraint subspace. Therefore, the CPC solution may be adopted to best recover the original signal and simultaneously avoid the undesirably noisy or redundant components. A technique for finding optimal CPC solutions via an orthogonal learning network (OLN) is proposed. The underlying numerical analysis for the theoretical proof of the convergency of OLN is discussed. The same numerical analysis provides a useful estimate of optimal learning rates leading to very fast convergence speed. Simulation and application examples are provided.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"62 1","pages":"719-722 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75855913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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