IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems最新文献

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A 9.4-bit, 28.8-mV range inverter based readout circuit for implantable pressure bridge piezo-resistive sensor 一种用于植入式压桥式压阻传感器的9.4位、28.8 mv量程逆变读出电路

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2014-01-01 DOI: 10.1109/ISCAS.2014.6865650

T. Nguyen, P. Häfliger

This paper presents an energy efficient inverter based readout circuit for implantable pressure bridge piezo-resistive sensor which can achieve 9 bit resolution with 28.8-mV input voltage range. Only one bridge branch is utilized with interchanging supply voltage to achieve net differential input voltage range, hence reducing the power consumption by a half. A gain compensated technique is applied for inverter based switched capacitor amplifier to achieve both power efficiency and high resolution. A two-step auto calibration is applied to eliminate the offset from non-ideal effects of the switched-capacitor amplifier (SC-amp) and comparator delay. The readout system is implemented and simulated in TSMC 90 nm CMOS technology. With supply voltage of 1.2 V, simulation results show that the circuit can achieve 9.4 bit resolution while consuming only 35 μW during 320 μs conversion time. The digital output code has little sensitivity to temperature variation.

提出了一种基于逆变器的可植入式压力桥压阻传感器读出电路，该电路在28.8 mv输入电压范围内可实现9位分辨率。仅使用一个桥支路与交换电源电压，实现净差分输入电压范围，从而减少一半的功耗。在逆变器型开关电容放大器中采用增益补偿技术，既提高了功率效率，又提高了分辨率。采用两步自动校准来消除开关电容放大器(SC-amp)和比较器延迟的非理想影响的偏移。采用台积电90nm CMOS技术对读出系统进行了仿真。仿真结果表明，在电源电压为1.2 V时，电路在320 μs的转换时间内，功耗仅为35 μW，可实现9.4 bit的分辨率。数字输出码对温度变化的敏感性很小。

引用次数: 0

Area and throughput efficient IDCT/IDST architecture for HEVC standard HEVC标准的面积和吞吐量高效IDCT/IDST架构

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2014-01-01 DOI: 10.1109/ISCAS.2014.6865683

Ziyou Yao, Weifeng He, L. Hong, Guanghui He, Zhigang Mao

引用次数: 2

Input stimulus comparison using an adaptive FPGA-based testing system 基于自适应fpga测试系统的输入刺激比较

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2014-01-01 DOI: 10.1109/ISCAS.2014.6865119

S. Pouros, V. Vassios, D. K. Papakostas, A. Hatzopoulos

引用次数: 2

High-Throughput Hardware for Real-Time Spike Overlap Decomposition in Multi-Electrode Neuronal Recording Systems. 多电极神经元记录系统中实时尖峰重叠分解的高通量硬件。

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2014-01-01 Epub Date: 2014-07-28 DOI: 10.1109/ISCAS.2014.6865221

Jelena Dragas, David Jäckel, Felix Franke, Andreas Hierlemann

Spike overlaps occur frequently in dense neuronal network recordings, creating difficulties for spike sorting. Brainmachine interfaces and in vivo studies of neuronal network dynamics often require that an accurate spike sorting be done in real time, with low execution latency (on the order of milliseconds). Moreover, modern neuronal recording systems that feature thousands of electrodes require processing of several tens or hundreds of neurons in parallel. The existing algorithms capable of performing spike overlap decomposition are generally very complex and unsuitable for real-time implementation, especially for an on-chip implementation. Here we present a hardware device capable of processing pair-wise spike overlaps in real time. A previously-published spike sorting algorithm, which is not suitable for processing data of large neuronal networks with low latency, has been optimized for high-throughput, low-latency hardware implementation. The designed hardware architecture has been verified on an FPGA platform. Low spike sorting error rates (0.05) for overlapping spikes have been achieved with a latency of 2.75 ms, rendering the system particularly suitable for use in closed-loop experiments.

在密集的神经网络记录中，脉冲重叠经常发生，这给脉冲分类带来了困难。脑机接口和神经网络动力学的活体研究通常需要实时完成准确的尖峰排序，执行延迟低(毫秒级)。此外，现代神经元记录系统以数千个电极为特征，需要并行处理数十或数百个神经元。现有的尖峰重叠分解算法通常非常复杂，不适合实时实现，特别是在芯片上实现。在这里，我们提出了一种能够实时处理成对尖峰重叠的硬件设备。先前发表的尖峰排序算法不适合处理低延迟的大型神经网络数据，本文针对高吞吐量、低延迟的硬件实现进行了优化。所设计的硬件架构已在FPGA平台上进行了验证。在2.75 ms的延迟下，重叠尖峰的低尖峰分类错误率(0.05)已经实现，使得系统特别适合在闭环实验中使用。

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引用次数: 1

Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors 用于具有高抽取因子的Sigma-Delta adc的功率和面积高效梳式抽取器

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2013-05-19 DOI: 10.1109/ISCAS.2013.6572082

G. Salgado, G. Jovanovic-Dolecek, J. M. Rosa

This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.

本文介绍了一种功率和面积有效的基于梳的抽取结构，特别适用于抽取因子为2的幂次的高值抽取。所提出的拓扑结构有两个阶段，其中第一阶段为非递归形式，第二阶段为递归形式(CIC滤波器)。此外，为了获得更好的混叠抑制效果，对所提出的十进制数结构进行了轻微的修改。仿真结果验证了该方法的有效性。

引用次数: 5

Influence of Prior Knowledge on the Accuracy Limit of Parameter Estimation in Single-Molecule Fluorescence Microscopy. 先验知识对单分子荧光显微镜参数估计精度限制的影响。

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2013-05-01 DOI: 10.1109/ISCAS.2013.6572093

Zhiping Lin, Yau Wong, Raimund J Ober

In estimation theory, it is known that prior knowledge of parameters can improve the Cramér-Rao lower bound (CRLB). In this paper, we study the influence of prior knowledge on the CRLB of the estimates of the parameters that describe the trajectory of a moving object (single molecule). Since the CRLB is obtained from the inverse of the Fisher information matrix, we present a general expression of the Fisher information matrix in terms of the image function, the object trajectory and the prior knowledge matrix. Applying this expression to an object moving linearly in a two-dimensional (2D) plane with two distinct cases of prior knowledge, explicit CRLB expressions are derived. From these expressions, we show that the improvement in the CRLB of the parameter estimates is dependent on which parameters are known.

在估计理论中，已知参数的先验知识可以改善cram - rao下界(CRLB)。在本文中，我们研究了先验知识对描述运动物体(单分子)轨迹参数估计的CRLB的影响。由于CRLB是由Fisher信息矩阵的逆得到的，因此我们给出了Fisher信息矩阵在图像函数、目标轨迹和先验知识矩阵方面的一般表达式。将此表达式应用于具有两种不同先验知识的二维(2D)平面线性移动的对象，推导出显式CRLB表达式。从这些表达式中，我们证明了参数估计的CRLB的改进取决于哪些参数是已知的。

引用次数: 2

Behavioral modeling techniques for teaching communication circuits and systems 用于通信电路和系统教学的行为建模技术

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271796

J. M. Rosa

This paper discusses the use of behavioral simulation techniques to improve the quality of teaching/learning circuits and systems for communications. The proposed pedagogical methodology has been applied in several electrical engineering courses, in both undergraduate and master degrees. The method allows students to better understand some complex circuit-and physical-level phenomena, by describing them at a higher abstraction level. In addition to enhance their understanding of design problems and skills, students become more motivated and satisfied. As an application, two case studies are considered in this work: a radio-frequency front-end system and an analog-to-digital converter. In both cases, behavioral models of the different building blocks have been implemented in MATLAB/SIMULINK and used by the students enrolled in two courses named: Electronic Circuits for Communications and Wireless Transceivers: Standards, Techniques and Architectures.

本文讨论了使用行为模拟技术来提高教学/学习电路和通信系统的质量。提出的教学方法已应用于几个电气工程课程，在本科和硕士学位。这种方法可以让学生更好地理解一些复杂的电路和物理现象，通过在更高的抽象层次上描述它们。除了提高他们对设计问题和技能的理解，学生们变得更有动力和满意。作为应用，本工作考虑了两个案例研究:射频前端系统和模数转换器。在这两种情况下，不同构建块的行为模型已经在MATLAB/SIMULINK中实现，并由参加两门课程的学生使用:通信电子电路和无线收发器:标准，技术和体系结构。

引用次数: 4

Novel algorithm for the real time multi-feature detection in laser beam welding 激光焊接多特征实时检测的新算法

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271618

N. Leonardo, T. Ronald, Abt Felix, Heider Andreas, Blug Andreas, Hofler Heinrich

In this paper, a novel visual multi-feature detecting algorithm for the real time monitoring and control of laser beam welding (LBW) processes is discussed. It was implemented in the Eye-RIS vision system (VS) which includes a focal plane processor programmable by typical Cellular Neural Network (CNN) operators. The algorithm is based on the extraction of “spatters” - explosions of rear melt pool - to provide on-line quality information about the process and on the detection of the full penetration hole (FPH) for the laser power control to maintain a constant penetration depth into the workpiece. A single image evaluating step is performed in about 90 µs.

本文讨论了一种用于激光焊接过程实时监测和控制的视觉多特征检测算法。它在Eye-RIS视觉系统(VS)中实现，该系统包括一个焦平面处理器，由典型的细胞神经网络(CNN)操作员可编程。该算法是基于“飞溅”的提取-后部熔池爆炸-提供在线质量信息的过程和检测全穿透孔(FPH)的激光功率控制，以保持一个恒定的穿透深度到工件。单个图像评估步骤在大约90µs内完成。

引用次数: 5

On adaptive bounded synchronization in Power Network models 电网模型中的自适应有界同步

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2012-01-01 DOI: 10.1109/ISCAS.2012.6271570

P. D. Lellis, M. Bernardo

引用次数: 0

An optimum linear phase approximation with small delay obtained by the manipulation of all-pass Padé approximants 利用全通帕德帕尔近似获得了一种具有小延迟的最佳线性相位近似

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2011-05-15 DOI: 10.1109/ISCAS.2011.5938053

Douglas David Baptista de Souza, S. N. Filho

This paper proposes a new rational approximation of a symmetric impulse response. The proposed technique uses both the Pade method to obtain an all-pass approximation of e−sT and specific zeros in order to achieve good phase linearity characteristics. The obtained functions, when compared with other classical ones, such as Bessel, for instance, present better linear phase characteristics with a smaller delay. Another advantage of this approach is that the transfer functions are provided in explicit forms. Finally, the effect of varying parameters and results from simulations are shown.

本文提出了对称脉冲响应的一种新的有理逼近。所提出的技术使用Pade方法来获得e−sT的全通近似和特定零，以获得良好的相位线性特性。与其他经典函数(如贝塞尔函数)相比，所得到的函数具有更好的线性相位特性和较小的延迟。这种方法的另一个优点是传递函数以显式形式提供。最后给出了参数变化的影响和仿真结果。

引用次数: 2

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