Pub Date : 2011-05-01DOI: 10.1109/ISCAS.2011.5937531
N. Trung, P. Häfliger
This paper describes a 250-Mb/s to 3Gb/s continuous rate clock and data recovery (CDR) circuit in the TSMC 90nm CMOS process. The circuit first recovers the precise clock frequency from bit-serial 27−1 pseudorandom binary-sequences (PRBS) across a wide range of data rates. Thus, the requirements for loop bandwidth and locking range is much relaxed for the second step of phase detection, implemented as a 1/5 rate linear phase detector (PD) offering reduced clock operating frequency and low jitter. The CDR achieves 12.6-ps peak-to-peak jitter at 2.5Gb/s and consumes a current of 3.84mA in post-layout simulation.
{"title":"250Mb/s to 3Gb/s unilateral continuous rate CDR using precise frequency detector and 1/5-rate linear phase detector","authors":"N. Trung, P. Häfliger","doi":"10.1109/ISCAS.2011.5937531","DOIUrl":"https://doi.org/10.1109/ISCAS.2011.5937531","url":null,"abstract":"This paper describes a 250-Mb/s to 3Gb/s continuous rate clock and data recovery (CDR) circuit in the TSMC 90nm CMOS process. The circuit first recovers the precise clock frequency from bit-serial 27−1 pseudorandom binary-sequences (PRBS) across a wide range of data rates. Thus, the requirements for loop bandwidth and locking range is much relaxed for the second step of phase detection, implemented as a 1/5 rate linear phase detector (PD) offering reduced clock operating frequency and low jitter. The CDR achieves 12.6-ps peak-to-peak jitter at 2.5Gb/s and consumes a current of 3.84mA in post-layout simulation.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"13 2 1","pages":"181-184"},"PeriodicalIF":0.0,"publicationDate":"2011-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81305695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-08-03DOI: 10.1109/ISCAS.2010.5537004
Daniel Brüderle, Johannes Bill, Bernhard A. Kaplan, J. Kremkow, K. Meier, Eric Müller, J. Schemmel
We will set up a fully functional system consisting of a custom design hardware framework (Figures 1 and 2) with the neural network chips described in the appended 4-page paper, Section II-A. The framework is connected digitally to a host PC, on which we will run a software that provides the simulator-like, flexible and non-expert usability of the neuromorphic device as described in the appended paper, Section II-B. We will also connect an oscilloscope via which arbitrarily selectable neuron membranes or other analog parameters can be recorded directly from the chips.
{"title":"Live demonstration: Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system","authors":"Daniel Brüderle, Johannes Bill, Bernhard A. Kaplan, J. Kremkow, K. Meier, Eric Müller, J. Schemmel","doi":"10.1109/ISCAS.2010.5537004","DOIUrl":"https://doi.org/10.1109/ISCAS.2010.5537004","url":null,"abstract":"We will set up a fully functional system consisting of a custom design hardware framework (Figures 1 and 2) with the neural network chips described in the appended 4-page paper, Section II-A. The framework is connected digitally to a host PC, on which we will run a software that provides the simulator-like, flexible and non-expert usability of the neuromorphic device as described in the appended paper, Section II-B. We will also connect an oscilloscope via which arbitrarily selectable neuron membranes or other analog parameters can be recorded directly from the chips.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"49 1","pages":"2783"},"PeriodicalIF":0.0,"publicationDate":"2010-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80754110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-01DOI: 10.1109/ISCAS.2010.5537283
Shoushun Chen, Wei Tang, E. Culurciello
In this paper we present a low power temporaldifference image sensor with wireless communication capability designed specifically for imaging sensor networks. The eventbased image sensor features a 64×64 pixel array and can also report standard analog intensity images. An ultra-wideband (UWB) radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor wakes up when it detects enough scene changes and only communicates meaningful frames. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to 4 m with rates of 1.3 Mbps and 160 fps.
{"title":"A 64×64 pixels UWB wireless temporal-difference digital image sensor","authors":"Shoushun Chen, Wei Tang, E. Culurciello","doi":"10.1109/ISCAS.2010.5537283","DOIUrl":"https://doi.org/10.1109/ISCAS.2010.5537283","url":null,"abstract":"In this paper we present a low power temporaldifference image sensor with wireless communication capability designed specifically for imaging sensor networks. The eventbased image sensor features a 64×64 pixel array and can also report standard analog intensity images. An ultra-wideband (UWB) radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor wakes up when it detects enough scene changes and only communicates meaningful frames. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to 4 m with rates of 1.3 Mbps and 160 fps.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"6 1","pages":"1404-1407"},"PeriodicalIF":0.0,"publicationDate":"2010-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89113272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-01DOI: 10.1109/ISCAS.2010.5537016
P. Häfliger
A prototype for a wireless implantable sensor system is demonstrated intended for a pill sized micro-implant for blood sugar monitoring. Power is sent and telemetry data received over a near field inductive link. The implant system is almost completely realized on a single CMOS ASIC, excepting three surface mounted capacitors, the coil antenna and the sensor. For this demonstration, the ASIC is packaged and mounted with the 4 other components on a PCB, and the glucose sensor is substituted with either a potentiometer or an atmospheric pressure sensor. In the targeted highly miniaturized implantable micro system all components (including antenna and sensor) will be integrated into a pill sized LTCC (low temperature cofired ceramics) package. The total implant power budget with the minimal supply voltage of 2.5V is at 76μW. This number includes the power for various test structures that will be unnecessary for an industrial prototype, which is expected to operate below 20μW. A simple demonstrator of the reader is implemented on another PCB with a two digit hexadecimal LED display to show the telemetry data. This demo is associated with the BioCAS and the Sensory Systems track and is based on the publication [1] I. DEMONSTRATION SETUP The demonstrator consists of two PCBs: a prototype for the reader and a prototype for the implant as depicted in figure 1. The upper board is the reader prototype, powered by a 9V battery. It sends power on a 13.56MHz carrier to the implant prototype and receives telemetry data on the same link. The main component is a Xilinx CoolRunner II CPLD. The sensor value is displayed on a two digit hexadecimal LED display. The lower board is the implant prototype. Either a potentiometer or a air pressure sensor can be connected, in lieu of the targeted glucose sensor that is still under development. The implant prototype depicted contains a number of configuration switches which will be removed and the configuration will be hardwired for the demonstrator that will be brought to ISCAS 2010. This prototype’s approximate dimension will either be 2.5cm x 5cm, an area which is required by the ASIC package and the coil antenna, or merely 2cm x 2cm if the ASIC is wire bonded directly onto the PCB. II. VISITOR INTERACTION AND EXPERIENCE A. Asynchronous Pulse Density Modulation The implant does not perform a normal analog to digital conversion (ADC), but an analog to analog conversion, where the analog sensor value is translated into an analog/asynchronous inter pulse interval [1]. These pulses are conveyed to the reader over the inductive link by load modulation. The real ADC then simply consists of counting the pulses over a given interval. The decoded pulses can be observed on a portable oscilloscope and the correspondence of pulseintervals, the LED display and the ’sensor’ can be observed while the visitor tweaks the ’sensor’-potentiometer. B. Tuning the Transmitted Power If the reader is not close enough to the implant antenna, the
演示了一种用于血糖监测的药丸大小的微型植入物的无线植入式传感器系统的原型。电能通过近场感应链路发送，遥测数据通过近场感应链路接收。除了三个表面安装电容器、线圈天线和传感器外，植入系统几乎完全在单个CMOS ASIC上实现。在本演示中，ASIC与其他4个组件一起封装并安装在PCB上，葡萄糖传感器由电位器或大气压传感器代替。在目标高度小型化的可植入微系统中，所有组件(包括天线和传感器)将集成到一个药丸大小的LTCC(低温共烧陶瓷)封装中。最小供电电压为2.5V时，植入体总功率预算为76μW。这个数字包括了工业样机所需的各种测试结构的功率，预计其工作功率将低于20μW。在另一块PCB上实现了一个简单的阅读器演示，该演示带有一个两位数十六进制LED显示屏来显示遥测数据。该演示与BioCAS和感官系统相关，并以出版物[1]i为基础。演示设置演示器由两个pcb组成:如图1所示的读取器原型和植入物原型。上面的板是阅读器原型，由9V电池供电。它通过13.56兆赫的载波向植入原型发送能量，并在同一链路上接收遥测数据。主要部件是Xilinx CoolRunner II CPLD。传感器值显示在两位数十六进制LED显示屏上。下面的板是植入物原型。可以连接电位器或气压传感器，以代替仍在开发中的目标葡萄糖传感器。所描述的植入原型包含许多配置开关，这些开关将被移除，并且配置将被硬连接到将被带到ISCAS 2010的演示器中。该原型的大致尺寸将是2.5cm x 5cm，这是ASIC封装和线圈天线所需的面积，或者如果ASIC直接连接到PCB上，则仅为2cm x 2cm。2a .异步脉冲密度调制植入物不执行正常的模拟到数字转换(ADC)，而是模拟到模拟转换，其中模拟传感器值被转换为模拟/异步脉冲间隔[1]。这些脉冲通过负载调制通过感应链路传送给阅读器。真正的ADC只是在给定的间隔内对脉冲进行计数。解码后的脉冲可以在便携式示波器上观察到，当参观者调整“传感器”电位器时，可以观察到脉冲间隔、LED显示屏和“传感器”的对应关系。B.调整发射功率如果读写器离植入物天线不够近，植入物既不通电，也不能在感应链路上发送数据:LED显示00。只有当植入物移动到离阅读器足够近的地方，才会传送脉冲并显示一个数字。然而，最初的权力将不足以让ASIC的内部监管机构正常运作。因此，脉冲频率将不能真实地反映传感器值。移动更近，功率将变得足够，但在某些点上ASIC上的内部整流电压将变得太高，并有可能损坏ASIC。这是防止内部可逆保险丝(打开无限负载)，它也发送脉冲在高频回阅读器。阅读器显示器将通过闪烁的数字点来指示这一点。更先进的原型阅读器通过逐渐增加载波功率，直到信号过电压，然后在每次读取前(每5分钟一次)稍微降低功率来实现最佳功率传输。
{"title":"Live demonstration: Inductive power and telemetry for micro-implant","authors":"P. Häfliger","doi":"10.1109/ISCAS.2010.5537016","DOIUrl":"https://doi.org/10.1109/ISCAS.2010.5537016","url":null,"abstract":"A prototype for a wireless implantable sensor system is demonstrated intended for a pill sized micro-implant for blood sugar monitoring. Power is sent and telemetry data received over a near field inductive link. The implant system is almost completely realized on a single CMOS ASIC, excepting three surface mounted capacitors, the coil antenna and the sensor. For this demonstration, the ASIC is packaged and mounted with the 4 other components on a PCB, and the glucose sensor is substituted with either a potentiometer or an atmospheric pressure sensor. In the targeted highly miniaturized implantable micro system all components (including antenna and sensor) will be integrated into a pill sized LTCC (low temperature cofired ceramics) package. The total implant power budget with the minimal supply voltage of 2.5V is at 76μW. This number includes the power for various test structures that will be unnecessary for an industrial prototype, which is expected to operate below 20μW. A simple demonstrator of the reader is implemented on another PCB with a two digit hexadecimal LED display to show the telemetry data. This demo is associated with the BioCAS and the Sensory Systems track and is based on the publication [1] I. DEMONSTRATION SETUP The demonstrator consists of two PCBs: a prototype for the reader and a prototype for the implant as depicted in figure 1. The upper board is the reader prototype, powered by a 9V battery. It sends power on a 13.56MHz carrier to the implant prototype and receives telemetry data on the same link. The main component is a Xilinx CoolRunner II CPLD. The sensor value is displayed on a two digit hexadecimal LED display. The lower board is the implant prototype. Either a potentiometer or a air pressure sensor can be connected, in lieu of the targeted glucose sensor that is still under development. The implant prototype depicted contains a number of configuration switches which will be removed and the configuration will be hardwired for the demonstrator that will be brought to ISCAS 2010. This prototype’s approximate dimension will either be 2.5cm x 5cm, an area which is required by the ASIC package and the coil antenna, or merely 2cm x 2cm if the ASIC is wire bonded directly onto the PCB. II. VISITOR INTERACTION AND EXPERIENCE A. Asynchronous Pulse Density Modulation The implant does not perform a normal analog to digital conversion (ADC), but an analog to analog conversion, where the analog sensor value is translated into an analog/asynchronous inter pulse interval [1]. These pulses are conveyed to the reader over the inductive link by load modulation. The real ADC then simply consists of counting the pulses over a given interval. The decoded pulses can be observed on a portable oscilloscope and the correspondence of pulseintervals, the LED display and the ’sensor’ can be observed while the visitor tweaks the ’sensor’-potentiometer. B. Tuning the Transmitted Power If the reader is not close enough to the implant antenna, the","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"14 1","pages":"2775"},"PeriodicalIF":0.0,"publicationDate":"2010-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84333706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-01DOI: 10.1109/ISCAS.2010.5537830
Z. Kong, A. Do
{"title":"A 16Kb 10T-SRAM with 4x read-power reduction","authors":"Z. Kong, A. Do","doi":"10.1109/ISCAS.2010.5537830","DOIUrl":"https://doi.org/10.1109/ISCAS.2010.5537830","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2 1","pages":"3485-3488"},"PeriodicalIF":0.0,"publicationDate":"2010-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84810267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-24DOI: 10.1109/ISCAS.2009.5117873
M. Wenk, P. Luethi, T. Koch, Patrick Maechler, N. Felber, W. Fichtner, M. Lerjen
The goal of the demonstration is to show the visitor how MIMO-OFDM communication works and what gains in terms of throughput, link reliability, etc. can be achieved, visualized by different experiments.
{"title":"Live Demonstration: Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed","authors":"M. Wenk, P. Luethi, T. Koch, Patrick Maechler, N. Felber, W. Fichtner, M. Lerjen","doi":"10.1109/ISCAS.2009.5117873","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117873","url":null,"abstract":"The goal of the demonstration is to show the visitor how MIMO-OFDM communication works and what gains in terms of throughput, link reliability, etc. can be achieved, visualized by different experiments.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"39 1","pages":"793"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86451466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-24DOI: 10.1109/ISCAS.2009.5118114
iroomi
This paper proposes a new sine wave approximation method and the proposed method is used as the phase amplitude converter of direct digital frequency synthesizer (DDFS). As the circuit size of the proposed method grows exponentially in proportion to the purity of the generated signal, an error compensation ROM is combined to improve the signal purity while keeping the circuit size small. VHDL simulations are conducted to test the DDFS and the results show that the circuit size of the proposed DDFS is about 40% smaller than that of the conventional DDFS.
{"title":"DDFS with new sinusoid approximation based on harmonics removal","authors":"iroomi","doi":"10.1109/ISCAS.2009.5118114","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118114","url":null,"abstract":"This paper proposes a new sine wave approximation method and the proposed method is used as the phase amplitude converter of direct digital frequency synthesizer (DDFS). As the circuit size of the proposed method grows exponentially in proportion to the purity of the generated signal, an error compensation ROM is combined to improve the signal purity while keeping the circuit size small. VHDL simulations are conducted to test the DDFS and the results show that the circuit size of the proposed DDFS is about 40% smaller than that of the conventional DDFS.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"1955 1","pages":"1751-1754"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87770523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-01DOI: 10.1109/ISCAS.2009.5118468
F. Javid, H. Aboushady, N. Beilleau, D. Morche
{"title":"Effect of OP-amp Phase Margin on SC SigmaDelta Modulator with Bulk Acoustic Wave Resonators","authors":"F. Javid, H. Aboushady, N. Beilleau, D. Morche","doi":"10.1109/ISCAS.2009.5118468","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118468","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"9 1","pages":"3138-3141"},"PeriodicalIF":0.0,"publicationDate":"2009-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78399845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-18DOI: 10.1109/ISCAS.2008.4542162
Rashmi Ramesh Racch, P. Mohan
In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.
{"title":"Implementation of AES S-Boxes using combinational logic","authors":"Rashmi Ramesh Racch, P. Mohan","doi":"10.1109/ISCAS.2008.4542162","DOIUrl":"https://doi.org/10.1109/ISCAS.2008.4542162","url":null,"abstract":"In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"446 1","pages":"3294-3297"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79667981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-18DOI: 10.1109/ISCAS.2008.4541557
J. A. Hernández, F. Gómez-Castañeda, J. Moreno-Cadenas
In some fuzzy systems the number of rules and the membership functions are estimated by designers, often being a tedious task. In this paper we describe a neurofuzzy system (SIMAP) able to build its structure and membership functions using only the input-output data. The system compresses the input-output data, minimizing predictive error by the increment of an input vigilance-parameter, in a similar way to the fuzzy-artmap neural network (G A. Carpenter et al., 1992). In the SIMAP network the output-clusters are weighted to obtain the final output vector, implementing a continuous map. A method for calculating the membership functions in neurofuzzy systems is proposed. These membership functions are used to operate the SIMAP network. The softness of the inference mechanism can be controlled adjusting a single fuzziness-parameter p.
在一些模糊系统中，规则和隶属函数的数量是由设计者来估计的，这往往是一项繁琐的任务。在本文中，我们描述了一个神经模糊系统(SIMAP)，它能够仅使用输入输出数据来构建其结构和隶属函数。该系统压缩输入输出数据，通过增加输入警戒参数来最小化预测误差，类似于fuzzy-artmap神经网络(G . a . Carpenter et al.， 1992)。在SIMAP网络中，对输出簇进行加权得到最终的输出向量，实现连续映射。提出了一种计算神经模糊系统隶属函数的方法。这些隶属函数用于操作SIMAP网络。该推理机制的柔软度可以通过调节单个模糊参数p来控制。
{"title":"A neurofuzzy selfmade network with output dependable on a single parameter","authors":"J. A. Hernández, F. Gómez-Castañeda, J. Moreno-Cadenas","doi":"10.1109/ISCAS.2008.4541557","DOIUrl":"https://doi.org/10.1109/ISCAS.2008.4541557","url":null,"abstract":"In some fuzzy systems the number of rules and the membership functions are estimated by designers, often being a tedious task. In this paper we describe a neurofuzzy system (SIMAP) able to build its structure and membership functions using only the input-output data. The system compresses the input-output data, minimizing predictive error by the increment of an input vigilance-parameter, in a similar way to the fuzzy-artmap neural network (G A. Carpenter et al., 1992). In the SIMAP network the output-clusters are weighted to obtain the final output vector, implementing a continuous map. A method for calculating the membership functions in neurofuzzy systems is proposed. These membership functions are used to operate the SIMAP network. The softness of the inference mechanism can be controlled adjusting a single fuzziness-parameter p.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"872-875"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82135117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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