Pub Date : 2025-06-17DOI: 10.1109/OJPEL.2025.3579781
Ahmed Elottri;Ali Sharida;Lakhdar Mzouz;Ahmed Hafaifa;Ahmed Lakhdar Kouzou;Sertac Bayhan;Haitham Abu-Rub
This paper presents a novel control strategy for integrating shunt active power filter (SAPF) functionality as an ancillary service in electric vehicle (EV) chargers. The proposed approach employs a bi-directional sliding mode control (BD-SMC) technique to enhance power quality by effectively mitigating harmonics and improving grid stability. The BD-SMC is designed to fulfill the charging requirements including constant current and constant voltage charging modes, in addition to acting as a SAPF when needed. This approach aims to address two critical challenges in modern power systems: mitigating the harmonics introduced by the non-linear loads and enhancing grid stability through the energy storage capabilities of EV batteries. The proposed system enables bi-directional energy flow between the grid and EV batteries, allowing for the batteries to act as both load and storage units. The proposed system is validated through hardware experiments under various scenarios, including steady-state, transient, normal, and abnormal grid voltage condition.
{"title":"Seamless Integration of Shunt Active Power Filtering in Fast EV Chargers for Grid Ancillary Services","authors":"Ahmed Elottri;Ali Sharida;Lakhdar Mzouz;Ahmed Hafaifa;Ahmed Lakhdar Kouzou;Sertac Bayhan;Haitham Abu-Rub","doi":"10.1109/OJPEL.2025.3579781","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3579781","url":null,"abstract":"This paper presents a novel control strategy for integrating shunt active power filter (SAPF) functionality as an ancillary service in electric vehicle (EV) chargers. The proposed approach employs a bi-directional sliding mode control (BD-SMC) technique to enhance power quality by effectively mitigating harmonics and improving grid stability. The BD-SMC is designed to fulfill the charging requirements including constant current and constant voltage charging modes, in addition to acting as a SAPF when needed. This approach aims to address two critical challenges in modern power systems: mitigating the harmonics introduced by the non-linear loads and enhancing grid stability through the energy storage capabilities of EV batteries. The proposed system enables bi-directional energy flow between the grid and EV batteries, allowing for the batteries to act as both load and storage units. The proposed system is validated through hardware experiments under various scenarios, including steady-state, transient, normal, and abnormal grid voltage condition.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1110-1122"},"PeriodicalIF":5.0,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11036705","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-17DOI: 10.1109/OJPEL.2025.3580399
Lang Li;Xiaochao Hou;Siqi Fu
This paper presents a decentralized adaptive control for cascaded-type virtual synchronous generators (CVSGs) in microgrids. By leveraging a frequency correction term derived from the local power derivative, the virtual inertia is adaptively adjusted without relying on phase-locked loops (PLLs), enabling a fully communication-free implementation. Compared to the existing methods, the need for PLLs is eliminated. The main novelty of the proposed method is the integration of adaptive inertia, PLL-free control and decentralization. Next, the stability of the proposed controller is assessed using the Lyapunov energy function method. Finally, its performance is validated through MATLAB/Simulink simulation and experiments.
{"title":"Decentralized Adaptive Control With Virtual Inertia for Cascaded-Type VSGs","authors":"Lang Li;Xiaochao Hou;Siqi Fu","doi":"10.1109/OJPEL.2025.3580399","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3580399","url":null,"abstract":"This paper presents a decentralized adaptive control for cascaded-type virtual synchronous generators (CVSGs) in microgrids. By leveraging a frequency correction term derived from the local power derivative, the virtual inertia is adaptively adjusted without relying on phase-locked loops (PLLs), enabling a fully communication-free implementation. Compared to the existing methods, the need for PLLs is eliminated. The main novelty of the proposed method is the integration of adaptive inertia, PLL-free control and decentralization. Next, the stability of the proposed controller is assessed using the Lyapunov energy function method. Finally, its performance is validated through MATLAB/Simulink simulation and experiments.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1123-1134"},"PeriodicalIF":5.0,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039065","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The fundamental frequency of high speed permanent magnet synchronous motor (HSPMSM) is relatively high (possibly exceeding 1 kHz), which can lead to low carrier ratio. Model predictive control (MPC) has the advantages of simple principles, easy implementation, and the ability to handle nonlinear systems. Therefore, adopting MPC in HSPMSM drivers can bring better control performance. Dual-vector model predictive current control (DV-MPCC) manipulates two voltage vectors in one control cycle, which can have higher control accuracy than that of single-vector model predictive current control (SV-MPCC). However, for HSPMSM, the stator inductance of HSPMSM is minimal (10-4 H). Therefore, during start-up and low-speed operation, the stator current ripple is relatively large, which would exacerbate torque ripple. Therefore, this paper proposes an adaptive duty-cycle adjustment-based dual-vector MPCC (AD-MPCC), which can reduce stator current and torque ripple during start-up and low-speed operation. Meanwhile, an improved error-correction Smith (IEC-Smith) structure compensator is adopted, providing better delay compensation characteristics and reducing the statice error. Finally, the experimental results validate the effectiveness and feasibility of the proposed method.
{"title":"Adaptive Duty-Cycle Adjustment Based Dual-Vector Model Predictive Current Control for High Speed PMSM","authors":"Mingli Ji;Xiaoqiang Li;Miao Xie;Weijie Xue;Xiaojie Wu","doi":"10.1109/OJPEL.2025.3579368","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3579368","url":null,"abstract":"The fundamental frequency of high speed permanent magnet synchronous motor (HSPMSM) is relatively high (possibly exceeding 1 kHz), which can lead to low carrier ratio. Model predictive control (MPC) has the advantages of simple principles, easy implementation, and the ability to handle nonlinear systems. Therefore, adopting MPC in HSPMSM drivers can bring better control performance. Dual-vector model predictive current control (DV-MPCC) manipulates two voltage vectors in one control cycle, which can have higher control accuracy than that of single-vector model predictive current control (SV-MPCC). However, for HSPMSM, the stator inductance of HSPMSM is minimal (10-4 H). Therefore, during start-up and low-speed operation, the stator current ripple is relatively large, which would exacerbate torque ripple. Therefore, this paper proposes an adaptive duty-cycle adjustment-based dual-vector MPCC (AD-MPCC), which can reduce stator current and torque ripple during start-up and low-speed operation. Meanwhile, an improved error-correction Smith (IEC-Smith) structure compensator is adopted, providing better delay compensation characteristics and reducing the statice error. Finally, the experimental results validate the effectiveness and feasibility of the proposed method.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1081-1093"},"PeriodicalIF":5.0,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11033197","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-06DOI: 10.1109/OJPEL.2025.3577453
Marco Menga;Lucio Barbato;Gianpatrizio Bianco;Luigi Mascolo;Gabriele Nardelli;Francesco Renna;Gianluca Sapienza;Chiara Micillo;Sergio Bruno;Cosimo Iurlaro;Massimo La Scala
In the energy transition scenario, the security of small isolated electrical networks is challenged by the pervasive Renewable Energy Sources (RES) penetration. This paper presents a hierarchical control architecture designed within the framework of an Italian industrial research project. The proposed control architecture aims to allocate adequate operating reserve during the operation of isolated microgrids in the presence of high RES penetration. To validate its performances under realistic conditions, the architecture was implemented and tested in a Hardware-in-the-Loop simulation environment, which employed Geographically Distributed Real-Time Simulation to exploit the software and hardware facilities of two separate laboratories. The set-up serves as a cyber-physical demonstrator, enabling the assessment of the readiness level and effectiveness of the proposed control architecture in ensuring the secure operation of the isolated electrical network of a real Italian small island under vulnerable operating conditions.
{"title":"Geographically Distributed Real-Time Simulation of a Hierarchical Control Architecture for Isolated Microgrids","authors":"Marco Menga;Lucio Barbato;Gianpatrizio Bianco;Luigi Mascolo;Gabriele Nardelli;Francesco Renna;Gianluca Sapienza;Chiara Micillo;Sergio Bruno;Cosimo Iurlaro;Massimo La Scala","doi":"10.1109/OJPEL.2025.3577453","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3577453","url":null,"abstract":"In the energy transition scenario, the security of small isolated electrical networks is challenged by the pervasive Renewable Energy Sources (RES) penetration. This paper presents a hierarchical control architecture designed within the framework of an Italian industrial research project. The proposed control architecture aims to allocate adequate operating reserve during the operation of isolated microgrids in the presence of high RES penetration. To validate its performances under realistic conditions, the architecture was implemented and tested in a Hardware-in-the-Loop simulation environment, which employed Geographically Distributed Real-Time Simulation to exploit the software and hardware facilities of two separate laboratories. The set-up serves as a cyber-physical demonstrator, enabling the assessment of the readiness level and effectiveness of the proposed control architecture in ensuring the secure operation of the isolated electrical network of a real Italian small island under vulnerable operating conditions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1135-1147"},"PeriodicalIF":5.0,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11027674","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power electronic converters are essential in modern energy systems, facilitating efficient energy conversion in applications such as renewable energy, transportation, and industry. Power semiconductors are crucial to ensure reliability within these converters, often representing the weakest link in performance and durability. Failures in these devices can lead to costly downtime, decreased performance, and safety risks in demanding applications. This article provides a comprehensive analysis of the reliability challenges and solutions associated with power semiconductors, specifically focusing on silicon (Si) IGBTs and silicon carbide (SiC) MOSFETs. It examines key failure mechanisms, such as gate-oxide degradation and thermo-mechanical aging, at both the chip and package levels. Additionally, the article offers a market-oriented overview of standard power semiconductor packages and insights into current manufacturing trends and their implications for reliability. It also explores Active Thermal Control (ATC) techniques, such as gate voltage modulation, which can be implemented at the user level to mitigate stress-related failures. The findings intend to inform future researchers and developers, ensuring that power electronics systems can meet the increasing demand for reliable, efficient, and safe energy solutions.
{"title":"Reliability of Power Semiconductor Modules: A State-of-the-Art Review","authors":"Eneko Agirrezabala;Iosu Aizpuru;David Garrido;Ane Portillo","doi":"10.1109/OJPEL.2025.3576994","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3576994","url":null,"abstract":"Power electronic converters are essential in modern energy systems, facilitating efficient energy conversion in applications such as renewable energy, transportation, and industry. Power semiconductors are crucial to ensure reliability within these converters, often representing the weakest link in performance and durability. Failures in these devices can lead to costly downtime, decreased performance, and safety risks in demanding applications. This article provides a comprehensive analysis of the reliability challenges and solutions associated with power semiconductors, specifically focusing on silicon (Si) IGBTs and silicon carbide (SiC) MOSFETs. It examines key failure mechanisms, such as gate-oxide degradation and thermo-mechanical aging, at both the chip and package levels. Additionally, the article offers a market-oriented overview of standard power semiconductor packages and insights into current manufacturing trends and their implications for reliability. It also explores Active Thermal Control (ATC) techniques, such as gate voltage modulation, which can be implemented at the user level to mitigate stress-related failures. The findings intend to inform future researchers and developers, ensuring that power electronics systems can meet the increasing demand for reliable, efficient, and safe energy solutions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1036-1067"},"PeriodicalIF":5.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11024189","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144323192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-03DOI: 10.1109/OJPEL.2025.3576296
Anderson A. Dionizio;Leonardo P. Sampaio;Sérgio A. O. da Silva;Vítor Monteiro;João L. Afonso
This paper proposes a novel single-phase integrated inverter for photovoltaic (PV) applications called Hybrid Inverter Zeta-Ćuk (HIZC). The HIZC operates in discontinuous conduction mode and employs four unidirectional power switches, which are achieved by associating series power diodes to MOSFETs. In addition, during the grid’s positive half-cycle, the inverter acts similarly to the Zeta converter. On the other hand, during the negative half-cycle, the inverter operates similarly to the Ćuk converter. Due to the adopted design criteria, the Zeta and the Ćuk operation modes show similar behavior. The small-signals analysis considers the Zeta and Ćuk operation modes, showing a significant similarity between their frequency responses, proofing the similarity of the HIZC’s functionality in both operation modes. The HIZC can boost the voltage of the PV array and perform the DC-AC conversion at the same time. The maximum power available at the PV array is harvested using a multi-loop control in conjunction with the perturb-and-observe algorithm, while an AF-αβ-PLL system guarantees synchronism with the power grid. Experimental results prove the structure feasibility of the proposed topology for PV applications. In addition, the HIZC presents high-efficiency conversion and also low total harmonic distortion in the current injected into the power grid.
{"title":"Hybrid Inverter Zeta-Ćuk for Grid-Tied Photovoltaic Applications","authors":"Anderson A. Dionizio;Leonardo P. Sampaio;Sérgio A. O. da Silva;Vítor Monteiro;João L. Afonso","doi":"10.1109/OJPEL.2025.3576296","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3576296","url":null,"abstract":"This paper proposes a novel single-phase integrated inverter for photovoltaic (PV) applications called Hybrid Inverter Zeta-Ćuk (HIZC). The HIZC operates in discontinuous conduction mode and employs four unidirectional power switches, which are achieved by associating series power diodes to MOSFETs. In addition, during the grid’s positive half-cycle, the inverter acts similarly to the Zeta converter. On the other hand, during the negative half-cycle, the inverter operates similarly to the Ćuk converter. Due to the adopted design criteria, the Zeta and the Ćuk operation modes show similar behavior. The small-signals analysis considers the Zeta and Ćuk operation modes, showing a significant similarity between their frequency responses, proofing the similarity of the HIZC’s functionality in both operation modes. The HIZC can boost the voltage of the PV array and perform the DC-AC conversion at the same time. The maximum power available at the PV array is harvested using a multi-loop control in conjunction with the perturb-and-observe algorithm, while an AF-αβ-PLL system guarantees synchronism with the power grid. Experimental results prove the structure feasibility of the proposed topology for PV applications. In addition, the HIZC presents high-efficiency conversion and also low total harmonic distortion in the current injected into the power grid.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1094-1109"},"PeriodicalIF":5.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11021613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144514470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, SiC planar-gate MOSFET (PG-MOS), SiC short-channel (0.3$mathbf {mu m}$) MOSFET (SCMOS), and SiC JBSFET are tested for the third quadrant I-V temperature characteristics and surge current capability at different gate-source bias voltage. The I-V temperature curves and the TCAD simulation reveal that different device structures exhibit distinct temperature variation trends due to different current conduction paths. The surge test results indicate that SiC PGMOS and SiC SCMOS exhibit bipolar conduction modes at ${mathit{V}}_{mathbf{GS}} = 0$ V and ${mathit{V}}_{mathbf{GS}} = -10$ V. SiC JBSFET operates in a unipolar conduction mode prior to the surge current density threshold of 998.3 $mathbf {A}/mathbf {cm}^{mathbf {2}}$, after which it transitions to a post-bipolar conduction mode, similar to SiC JBS diode. Finally, the failure mechanism is analyzed. The surge current crowding in the edge termination region is a key factor affecting the surge capability of SiC PGMOS. Reducing channel length leads to premature breakdown of the gate-source dielectric layer in SiC SCMOS at ${mathit{V}}_{mathbf{GS}} = 0$ V but enhances the surge ability at ${mathit{V}}_{mathbf{GS}} = -10$ V. The thermal stress induced by the surge current in SiC JBSFET causes large-scale damage to the source metal and cells, resulting in a short circuit between the gate, source, and drain.
{"title":"Investigation of SiC MOSFET Structures for Surge Robustness in the Third Quadrant Under Various $V_{text{GS}}$ Biases","authors":"Xinbin Zhan;Yanjing He;Xi Jiang;Hao Yuan;Qingwen Song;Xiaoyan Tang;Xiaowu Gong;Yuming Zhang","doi":"10.1109/OJPEL.2025.3576381","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3576381","url":null,"abstract":"In this work, SiC planar-gate MOSFET (PG-MOS), SiC short-channel (0.3<inline-formula><tex-math>$mathbf {mu m}$</tex-math></inline-formula>) MOSFET (SCMOS), and SiC JBSFET are tested for the third quadrant I-V temperature characteristics and surge current capability at different gate-source bias voltage. The I-V temperature curves and the TCAD simulation reveal that different device structures exhibit distinct temperature variation trends due to different current conduction paths. The surge test results indicate that SiC PGMOS and SiC SCMOS exhibit bipolar conduction modes at <inline-formula><tex-math>${mathit{V}}_{mathbf{GS}} = 0$</tex-math></inline-formula> V and <inline-formula><tex-math>${mathit{V}}_{mathbf{GS}} = -10$</tex-math></inline-formula> V. SiC JBSFET operates in a unipolar conduction mode prior to the surge current density threshold of 998.3 <inline-formula><tex-math>$mathbf {A}/mathbf {cm}^{mathbf {2}}$</tex-math></inline-formula>, after which it transitions to a post-bipolar conduction mode, similar to SiC JBS diode. Finally, the failure mechanism is analyzed. The surge current crowding in the edge termination region is a key factor affecting the surge capability of SiC PGMOS. Reducing channel length leads to premature breakdown of the gate-source dielectric layer in SiC SCMOS at <inline-formula><tex-math>${mathit{V}}_{mathbf{GS}} = 0$</tex-math></inline-formula> V but enhances the surge ability at <inline-formula><tex-math>${mathit{V}}_{mathbf{GS}} = -10$</tex-math></inline-formula> V. The thermal stress induced by the surge current in SiC JBSFET causes large-scale damage to the source metal and cells, resulting in a short circuit between the gate, source, and drain.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1028-1035"},"PeriodicalIF":5.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11023073","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-03DOI: 10.1109/OJPEL.2025.3576301
Hani Vahedi
This article presents the 5-level Packed U-Cell (PUC5) converter as an active front-end (AFE) rectifier designed to achieve high power quality and power factor correction (PFC) in grid-connected applications. Operating in boost mode, the proposed topology significantly mitigates input current harmonics and enables precise regulation of the DC output voltage, making it well-suited for bidirectional DC systems such as electric vehicle (EV) charging infrastructure with Vehicle-to-Grid (V2G) capability. A detailed analysis of the converter’s switching states is conducted, with a focus on identifying redundant states that can be strategically utilized to balance the voltage of the auxiliary capacitor. This balancing is essential to sustain the five-level voltage waveform at the rectifier input, which in turn minimizes voltage distortion and directly reduces current harmonic content. The output voltage is tightly regulated to supply downstream DC loads with high stability. Experimental validation confirms the effectiveness of the proposed PUC5 rectifier, demonstrating its ability to operate with a near-unity power factor while drawing low-distortion current from the AC grid and maintaining robust dynamic performance under varying load conditions.
{"title":"5-Level Packed U-Cell (PUC5) Active Front-End Rectifier","authors":"Hani Vahedi","doi":"10.1109/OJPEL.2025.3576301","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3576301","url":null,"abstract":"This article presents the 5-level Packed U-Cell (PUC5) converter as an active front-end (AFE) rectifier designed to achieve high power quality and power factor correction (PFC) in grid-connected applications. Operating in boost mode, the proposed topology significantly mitigates input current harmonics and enables precise regulation of the DC output voltage, making it well-suited for bidirectional DC systems such as electric vehicle (EV) charging infrastructure with Vehicle-to-Grid (V2G) capability. A detailed analysis of the converter’s switching states is conducted, with a focus on identifying redundant states that can be strategically utilized to balance the voltage of the auxiliary capacitor. This balancing is essential to sustain the five-level voltage waveform at the rectifier input, which in turn minimizes voltage distortion and directly reduces current harmonic content. The output voltage is tightly regulated to supply downstream DC loads with high stability. Experimental validation confirms the effectiveness of the proposed PUC5 rectifier, demonstrating its ability to operate with a near-unity power factor while drawing low-distortion current from the AC grid and maintaining robust dynamic performance under varying load conditions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"1022-1027"},"PeriodicalIF":5.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11022762","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increase of inverter-based resources, the reduction in grid inertia has become an issue. To overcome this problem, various virtual inertia controls have been proposed. df/dt control is a candidate for practical application since it can be integrated into conventional current controlled inverters. However, df/dt control can make the system unstable under certain conditions. A common solution is to use a low-pass filter (LPF), but there is no clear answer to why df/dt control becomes unstable and the LPF can improve stability. As a result, there are no general design criteria of the LPF for various plants. This paper focuses on the stability of a current-controlled inverter with df/dt-type virtual inertia control. The authors analyze the dynamic characteristics of a synchronous generator and demonstrate the existence of a second-order delay between the frequency of the point of common coupling (PCC) voltage and the speed of the rotor. The result demonstrates an equivalence between this delay and LPF for stabilization in df/dt control. Then, this second-order delay is implemented in df/dt control as an LPF. The influence of this LPF for stability is analyzed by EMT simulations and Bode plot of the entire system. These results illustrate that the LPF is indispensable for df/dt control, and parameters corresponding to synchronous generators can be used as a design criterion of the LPF.
{"title":"Instability and Stabilization Filter of df/dt-Type Virtual Inertia Control Comparing to Synchronous Machines","authors":"Takumi Ueda;Kenichiro Sano;Daisuke Terazono;Kaho Nada","doi":"10.1109/OJPEL.2025.3565697","DOIUrl":"https://doi.org/10.1109/OJPEL.2025.3565697","url":null,"abstract":"With the increase of inverter-based resources, the reduction in grid inertia has become an issue. To overcome this problem, various virtual inertia controls have been proposed. df/dt control is a candidate for practical application since it can be integrated into conventional current controlled inverters. However, df/dt control can make the system unstable under certain conditions. A common solution is to use a low-pass filter (LPF), but there is no clear answer to why df/dt control becomes unstable and the LPF can improve stability. As a result, there are no general design criteria of the LPF for various plants. This paper focuses on the stability of a current-controlled inverter with df/dt-type virtual inertia control. The authors analyze the dynamic characteristics of a synchronous generator and demonstrate the existence of a second-order delay between the frequency of the point of common coupling (PCC) voltage and the speed of the rotor. The result demonstrates an equivalence between this delay and LPF for stabilization in df/dt control. Then, this second-order delay is implemented in df/dt control as an LPF. The influence of this LPF for stability is analyzed by EMT simulations and Bode plot of the entire system. These results illustrate that the LPF is indispensable for df/dt control, and parameters corresponding to synchronous generators can be used as a design criterion of the LPF.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"6 ","pages":"849-857"},"PeriodicalIF":5.0,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10980341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-28DOI: 10.1109/OJPEL.2025.3564717
Tingting Yao;Wenyuan Zhang;Mingfei Ban;Yiqi Liu;Yueshi Guan;Yijie Wang
In this article, a high frequency resonant inverter system with stacked architecture and merging network is analyzed. The design method of multi-resonant circuit is given in detail. The parameter is designed by time domain analysis method which is more accurate than frequency domain method. Based on the single resonant circuit, a stacked topology is analyzed which can greatly reduce the switch voltage stress to almost around the input voltage. Meanwhile, the passive component can be merged to further reduce the number of inductor. Also the soft switching characteristics can be extended from rated resistive load to a range of resistive load by the merged passive network. The detailed operating principle and parameters design method are introduced. A 6.78 MHz experimental prototype is built to verify theoretical analysis and soft switching characteristics can be maintained between 25% to 100% load range and the peak efficiency can be 92.85% .
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